JPS62269424A - Error correction circuit - Google Patents

Abstract

PURPOSE:To speed up the error correction processing by providing the 1st and 2nd storage means storing an error pointer and a means producing the error pointer so as to process the error pointer at each unit series. CONSTITUTION:The titled circuit is provided with the 1 st storage means 116 storing an error pointer corresponding to each symbol data, the 2nd storage means 117 storing the error pointer corresponding to the code series provided in response to the correction stage, and a generating means 103 generating the error pointer from the error pointer of the pre-stage stored in the 2nd stor age means and the error pointer of the 1st storage means. Thus, the error pointer of the code series unit is referenced so as to rewrite the error pointer, thereby omitting the pointer rewrite period substantially having a large share to the cycle time, and the high speed processing more than the double speed is attained, where the number of steps of error correction processing is nearly equal to the code length (n).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an error correction processing circuit in a digital signal recording/reproducing apparatus and transmission apparatus.

2. Description of the Related Art In recent years, audio equipment recorded in a digital signal format, such as compact discs, has been gaining momentum. These digital devices are not only used for audio, but also for
This also extends to video equipment.

Information codes used in computers are also stored and processed in the form of digital signals. These recording/reproducing devices and transmission devices detect errors in the original information signal when errors occur due to dust, scratches on the recording medium, or changes in the state of the transmission path.
An error correction code is added, and error correction processing is performed at the time of regeneration to restore the original information. The aforementioned compact disc employs Reed-Solomon code, which has good coding efficiency and high correction ability.

Next, an overview of Reed-Solomon codes will be explained.

2 elements 0 of expanded Galois field GF(2),
Information points of code length n are mapped to a, α, a, . . . . In a Reed-Solomon code series consisting of k information points and n- check points, the check code generating polynomial is expressed by the following equation.

G(X)=(x+α)(X+α)(X+α)...
...(X〇n-k)... (1) However, α is an example of the primitive light of GF (2), and considering the case where m = 8 and n- = 4, it is 8 pits. Information is treated as one symbol, and a four-symbol check code is added.

Generally, the transmission code word C(x) is an information polynomial I(x).

It is expressed by the following equation, where P(x) is the check polynomial.

C(x)-I(x)・xk+P(x)...
・-(2) C(x) is divisible by the generator polynomial 〇(x),
It has a root α1 (i-1 to n-k).

The received code word R(x) is R(x)-〇(x)+E(x), where the error polynomial is E(x).
It is expressed as −・−(3). Syndrome Si is obtained by substituting α1 into the received code word R(x), and C(x) is α
Since the root is 1, 5i=E(a)(i=1~n−k) −・
...(4). Therefore, in error correction, when the error pattern at location xj is Yj, the error polynomial E(x) is E(x)=ΣY ] X = ・
...Error location α defined in (6)
1 and the error pattern Yj from the syndrome Si.

The error location polynomial σ(X) is expressed by the following equation.

σ(x)-ro(X-σj) ・・・・・・
(6)=X 1σX +・・・・・・+σ6(e:
If αj (number of errors) is determined, the actual error position j can be determined. The relationship between the error location coefficient σ and the syndrome Si is expressed by the following equation.

”i −1−6+σ1Si+e−+””σe−+5i
−z+σeSi−〇 ・Old・・
('r) The solution of the above equation is taken as an example. m=8, n-
The number of errors is calculated for each case of el=1 and e=2.

When e = 1, when θ-2, solving the above simultaneous equations, when 6 = 1, σ, =S2/S, =S, /S2moS4/S3 ・
・・・・・・(@ Syndrome condition: S2 →-s,
s,=.

52s3+S, S4=:Q S5 4-82842〇Si≠0 If el=2, σ1-(S285+8184)/(S2,000S, S3)σ
2=(S, +8., S4)/(S2+S, S,)・
...(11) Syndrome conditions: S, VS2≠S, ≠O82→-S,
S, ≠0 If e≧3, it cannot be solved and the error location is uncertain.

From the obtained error location coefficient σ1, find the root (x=) of the location polynomial σ0C)-0.

When 6=1, σ(x)=x+σ,=○...
・(12),′,X−σ1 If el=2, σ(x)=x +σ, X+σ220 ・Old・・
(13) There are two ways to find the roots in this case. One is to substitute X-αj (j=o~n-1) in order, and j becomes 0.
How to find X-σ, y and y(y+1)-σ2/
There is a method of calculating σ2/σ,' from σ1', obtaining y from the root table, and finally obtaining α3-σ,y.

Once the error location is determined, the error pattern is determined next.

Error pattern es, -ΣEj (/21)j-・-・
(14) If 6=1, ICj=S, bright...(16)6=
In case 2, the actual correction is to add an error pattern to the received symbols (
mod2) is executed.

The following is an overview of error correction using Reed-Solomon codes, and the error correction process can be summarized in terms of each step as follows.

[1] Calculate syndrome Si using equation (4).

[2] Perform calculations to determine the number of errors and obtain the coefficient σ of the error location polynomial using equations (10) and (11).

[3] Solve equations (12) and (13) to obtain the error location polynomial $x3.

[4] (16) Calculate the error pattern using equation (16) and find the error polynomial in equation (5).

[6] Perform error correction based on equation (3).

Next, error correction will be described in more detail using the Reed-Solomon code described above.

Generally, in order to improve the error correction ability, it is effective to prepare a plurality of systems of the above-mentioned Reed-Solomon codes, intersect them and perform correction in order, or repeat this operation. Focusing on one data symbol, for example, if it belongs to two sequences called C1 sequence and 02 sequence that intersect with each other, in order to perform error correction for each 01°C2 sequence, it is necessary to check whether the symbol contains an error or not. A flag (herein referred to as a pointer) is provided to indicate the error, and when the next stage of correction is performed, the pointer based on the previous stage's correction result is referred to and the correction operation is performed. In practice, one bit is assigned to one pointer inverter symbol, and for example, "O" indicates no error and "1" indicates an error, and rewriting is performed each time during a correction operation if necessary. After repeated corrections, if the pointer is 11111 or 1 at the final stage, that data is treated as an error and output is prohibited or an error flag is added.The above is an outline of pointer operations during repeated corrections. .

Next, a specific circuit will be shown and the correction operation will be explained. 8th
The figure is a general configuration diagram of an error correction circuit, and 801 in the figure
802 is a data bus, 8o3 is a syndrome check circuit, 804 is an error correction calculation circuit, 805 is a correction circuit, 806 is a pointer memory, and 807 is an address bus.

Moving on to the operation description, data reproduced from a recording medium or data received from a transmission path is once stored in a data memory 801 in predetermined units via a data bus 802. Once the storage operation is complete, error correction begins. The data read out from the data memory 801 according to the generation code series and the check code added to the data are input to the syndrome check circuit 803 via the data bus 802, and are used to generate the syndrome described in the explanation of Reed-Solomon codes. will be held. Each generated syndrome is input to the error correction calculation circuit 804, which determines the number of errors, calculates the coefficients and roots of the error location polynomial, and outputs an error pattern and error address, as described above. The output error address is address bus 8.
07, the data memory 801 is accessed, error data is read out, and the correction circuit 805 is accessed via the data bus 802.
Enter. The correction circuit 805 adds the error pattern and the error data read from the data memory 801 (m
od2) Perform L correction.

In this correction operation, the data memory 801 and the pointer memory IJ accessed via the common address bus 807
In step 806, a pointer for the current correction operation is generated from a pointer based on the result of determining the number of errors determined from the syndrome condition performed by the error correction calculation circuit 804 and the previous correction result, and is stored. Specifically, for example, if the error correction code is capable of double correction, when the number of errors is determined to be 1, correction is performed and the pointer is cleared. When the number of errors is determined to be 2, it is predicted that there is a high probability of missing by taking into account the number of pointers in the code sequence that are set, and the correction is made, but a new pointer is set and passed to the next stage. Perform operations such as The above is just an example, but three types of pointer operations can be considered: clearing the pointer (when there is no error, when correction is made), setting the pointer (when making correction, when correction is impossible), and "-t to 1". Therefore, when correcting multiple series (01, 02), it is necessary to repeat the operations described in "2" for each series and rewrite the pointer each time.

FIG. 9 is a time chart showing one cycle of correction operation for code length n in the conventional general error correction described in FIG. Syndrome checking requires n clocks, error correction computation requires m clocks, error correction requires one clock (depending on the number of corrections), and pointer rewriting requires n clocks. Therefore, the cycle time for correction of a data string of code length n is 2 n -1-m +1.

Also, during the correction operation, the data bus is occupied during non-drome check and actual correction, and the address bus is occupied during non-drome check, correction, and pointer rewriting.

Problems to be Solved by the Invention In error correction processing using Reed-Solomon codes,
As mentioned above, in the conventional method, the number of processing steps is more than twice the code length, and if this is repeated for each sequence, the total number of steps is: (number of code sequences) x (2 x code length + α). It becomes necessary.

On the other hand, for image signals and computer files that require high-speed processing, both high correction capability and high-speed processing must be achieved. For example, in order to process an image signal in real time, it is necessary to realize error correction at a symbol data rate of at least 1 oMH2 or more.

Therefore, applying the conventional method to that extent is not suitable for the current IS.
This is also difficult from the point of view of operating speed and cost.

Means for Solving the Problems The present invention solves the following two problems by providing a first storage means for storing error pointers corresponding to each symbol data;
a second storage means for storing an error pointer corresponding to a code sequence provided corresponding to the correction stage; an error pointer from the previous stage stored in the second storage means; and the first storage means. and generating means for generating the error pointer from the error pointer.

By using the means described in the operation section, in the correction operation of each stage, the error pointer is not rewritten after the correction process is determined, but the error pointer of the code sequence unit generated during the correction of the previous stage is referenced in parallel when the syndrome is generated. It is possible to rewrite the error pointer, virtually eliminate the pointer rewrite interval that occupies a large part of the cycle time, and perform syndrome checks almost continuously, and the number of steps in the error correction process is approximately equal to the code length n. Equally, high-speed processing that is more than twice as fast as before is possible.

Embodiment FIG. 1 is a block diagram of an error correction circuit according to an embodiment of the present invention. In the figure, 101 is a data memory for storing data and added check codes, 102 is a data bus, 1o3 is a syndrome check circuit, and 1o4 is a data memory for storing data and added check codes. The area within the broken line shows the entire error correction calculation circuit, 105 is a correction circuit that actually performs error correction, 106 is a lunch that stores syndromes, 107 is an address bus, 10B is an error location polynomial coefficient calculation circuit, and 109 is an error location Arithmetic circuit, 110
111 is an error pattern calculation circuit; 111 is a judgment circuit that judges the number of errors and determines pointer processing; 112 is a pointer processing circuit; 113 is a pointer count that calculates the number of error pointers and address pointers; 116 is an address pointer memory, 116 is a pointer memory IJ I that stores an error pointer in symbol data units, 117 is a pointer memory 1 that stores error pointers in code sequence units, 118 is each A multiplexer 119 for switching addresses of the pointer memory is an incremental address generation circuit.

FIG. 2 is an example of a signal format having two code sequences, 01°C2, used in one embodiment of the present invention. At the beginning of each block, a block synchronization (not shown) is followed by a block address (0,...N1...)
is added. The vertical direction in the figure is the block length direction, and data is transmitted or recorded in this order.

Ru. As shown in the figure, the C1 series is composed of data symbols in a diagonal direction going downward to the right, and the C2 series is composed of data symbols in a diagonal direction going downward to the left as shown in the figure, and the check codes generated for each are also within the stream. It can be paid. Therefore, although the increment amount is a distance of ±Δ blocks, this increment does not limit the present invention. The check code to be generated and added is 4 symbols of Reedon Lomon code for both the 01 and 02 series, and can be corrected with double error correction.Since the C1 series is generated including the check code of the C2 series, the correction is It is assumed that the sequences are performed in the order of C1 series and 02 series.

Next, the operation of one embodiment of the present invention will be explained based on FIG. Data and check codes transmitted, recorded and reproduced via the data bus 102 are stored in the data memory 101 in predetermined units. At this time, the block address is also checked by the address check circuit 114, and only the data of the block with the correct address is transferred to the data memory IJ1.
It is stored in 01. The shuffled address check result is stored in address pointer memory 116 as an address pointer.

In the error correction operation, first, a ndroid is generated using a feedback loop, for example, α0. α1. α2. Syndrome generation circuit 1 realized with a feedback register multiplied by α3
It will be held on 03. The nondrome generation result is held at a value of 6 at the moment when syndrome generation for the next block data begins.

An error location polynomial coefficient calculation circuit 108 performs calculations for determining an error location, an error pattern, and an error determination condition on the result of the obtained broadband check. The arithmetic expressions, etc. were described in the section explaining the Reed-Solomon code, so they will be omitted. The obtained calculation result is further sent to the error location calculation circuit 109, and the error location calculation circuit 109
The positions of the one-symbol and two-symbol errors, which are the roots of the Yon polynomial, are determined and returned to the address bus 107 as error addresses.

Further, an error pattern calculation circuit 110 calculates a Nilay pattern from the result of the error location calculation, the sondrome generation output, and the coefficients of the error location polynomial.

Correction of error data is performed by error location calculation circuit 1.
The error address which is the output of 09 is sent to the address bus 107.
and reads out the error data from the data memory 101. The read error data is transferred to data bus 1.
02 to the correction circuit 105. Correction circuit 1
06, the error data and the error pattern output from the error pattern calculation circuit 110 are controlled by the determination circuit 111 (
Addition (InOd2) is performed by a) in the figure and correction is performed.

The above is an overview of the data flow in correction operations.
Pointer operation, which is the key point of the present invention, will be described in detail.

FIG. 3 is a truth table for pointer processing and correction processing showing an example of an error correction algorithm used in the present invention, and is applied to the first correction of the 01 series. Similarly, FIG. 4 is a truth table of pointer processing and correction processing applied to the first and subsequent corrections of the 02 series.

In the first correction of the C1 sequence, first, the determination circuit 111 calculates the number of errors included in the code sequence from the syndrome output (Si=-0, ≠Q, etc.) and the calculation output of the error location polynomial coefficient. Furthermore, address pointer memory 1
The pointer counter 113 counts the number of address pointers included in the same code series read from 16, and performs pointer processing and correction processing depending on the number of errors and the number of address errors (A in the figure). Ru. For example, if the number of errors is °゛0'' and the number of address errors in the sequence is 3 or less, it is assumed that the detection of the number of errors by Reed-Solomon code is sufficiently reliable in terms of probability, and it is assumed that there were no errors. Clear the i~ pointer.If the number of address errors is 4 or more, there is a high possibility that it will be missed, so set a pointer to all the address errors.Even if the number of errors is 2 or more, the cases are divided according to the number of address errors. Then, the error location obtained by calculation is compared with the position of the address pointer (as shown in the figure), and the optimum pointer operation and one symbol correction are performed.

2 Perform correction operations such as number correction. The resulting pointer processing result is written from the determination circuit 111 to the pointer memory 117 as one error pointer for one unit of code sequence (see O in the figure).

The same concept is applied to the first and subsequent corrections of the C2 series in Figure 4, but in addition to referencing the address pointer, reference to the error pointer based on the previous correction result (work in the figure) is added, and the pointer processing As for pointer ``Part 1
A process called "ma" is added.The case where the number of errors is 2 or more is omitted because it has little direct relation to the content of the present invention.

Further, the setting of address errors and the number of error pointers shown in the truth tables of FIGS. 3 and 4 may change depending on the Hamming distance of the code used, the code length, etc., and is merely an example.

In the present invention, according to the pointer processing algorithm of the truth table shown in FIGS. 3 and 4, the pointer, which was conventionally rewritten each time a correction is made, is not rewritten, but new pointer information determined by the determination circuit 111 (O in the figure) is used. Once the pointer memory
117, and during the syndrome generation period in which the address bus is accessed during correction of the next code series, the previous error pointer stored in the pointer memory 117 is read out and a new error pointer is generated in the pointer processing circuit 112. , if the error pointer needs to be updated, a new error pointer is written into the pointer memory 1116 one after another.

FIG. 6 shows a pointer processing circuit 11 which is the key point of the present invention.
2, and the same parts as in FIG. 1 are given the same figure numbers. In the figure, 120 is a decoder, 121 is a NOR gate, 122 is an AND gate, 123 is an inverter, 124
is an OR gate.

FIG. 6 is a truth table for pointer processing, which is the circuit operation of the configuration shown in FIG. In the present invention, the pointer is cleared and the pointer is set up. °'oo'' and ``01'' for the three states of the pointer ``as is''.

A 2-bit flag “10” is assigned.

Moving on to the operation description, in the initial state, correction of one code sequence, for example, the C2 sequence, has already been completed, and the pointer memory 116 has an error pointer for each symbol, and the pointer memory 11 has corrected the C2 sequence. An error pointer for each code sequence is stored, and correction of the C1 sequence is started.

First, address bus 107 is accessed by address counter 106 to generate a syndrome. At the same time, the contents of pointer memory 1116 are also read from output terminal 0. Since the C1 series and the C2 series are interleaved with each other as shown in Fig. 2, when one series is corrected, in order to refer to the pointer for the previous code series stored in the pointer memory 117, it is necessary to It is necessary to perform address conversion in the interleave address generation circuit 119.

To explain address conversion in more detail, the second
From the format shown in the figure, when accessing the i-th symbol of the H-th block during correction of the C1 series, if an address of N+Δi (lower two block address) 1 (lower two block address) is assigned to the address bus, then C2 In order to refer to the series pointer 22, the address of the pointer memory 117 is N+2Δi, and conversely, if the address bus is N-Δill: z position) i (lower) when correcting the C2 series, the pointer memory ■The address of 117 is N-2Δi
becomes. Further, address switching between writing and reading of the pointer memory 117 is performed by a multiplexer 118.

By the address operation described above, the error pointer corresponding to each symbol is stored in the pointer memory 1116. when the syndrome is generated. Read from pointer memory ■117,
A new pointer is generated by pointer processing circuit 112 according to the truth table of FIG.

In the pointer processing circuit 112, first the pointer memory ■11
A 2-bit flag, which is the output of 7, is decoded into three states by a decoder 120. In the figure, (g) indicates the pointer "it'," (ri) indicates the pointer is cleared, and (g) indicates the high level when the pointer is set up. When it is necessary to rewrite the pointer, the NOR gate 121 generates a write enable (WX) signal for the pointer memories 111623.--, and a new pointer (C in the figure) is written from the input terminal (I).

Further, in order to simplify the configuration, the circuit shown in FIG. 6 employs a method of writing the same contents even when the contents of the pointer memo IJ l 116 are unchanged, but this does not limit the present invention. The OR gate 124 outputs the contents of the pointer memory 1116 to the pointer counter 113 according to the contents of the pointer memory. Power).

Through the operations described above, rewriting of the pointer memory 1116 and counting of the number of pointers are executed in parallel with the generation of the broadband. The above operation can be repeated even when repeating correction for different code sequences. A similar operation can be performed when reading the error flag after multiple corrections have been completed. Further, in the initial state, when only address pointer reference is required, this pointer processing is unnecessary.

FIG. 7 is a timing diagram showing the sequence of error correction according to the present invention.As described above, in parallel with the generation of a block, pointers are rewritten and the number of pointers for error determination is counted, and the number of pointers is counted during calculation. It becomes possible to refer to the error pointer that was rewritten during correction execution. Therefore, one cycle of correction can be executed n steps shorter than in the past, making it possible to perform significantly faster processing.

Effects of the Invention In the error correction processing of Reed-Solomon codes, etc., which have multiple types of code sequences, the present invention replaces the conventional process of rewriting the error pointer added every 7 symbols of each data unit after performing correction of one unit sequence. , one error pointer is assigned to each unit sequence, and when generating a pattern for a different code sequence in the next stage, errors necessary for correction are calculated in parallel from the error pointer for each unit sequence in the previous stage and the error pointer for each data symbol. A pointer can be generated, which is effective in speeding up error correction processing.

26 - Therefore, the present invention is highly effective for applications that require high-speed error correction processing, such as real-time processing of image signals and high-speed files for computers.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an error correction circuit according to an embodiment of the present invention, FIG. 2 is a schematic diagram of a signal format used for error correction according to an embodiment of the present invention, and FIGS. 3 and 4 are diagrams according to the present invention. 6 is a block diagram of a pointer processing circuit according to an embodiment of the present invention, FIG. 6 is a truth table diagram, and FIG. 7 is a truth table diagram showing an error correction algorithm according to an embodiment of the present invention. FIG. 8 is a schematic diagram of an error correction circuit according to the prior art, and FIG. 9 is a timing diagram of error correction according to the prior art. 101...Data memory, 103...
Syndrome generation circuit, 108...Error location polynomial coefficient calculation circuit, 109...Error location calculation circuit, 110...Error pattern calculation circuit, 111...Determination circuit, 112
... Pointer processing circuit, 113 ... Pointer counter, 116 ... Pointer memory 1
．． 117... Pointer memory ■. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure □ Block 1 direction Figure 3 (+) Error device and a) Response error a'M force A...-
Minister〈. (++) Ri Hun-Maki. Figure 4 Figure 5 Figure 1? Figure 6

Claims (1)

[Claims] syndrome generating means for generating a syndrome from received data having a plurality of code sequences; a calculating means for calculating an error location and an error pattern from the generated syndrome; and a first error provided for each symbol of the received data. a pointer storage means; a determination means for determining the number of errors and a pointer processing content based on the calculation result of the calculation means and the contents of the first error pointer storage means; and a determination means for storing the pointer processing content in code sequence units. a second error pointer accumulation means for
An error correction circuit comprising: error pointer generation means for generating the error pointer from the first accumulation means and the second accumulation means.