JPH0148594B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image contour processing circuit, and in particular,
The present invention relates to an image contour processing circuit that generates fill information for a character or image (hereinafter referred to as an image) based on contour data of the image.

[Prior art] As a prior art of the present invention, for example, Japanese Patent Application Laid-Open No. 1988-
There is a technique disclosed in Publication No. 142390. In these conventional techniques, in order to fill in the interior of a given image contour, the contour bits determined from the contour data are developed and stored in a bitmap memory, and then the memory is sequentially read out bit by bit. It checks whether the content is a contour bit or not, and sequentially stores images in a separate output refresh memory etc. for the section corresponding to the contour bit detected on the same line from the contour bit of the odd number to the next contour bit. ” information.

[Problems to be Solved by the Invention] Therefore, in this type of conventional apparatus, data processing takes time due to the checking operation to see whether or not it is a contour bit, and high-speed filling processing cannot be performed.

SUMMARY OF THE INVENTION Accordingly, the present invention provides an image contour processing circuit that has a simple configuration and can fill in an image at high speed.

[Means for Solving the Problems] The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a schematic configuration diagram showing an embodiment of an image contour processing circuit according to the present invention.

In the figure, reference numeral 1 denotes a contour bit information generating section that sequentially outputs contour bit information in which one contour bit is set to ``1'' and the other bits are set to ``0'', in units of N bits adjacent to each other on the same line. , a memory 12, an output section 13, and the like.

The decoding unit 11 uses, for example, contour data 14 (in many cases encoded) supplied from the outside.
The bit information corresponding to the contour shape is decoded and reproduced based on the decoding section 11, and the information regarding the contour bit obtained by the decoding section 11 is stored in the memory 12.

Based on the information stored in the memory 12, the output unit 13 generates contour bit information in which the bit corresponding to the contour position is set to, for example, "1" and the other bits are set to "0", and furthermore, the generated contour bit information is is output in units of multiple (N) adjacent bits on the same line.

As will be described later, 2 in FIG. 2 is a fill-in information generating unit equipped with a conversion unit 21 in which N stages of processing units are connected in a cascade, and a latch circuit 22 that temporarily latches the output of the conversion unit 21. and
Based on the N-bit contour bit information supplied from the contour bit information generating section 1, fill-in bit information (N bits) for the section corresponding to the N-bit information is output in parallel.

Reference numeral 3 denotes a write circuit which writes information sequentially outputted from the fill-in information generating section 2 to a predetermined address of the memory 4 to reproduce fill-in data.

Next, a detailed configuration of the filling information generating section 2 is shown in FIG.

In FIG. 1, input bit information A ₁ to A _o is
This is N-digit contour bit information supplied from the contour bit information generating section 1.

Then, corresponding to each input bit information A ₁ to A _o ,
Processing units 5 ₁ to 5n are provided, respectively, and the converting section 21 is constructed by cascading and cascading these processing units as shown in the figure.

Each processing unit 5i inputs arbitrary i-th digit input bit information A _l of the N-bit information supplied from the contour bit information generating section 1 and carry-up information C _l-1 from the previous stage.
An OR (logical sum) circuit that generates the logical sum of the i-th digit as output bit information B _l , the input bit information A _l of the arbitrary i-th digit, and carried information B _l-1 from the previous stage.
It is configured by a combination with an EXOR (exclusive _OR ) circuit that outputs the _{exclusive OR} of 3 and are sequentially stored in the memory 4.

The latch circuit 22 temporarily latches the carry-up information C _o output from the Nth stage (final stage) processing unit 5n, and supplies the latched information to the first stage processing unit _51. Output as advance information C ₀ .

The latch circuit 22 is reset in accordance with a command from the RS terminal each time the operation starts and the processing of one line ends.

[Operation] Next, the operation of the configuration shown in FIGS. 1 and 2 will be explained according to a specific example.

For example, suppose that the contour shape of the image 6 as shown in FIG. 3 is given by the contour data 14.

FIG. 4 is a diagram schematically showing contour bit information on an arbitrary line L _n of the image 6, and shows "1".
corresponds to contour information.

The output section 13 is an arbitrary one as shown in FIG.
Line contour bit information is sequentially output in units of N adjacent bits for each output cycle.

That is, the sections , , in Fig. 4 indicate output cycles when adjacent 8 bits (N = 8) are used as a unit; for example, in the first cycle, a signal "01000000" is input as input bit information A ₁ to A ₈ . The data is supplied to the fill information generation circuit 2.

FIG. 5 shows the relationship between the input/output bit information A, B and the carry-up information C in the conversion section 21.
5 is a state diagram shown corresponding to each cycle in FIG. 4. FIG.

The operation of each cycle will be described below with reference to the state diagram shown in FIG.

Operation in the first cycle: In the initial state of any line, the latch circuit 2
2 has been reset, so C ₀ =0.

Therefore, for the first stage processing unit 5 ₁ , A ₁ =0
B ₁ = 0 by ORing C ₀ = 0 and EXOR
Therefore, C ₁ =0.

The second stage processing unit 5 ₂ has A ₂ = 1 and C ₁ = 0.
B ₂ = 1 by OR, and by EXOR
C ₂ =1.

Next, the processing unit 5 ₃ in the third stage has A ₃ = 0 and C ₂
By OR of =1, B ₃ =1, and by EXOR, C ₃ =1.

From here on, the same situation is repeated until the 8th stage,
C ₈ =1 is taken into the latch circuit 22 and becomes C ₀ for the next cycle.

Operation of the second cycle The processing unit 5 ₁ of the first stage has A ₁ = 0 and C ₀ = 1.
B ₁ = 1 by OR, and by EXOR
C ₁ =1.

The second stage processing unit 5 ₂ has A ₂ = 0 and C ₁ = 1
B ₂ = 1 by OR, and by EXOR
C ₂ =0.

The processing unit 5 ₃ in the third stage has A ₃ = 0 and C ₂ = 0.
B ₃ = 0 by OR, and by EXOR
C ₃ =0.

From here on, repeat the same situation until the 6th stage,
C ₆ =0.

Processing unit 5 ₇ in the seventh stage has A ₇ =1 and C ₆ =0
B ₇ = 1 by OR, and by EXOR
C ₇ =1.

Processing unit 5 ₈ in the 8th stage has A ₈ = 0 and C ₇ = 1
B ₈ = 1 by OR, and by EXOR
C ₈ =1. This C ₈ =1 is taken into the latch circuit 22 as before, and becomes C ₀ for the next cycle.

Operation of the third cycle The processing unit 5 ₁ of the first stage has A ₁ = 0 and C ₀ = 1.
B ₁ = 1 by OR, and by EXOR
C ₁ =1.

From here on, repeat the same situation until the 6th stage,
C ₆ =1.

Processing unit 5 ₇ in the 7th stage has A ₇ = 1 and C ₆ = 1
B ₇ = 1 by OR, and by EXOR
C ₇ =0.

Processing unit 5 ₈ in the 8th stage has A ₈ = 0 and C ₇ = 0
B ₈ = 0 by OR, and by EXOR
C ₈ =0. Then, this C ₈ =0 is taken into the latch circuit 22 in the same way as above, and is used in the next cycle.
C becomes ₀ .

FIG. 6 is a diagram showing the output bit information B ₁ to B ₈ obtained for each cycle described above, following the example of FIG. 4.

As shown in the comparison between Fig. 4 and Fig. 6, the bit information "1" in Fig. 6 is the filling information for the section from the odd-numbered contour bit to the next contour bit in Fig. 4. It's getting old.

That is, the output bit information B forms information in which the inside of the image 6 shown in FIG. 3 is filled in.

[Other Embodiments] In the above explanation related to FIGS. 4 to 6, the case where the number of stages of the processing unit 5 is eight has been described, but the present invention is not limited to this and can be implemented with any number of stages. Of course it is possible.

Then, the configuration and connections of each processing unit 5 are
By constructing as shown in the figure, it is possible to obtain a plurality of digits of information B at the same time in each cycle, and by appropriately increasing the number of stages of the processing unit 5, it becomes possible to obtain fill-in information at extremely high speed.

[Effects of the Invention] As described in detail above, the present invention is an image contour processing circuit that converts contour bit information of an image into fill information; a contour bit information generation unit that sequentially supplies; arbitrary i-th input bit information A _l of the supplied N-bit information;
An OR circuit that generates the logical sum of the carry-up information C _l-1 from the previous stage as the i-th digit output bit information B _l , the input bit information A _l of the arbitrary i-th digit, and the carry-up information B _l from the previous stage. _-1 and an EXOR circuit that outputs the exclusive OR with 1 as carry information C _l to the next stage. A very simple configuration: a latch circuit that latches the carry-up information C _o output from the Nth-stage processing unit and outputs the latched information as carry-up information C ₀ to be supplied to the first-stage processing unit; This circuit is characterized by consisting of the following circuits.

Moreover, by operating each cycle of this simple circuit, it is possible to obtain multiple digits of output bit information B simultaneously, and by using an appropriate number of processing units, it is possible to obtain the desired filling information at extremely high speed. This provides a new processing circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing details of a fill-in information generating section constituting the present invention, FIG. 2 is a schematic configuration diagram showing an embodiment of an image contour processing circuit according to the present invention, and FIG. 3 is an example of an image to be processed. FIG. 4 is a diagram schematically showing an example of contour bit information, FIG. FIG. 6 is a diagram showing fill information corresponding to the outline bit information of FIG. 4. DESCRIPTION OF SYMBOLS 1... Contour bit information generation section, 2... Filling information generation section, 3... Writing circuit, 4... Memory, 5... Processing unit, 6... Image, 11... Decoding section, 12... Memory, 13... Output section, 14...
Contour data, 21... Conversion unit, 22... Latch circuit, A... Input bit information, B... Output bit information, C... Carry information.

Claims (1)

[Scope of Claims] 1. An image contour processing circuit that converts contour bit information of an image into fill information, which converts contour bit information into N adjacent pixels on the same line.
The contour bit information generating section sequentially supplies bits as a unit, and the logical sum of the arbitrary i-th digit input bit information A _l of the supplied N-bit information and the carry-up information C _l-1 from the previous stage is i The OR circuit that generates the output bit information _Bl of the digit, the input bit information _Al of the arbitrary i-th digit, and the carried information Bl _-1 from the previous stage is the exclusive OR of the carried information to the next stage. Output as C _l
A conversion unit configured by connecting an i-th stage processing unit in combination with an EXOR circuit in an N-stage cascade, and carry-up information output from the N-th stage processing unit.
An image contour processing circuit comprising: a latch circuit that latches C _o and outputs the latched information as carry-up information C ₀ to be supplied to a first stage processing unit.