JPH0490196A - Clock pulse detecting circuit - Google Patents

Abstract

PURPOSE:To reduce circuit size and to surely detect only the initial clock signal by using a clocked latch circuit and a logical gate circuit. CONSTITUTION:An initial clocked latch circuit M1 latches the L level NOT logical signal of a select signal, the inverse of CS, based upon a clock pulse signal CLK and an intermediate clocked latch circuit M2 latches an L level latch signal Q1 in response to the leading edge of the signal CLK. A final stage clocked latch circuit M3 latches an L level latch signal Q2 in response to the leading edge of the CLK. A logical gate circuit M4 generates a pulse signal STB synchronized with the 1st clock pulse signal CLK based upon the latch signals Q2, Q3. Since the clocked latch circuit has the smallest circuit size of a circuit for storing data, the circuit size can be extremely reduced as compared with a case using a flip flop circuit.

Description

[Detailed Description of the Invention] [Summary] Regarding a clock pulse detection circuit, it is possible to reduce the circuit scale, and moreover, to reliably generate l-shot synchronized with the rising or falling edge of a desired clock pulse signal counting from the negative logic signal of the selection signal. a first-stage clock latch circuit which inputs a selection signal and a clock pulse signal, and latches and outputs an inverted signal of a negative logic signal based on the clock pulse signal; and a middle-stage clock dratch which inputs the latch signal of the first-stage clock-dratch circuit, and latches and outputs the latch signal of the first-stage clock-dratch circuit based on the rising edge of the clock pulse signal that is first output from the negative logic signal of the selection signal. input the clock pulse signal and the latch signal of the middle-stage clock-dratch circuit, and generate the latch signal of the middle-stage clock-dratch circuit based on the falling edge of the clock pulse signal that is first output from the negative logic signal of the selection signal. A final stage clock latch circuit that latches and outputs the clock pulse signal that is inputted with both the latch signals of the middle stage clock latch circuit and the final stage clock dratch circuit, and that is outputted first from the negative logic signal of the selection signal. It consists of a logic gate circuit that generates synchronized pulse signals.

[Industrial application field] The present invention relates to a clock pulse detection circuit.

In recent years, as LSIs have become faster and more highly integrated, the clock pulse detection circuits used in the information processing circuits of parallel-to-serial conversion shift registers, etc., built into these devices, have become simpler and more reliable. There is a demand for something that does.

[Prior Art] A clock pulse detection circuit is used as an information processing circuit such as a parallel/serial conversion shift register, for example. This parallel/serial conversion shift register is composed of a plurality of (eight in the figure) registers 1 to 8 and an information processing circuit 9, as shown in FIG. And the information processing circuit 9
Parallel data PI-P8 is input to each register 1 to 8 based on the one-shot pulse signal STB from the clock pulse signal (hereinafter referred to as clock signal) C.
In response to the falling edge of LK, parallel data PI-P8 input to each register 1 to 8 is shifted to an adjacent register, and sequentially output from register 8 at the final stage as serial data.

The information processing circuit 9 inputs a selection signal /CS that allows transfer of the clock signal CLK and parallel data PI-P8 to each register 1 to 8, and first after the selection signal /C3 changes from H level to L level. (1st) clock signal C
LK is detected and a pulse signal STB is output to each register 1-8. That is, the information processing circuit 9 is a pulse detection circuit that detects the first clock signal CLK output after the selection signal /C3 changes from the H level to the L level.

In detail, the pulse detection circuit used in the information processing circuit 9 includes three flip-flops FFl-FF3 connected in series as shown in FIG.
The counter circuit consisted of a NOR circuit 10 and inverter circuits 11 to 14. Each flip-flop FF
I to FF3 are edge trigger type set flip-flops, which are set when the selection signal /CS changes from the H level to the L level.

After setting, the flip-flop FF1 at the first stage divides the frequency of the clock signal CLK by 1/2, and as shown in FIG.
It goes to L level based on the rising edge of K, and goes to H level at the rising edge of the second clock signal CLK. Furthermore, the middle stage flip-flop FF2 divides the output Qll of the first stage flip-flop FF1 into 1/2, and its output Q22 becomes L level based on the rise of the first output Qll, and the second output It becomes H level at the rising edge of Qll. Furthermore, the final stage flip-flop FF3 converts the output Q22 of the middle stage flip-flop FF2 to 1.
/2, and its output Q33 is the first output Q2
It becomes L level based on the rise of the second output Q2, and becomes H level when the second output Q2 rises.

Outputs Q11 to Q3 of each flip-flop FFI to FF3
3 except for the output Qll is input to the NOR circuit 10 via the inverter circuits 11 and 12, and the NOR circuit 10 receives the clock signal CLK via the inverter circuit 14.
is being entered. As shown in FIG. 21, the NOR circuit 10 outputs only the first clock signal CLK output after the selection signal /CS changes from the H level to the L level as a pulse signal STB.

[Problems to be Solved by the Invention] However, each of the flip-flops FFl to FF3 used in the clock pulse detection circuit consists of eight NAND circuits 1, 5 to 22 and four inverter circuits, as shown in FIG. 23 to 26, the circuit scale is extremely large. Therefore, the circuit scale of this pulse detection circuit becomes a problem in achieving higher integration of semiconductor integrated devices.

In addition, this pulse detection circuit outputs a pulse signal STB every time the clock signal CLK is input to eight flip-flops FFI at the first stage while the selection signal /CS continues to maintain the L level state. Every time the pulse signal STB is output, new parallel data Pi-P8 will be input to each register 1-8. Moreover, 8
Since it cannot support parallel/serial shift registers with more than 8 bits, it is necessary to increase the number of flip-flop circuits when used in shift registers with more than 8 bits, which leads to an increase in the circuit scale.

Furthermore, since this clock pulse detection circuit outputs the pulse signal STB by calculating the NOR of four people in the NOR circuit IO, the so-called pulse signal STB is output based on the delay operation of each flip-flop FFl-FF3. A "whisker" occurs, and this "whisker" may cause the shift register to malfunction.

The present invention has been made to solve the above-mentioned problems, and its purpose is to reduce the circuit scale (and also to ensure that the desired clock pulse signal rises or rises counting from the negative logic signal of the selection signal). An object of the present invention is to provide a clock pulse detection circuit capable of generating an l-shot pulse signal synchronized with falling.

[Means to solve the problem] FIG. 1 shows a principle diagram for explaining the present invention in detail.

The first stage clock latch circuit M1 receives a selection signal /CS and a clock pulse signal CLK. The clock latch circuit M1 latches and outputs the negative logic signal of the selection signal /CS based on the clock pulse signal CLK, and continues to latch the value until the selection signal /C3 is inverted again.

The middle stage clock latch circuit M2 receives the clock pulse signal C
LK and the latch signal Q of the first stage clock latch circuit M1
Enter 1. The middle stage clock latch circuit M2 latches and outputs the latch signal Q1 of the first stage clock latch circuit M1 based on the rising edge of the clock pulse signal CLK that is first outputted from the negative logic signal of the selection signal /CS.

The final stage clock latch circuit M3 receives the clock pulse signal CLK and the latch signal Q2 of the middle stage clock latch circuit M2. The final stage clock latch circuit M3 latches and outputs the latch signal Q2 of the middle stage clock latch circuit M2 based on the fall of the clock pulse signal CLK that is first output from the negative logic signal of the selection signal /CS.

The logic gate circuit M4 is the middle stage clock latch circuit M.
Both latch signals Q2.2 and final stage clock latch circuit M3. Q3 is input to generate a pulse signal STB that is synchronized with the clock pulse signal CLK that is first output from the negative logic signal of the selection signal /CS.

Therefore, when the selection signal /CS has a negative logic, for example, when it is inverted from H level to L level as shown in FIG. is latched and output as an L-level negative logic signal based on the clock pulse signal CLK. This latch signal Q1 is the selection signal /C
It continues to be latched while S is at L level.

When the first stage clock latch circuit M1 latches the L level state, the middle stage clock latch circuit M2 latches the L level latch signal Q1 of the first stage clock latch circuit M1 in response to the rise of the clock pulse signal CLK. That is, the latch signal Q of the first stage clock latch circuit Ml is adjusted based on the rising edge of the first clock pulse signal CLK output after the selection signal /CS is inverted.
Latch 1. The latch signal Q2 of this middle stage clock latch circuit M2 is the latch signal Q1, that is, the selection signal /
It continues to be latched and output while CS is at L level.

When the middle stage clock latch circuit M2 latches the L level state, the final stage clock latch circuit M2 latches the L level latch signal Q2 of the middle stage clock latch circuit M2 in response to the fall of the clock pulse signal CLK. That is, based on the fall of the first clock pulse signal CLK, the latch signal Q2 of the middle stage clock latch circuit M2 is latched and continues to be output while the selection signal /C3 is at the L level.

Then, the logic gate circuit M4 generates the first clock based on the latch signal Q2 latched at the rising edge of the first clock pulse signal CLK and the latch signal Q3 latched at the falling edge of the first clock pulse signal CLK. Pulse signal STB synchronized with pulse signal CLK
will be generated.

At this time, the first stage, middle stage and final stage clock latch circuit M
Since 1 to M3 are connected in series, the selection signal /
Unless C3 is inverted from the L level to the H level, the latch signals Ql-03 of the first, middle, and final stage clock latch circuits M1-M3 remain unchanged. As a result, the pulse signal STB synchronized with the first clock pulse signal CLK
After is output, unless the selection signal /CS is inverted,
It is not output in response to the clock pulse signal CLK.

In addition, each of the clock latch circuits M1 to M3 has the smallest circuit scale as a circuit that holds data, and for example, as shown in FIG.
OS transistor T3. A clocked inverter INVI consisting of T4 etc. and a latch inverter INV2. INV
3, the circuit scale is much smaller than that of a flip-flop circuit.

[Example] An example embodying the present invention will be described below with reference to the drawings.

FIG. 4 shows a clock pulse detection circuit used in the processing circuit, which is composed of three clock latch circuits (hereinafter simply referred to as latch circuits) 31, 32, 33, a NOR circuit 34, and the like. The first stage latch circuit 31 has a set including a set input terminal (hereinafter simply referred to as a set terminal) S, a data input terminal (hereinafter simply referred to as a data terminal) D, a clock input terminal C1, an inverted clock input terminal CX, and an output terminal Q. The latch circuit has a selection signal /CS on the set terminal S and data terminal, a clock pulse signal (hereinafter simply referred to as a clock signal) CLK on the inverted clock input terminal CX, and a clock signal on the clock input terminal C. CLK and a reverse phase clock pulse signal (
/CLK (hereinafter simply referred to as a reverse phase clock signal) are respectively input.

The latch circuit 31 is explained in detail according to FIG. 6. The latch circuit 31 consists of a data input section and a latch section, and the input section is a PMO connected between the VCC power supply and ground.
S transistors Tll to T13, NMOS transistors T14. It is composed of T15. The gate terminal of this PMOS transistor T11 is connected to the set terminal S, and the gate terminals of the PMOS transistor T12 and NMOS transistor T15 are connected to the data terminal. Further, the PMO8h run transistor T13 is connected to the inverted clock input terminal CX, and the gate terminal of the NMOS transistor T14 is connected to the clock input terminal C. Then, when the selection signal /CS becomes L level, the clock signal CL K becomes L level, and when the reverse phase clock signal /CLK becomes H level, the drain terminal of PMOS transistor T13 and the NMOS transistor T14
An H level output signal is output from the connection point of the train terminal to the latch section.

On the other hand, the latch section uses two inverters INVILINV1
The inverter INV11 inputs the output signal from the data input section, outputs the inverted signal from the output terminal Q, and cooperates with the inverter INV12 to output the same signal. Retain state. The NMOS transistor T16 has its gate terminal connected to the set terminal S, and when the H level selection signal /C3 is input to the set terminal S, it turns on and sets the latch circuit 31 (the output signal of the output terminal Q). is set to H level).

Therefore, when the selection signal /CS is inverted from H level to L level, when the state of clock signal CLK at that time is L level, or when the state of clock signal CLK changes from H level to L level (reverse phase clock signal When /CLK is at L level or changes from H level to L level), an output signal at L level is output from output terminal Q, and the output is held until selection signal /CS is inverted to H level.

This output signal is then input to the middle stage latch circuit 32 via the NOT circuit 35 as the latch signal Ql of the first stage latch circuit 31 at H level.

The middle latch circuit 32 is a latch circuit with a reset that includes a reset input terminal (hereinafter simply referred to as a reset terminal) /R, a data terminal D, a clock input terminal C1, an inverted clock input terminal CX, and an output terminal Q. The latch signal Q1 is input to the /R and data terminals, the reverse phase clock signal /CLK is input to the inverted clock input terminal CX, and the clock signal CLK is input to the clock input terminal C.

The details of this middle-stage latch circuit 32 will be explained according to FIG. 7. The latch circuit 32 consists of a data input part and a latch part, and the input part is a PMOS transistor T17°T18 connected between the VCC power supply and the ground. ．． NMO8
It is composed of l-transistors T19 to T21.

The gate terminals of the PMOS transistor T17 and the NMOS transistor T20 are connected to the data terminal.

Further, the PMOS transistor T18 is connected to the inverted clock input terminal CX, and the gate terminal of the NMOS transistor TI9 is connected to the clock input terminal C. N.M.O.
The gate terminal of the S transistor T21 is the reset terminal /R
It is connected to the.

Then, when the latch signal Q1 becomes H level and the clock signal CLK becomes H level, that is, the first clock signal CLK (hereinafter referred to as the first clock signal) after the selection signal /CS is inverted to L level. When the negative phase clock signal /CLK goes to L level, an L level output signal is output from the connection point between the drain terminal of PMOS transistor T18 and the drain terminal of NMO3I-transistor T19 to the latch section.

On the other hand, the latch part has two inverters INV13°INV
14 and PMOSMOS transistor T22 for reset
The inverter INV13 inputs the output signal from the data input section, outputs the inverted signal from the output terminal Q, and maintains the same output state in cooperation with the inverter INV14. PMOSMOS transistor T
22 gate terminal is connected to the reset terminal /R, and when the L-level latch signal Q1 is input to the reset terminal /R, it turns on and resets the latch circuit 32 (the output signal of the output terminal Q is L-level). ) state.

Therefore, when the latch signal Q1 is inverted from L level to H level, when the first clock signal CLK rises (reverse phase clock signal /C
LK falls), the output terminal Q outputs a high level output signal, and the latch signal Q1 outputs the output signal to the low level.
Retains unless the level is reversed. Then, this output signal is passed through the NOT circuit 36 as the latch signal Q2 of the middle stage latch circuit 32 at L level, and is output to the final stage latch circuit 3.
3 is input. That is, this middle-stage latch circuit 32 outputs the 1 signal that is first output when the selection signal /CS becomes L level.
In response to the rise of the th clock signal CLK, it is inverted and outputs the latch signal Q2 at L level.

The final stage latch circuit 33 has a set terminal S and a data terminal D.
, a latch circuit with a reset comprising a clock input terminal C1, an inverted clock input terminal CX, and an output terminal Q,
The latch signal Q2 is connected to the set terminal S and the data terminal.
However, the clock signal CLK is input to the inverted clock input terminal CX.
However, the clock input terminal C receives a reverse phase clock signal /CLK.
are entered respectively.

This final stage latch circuit 33 is a set latch circuit having the same configuration as the first stage latch circuit 31 shown in FIG. 6, so its details will be omitted.

Therefore, in this case, when the latch signal Q2 is inverted from the H level to the L level and the first clock signal CLK falls (the anti-phase clock signal /CLK rises), the latch circuit 33 at the final stage outputs the output terminal Q. outputs an L level output signal from
The signal is held until it is inverted to H level. This output signal is output via the NOT circuit 37 as a latch signal Q3 of the final stage latch circuit 33 at H level.

That is, the latch circuit 33 at the final stage inverts and outputs the latch signal Q3 at the H level in response to the fall of the first clock signal CLK that is first output when the selection signal /CS goes to the L level. .

The NOR circuit 34 receives the latch signal Q2 and the latch signal Q3.
As shown in FIG. 5, when the latch signal Q2 becomes L level, the latch signal Q3
Until the clock reaches H level, that is, the first clock CL
While K is being output, an H level pulse signal STB is output.

Next, the operation of the clock pulse detection circuit configured as described above will be explained.

Now, when the selection signal /C3 goes from H level to L level,
The first stage latch circuit 31 inverts the state of the clock signal CLK in response to the L level, latches the L level of the selection signal /C3, and sends it to the middle stage latch circuit 32 as an H level latch signal Ql via the NOT circuit 35. For input, the middle stage latch circuit 32 receives the first clock signal C that is first output when the selection signal /CS changes from H level to L level.
It enters the LK detection standby state.

At this time, the middle stage latch circuit 32 is a clock latch circuit with reset, and inputs the clock signal CLK to the tack input terminal C and the reverse phase clock signal /CLK to the inverted clock input terminal CX. In response to the rising edge of the clock signal CLK, it is inverted and latches the first stage latch signal Q1.

Therefore, the middle stage latch circuit 32 detects the rising edge of the first clock signal CLK.

On the other hand, the final stage latch circuit 33 receives the latch signal Q2 of the middle stage latch circuit 32 at L level via the NOT circuit 36, and enters a standby state for detecting the first clock signal CLK. At this time, the final stage latch circuit 33 is a clock latch circuit with a set, and inputs the reverse phase clock signal /CLK to the clock input terminal C and the clock signal CLK to the inverted clock input terminal CX.
In response to the fall of the th clock signal CLK, it is inverted and latches the middle stage latch signal Q2.

Therefore, this final stage latch circuit 33 detects the fall of the first clock signal CLK. Then, the NOR circuit 34 receives the middle and final stage latch signals Q2. The first clock signal CLK based on Q3
A pulse signal STB synchronized with is output.

In this way, in this embodiment, three clock latch circuits 3 are used.
1 to 33 are connected in series, and the latch signal of the first stage latch circuit 31 is sequentially latched by the succeeding latch circuits 32 and 33 based on the clock signal CLK and the reverse phase clock signal /CLK. Clock signal CLK
A pulse (i) synchronized with the lock signal CLK is detected.
The number STB can be output.

Moreover, in this embodiment, the selection signal /C3 changes from L level to H level.
Since each latch circuit 31 to 33 holds the latch signal unless the level is reversed, it is not limited to the information processing circuit 9 used for an 8-bit serial/parallel type shift register, but also for 16-bit and 32-bit shift registers. It can also be used as is in information processing circuits used in serial/parallel type shift registers such as the above, without increasing the circuit scale.

Furthermore, in this embodiment, since the NOR circuit 34 generates the pulse signal STB based on the power of two people from the middle-stage latch circuit 32 and the final-stage latch circuit 33, both latch circuits 34
There is no generation of erroneous signals such as "whiskers" based on the delay operation between 2.33 and 2.33.

In this embodiment, the clock latch circuits 31 to 33 are connected via the knot circuits 35 and 36, but the clock latch circuits 31 to 33 may be connected directly to each other as shown in FIG. . In this case, the clock latch circuit 32 in the middle stage is changed from a clock latch circuit with a reset to a clock latch circuit with a set, and its set terminal S is connected to the output terminal Q of the latch circuit 31 in the first stage. and,
The operation is basically the same as the detection circuit shown in FIG.
As shown in FIG. 9, the middle-stage set clock latch circuit 32 is inverted at the rising edge of the first clock signal CLK to output an L-level latch signal Q2, and the final stage set clock latch circuit 32 is activated. The inversion operation is performed at the falling edge of the first clock signal CLK to output the L-level latch signal Q3, and based on both latch signals Q2 and Q3, the NOR circuit 34 outputs the pulse signal STB.
to be generated.

Therefore, this detection circuit is composed entirely of clocked latch circuits with sets, and the number of not circuits is also reduced, making the circuit scale simpler and smaller (
can do.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. 1O. In contrast to the above embodiment, which detected the first clock signal CLK after the selection signal /C3 was inverted and generated the pulse signal STB that is synchronized with the clock signal CLK, in this embodiment, the selection signal /CS is inverted. After that, the second clock signal CLK is detected and a pulse signal STB synchronized with the clock signal CLK is output.

In FIG. 10, five clocked latch circuits 40 are connected in series, with odd-numbered clocked latch circuits 40
A reverse phase clock signal /CLK is input to the clock input terminal C of the circuit, and a clock signal CLK is input to the inverted clock input terminal CX. Further, the clock input terminal C of the even-numbered clock latch circuit 40 receives the clock signal C.
LK is input to the inverted clock input terminal CX, and an opposite phase clock signal /CLK is input to the inverted clock input terminal CX. Although each of the clock latch circuits 40 uses the clock latch circuit shown in FIG. 3, a set clock latch circuit shown in FIG. 6 may also be used.

Further, the output terminal Q of the fourth clocked latch circuit 40 is connected to the NOR circuit 34, and the output terminal Q of the clocked latch circuit 40 at the final stage (fifth) is connected to the NOR circuit 34 via the NOT circuit 37. It is connected to the.

Therefore, when the selection signal /CS is inverted to the L level and the first stage latch circuit 40 latches the L level, the subsequent latch circuits 40 sequentially respond to the rising or falling edge of the clock signal CLK as shown in FIG. The L level is latched and outputted. Then, the NOR circuit 34 receives the latch signal Q4. of the fourth and fifth latch circuits 40. A pulse signal STB is output based on Q5. At this time, the fourth latch circuit 40 receives the selection signal /C3.
The fifth latch circuit 40 performs a latching operation at the rising edge of the second output clock signal CLK after it is inverted to the L level, and the fifth latch circuit 40 receives the second output clock signal CL.
Since the latch operation is performed at the falling edge of K, the pulse signal S
TB becomes a pulse signal synchronized with the second output clock signal CLK.

Therefore, the clock pulse detection circuit of this embodiment has the same effect as the previous embodiment, can detect the clock signal CLK that is outputted second after the selection signal /CS is inverted, and can detect the clock signal CLK that is outputted second after the selection signal /CS is inverted. It can be output as a pulse signal STB.

FIG. 12 shows a modification of the second embodiment, in which four clocked latch circuits 40 are connected in series, the output terminal Q of the third clocked latch circuit 40 is connected to the NOR circuit 34, and the final The output terminal Q of the clock latch circuit 40 in the fourth stage is connected to the NOR circuit 34 via the NOT circuit 37.

In this case, as is clear from FIG. 13, the third latch circuit 40 latches at the falling edge of the first clock signal CLK output after the selection signal /CS is inverted to L level, and the fourth Since the latch circuit 40 performs a latch operation at the rising edge of the second output clock signal CLK, the pulse signal STB changes from the falling edge of the first clock signal CLK to the second clock signal CLK.
It is a pulse signal that is detected until LK rises, that is, it is synchronized with the second anti-phase clock signal /CLK.

[Third Embodiment] In this embodiment, as shown in FIG. 14, a large number (N) of clock latch circuits 40 are connected in series.

The reverse phase clock signal /CLK is input to the clock input terminal C of the odd-numbered clock latch circuit 40, and the clock signal CLK is input to the inverted clock input terminal CX.

Further, the clock signal CLK is input to the clock input terminal C of the even-numbered clock latch circuit 40, and the reverse phase clock signal /CLK is input to the inverted clock input terminal CX. In this embodiment as well, each clock latch circuit 40 uses the clock latch circuit shown in FIG. 3, but a set clock latch circuit shown in FIG. 6 may also be used.

With this configuration, when the first-stage latch circuit 40 latches the L level as in the previous embodiment, the subsequent latch circuits 40 sequentially respond to the rising or falling edge of the clock signal CLK, as shown in FIG. The L level will be latched. And, for example, the first
As shown in FIG. 6, one input terminal of the NOR circuit 34 is connected to the output terminal Q of the fourth latch circuit 40 via the NOT circuit 37, and the other input terminal is connected to the output terminal Q of the fourth latch circuit 40.
17, the pulse signal STB becomes a pulse signal detected during the period from when the first clock signal CLK rises to when the second clock signal CLK rises.

Therefore, two clock latch circuits 40 are selected as appropriate,
The latch circuit 40 on the latter stage receives the clock signal CLK by connecting the NOR circuit 34 via the NOT circuit 37.
A pulse signal STB synchronized with can be generated at any timing and with any length.

Note that the clock pulse detection circuit of the present invention is not limited to the above-mentioned embodiments, and may be used, for example, in a circuit other than an information processing circuit of a parallel/serial type shift register to detect a desired clock pulse signal and detect the same clock pulse signal. It may also be used in processing circuits that require pulse signals synchronized with.

[Effects of the Invention] As described in detail above, according to the present invention, the circuit scale can be reduced, and only the first clock signal can be reliably detected. Moreover, by appropriately changing the number of clock-dratch circuits connected in series, it is possible to generate one shot pulse signal synchronized with the rise or fall of a desired clock pulse signal, counting from the negative logic signal of the selection signal. Has excellent effects.

[Brief explanation of drawings]

FIG. 1 is a principle diagram showing the principle of the present invention; FIG. 2 is a time chart diagram for explaining the present invention in detail; FIG. 3 is a circuit diagram showing an example of a clock latch circuit used in the present invention; Fig. 4 is an electrical block circuit diagram of a clock pulse detection circuit explaining the first embodiment of the present invention, Fig. 5 is a time chart diagram of the clock pulse detection circuit, and Fig. 6 is an electrical circuit diagram of a clock latch circuit with a set. 7 is an electric circuit diagram of the clock latch circuit with reset, FIG. 8 is an electric block circuit diagram showing a separate clock pulse detection circuit of the first embodiment, and FIG. 9 is an electric circuit diagram of the clock pulse detection circuit of the first embodiment. Figure 10 is an electric block circuit diagram showing the clock pulse detection circuit of the second embodiment. Figure 11 is the same (time chart diagram of the clock pulse detection circuit). Figure 12 is the clock pulse detection circuit diagram of the second embodiment. FIG. 13 is an electric block circuit diagram showing a modified example of the pulse detection circuit; FIG. 13 is a time chart diagram of the clock pulse detection circuit; FIG. 14 is an electric block circuit diagram showing a clock pulse detection circuit of the third embodiment; The figure is a time chart diagram of the clock pulse detection circuit, Figure 16 is a gate circuit diagram that inputs latch signals from the second latch circuit and the fourth latch circuit, and Figure 17 is a time chart diagram at that time. , 18th
The figure is a block circuit diagram for explaining the parallel/serial type shift register, Figure 19 is a time chart diagram for explaining the operation of the parallel/serial type shift register, and Figure 20 is a block circuit diagram for explaining the operation of the parallel/serial type shift register. FIG. 21 is a time chart for explaining the operation of the clock pulse detection circuit; FIG. 22 is a flip-flop circuit diagram with a set used in a conventional clock pulse detection circuit. In the figure, Ml is a first-stage clock-dratch circuit, M2 is a middle-stage clock-dratch circuit, M3 is a final-stage clock-dratch circuit, and M4 is a logic gate circuit.

Claims (1)

[Claims] 1. Selection signal (/CS) and clock pulse signal (CL
a first-stage clock latch circuit (M1) that inputs the clock pulse signal (CLK) and latches and outputs a negative logic signal of the selection signal (/CS) based on the clock pulse signal (CLK); The latch signal (Q1) of the clock latch circuit (M1) is inputted, and the first-stage clock latch circuit ( A middle-stage clock latch circuit (M2) that latches and outputs the latch signal (Q1) of M1), and inputs the clock pulse signal (CLK) and the latch signal (Q2) of the middle-stage clock latch circuit (M2), and A final stage clock that latches and outputs the latch signal (Q2) of the middle stage clock latch circuit (M2) based on the fall of the clock pulse signal (CLK) that is first output from the negative logic signal of the signal (/CS). a latch circuit (M3), and both latch signals (Q2, Q3) of the middle-stage clock-dratch circuit (M2) and the final-stage clock-dratch circuit (M3).
) and a logic gate circuit that generates a pulse signal (STB) that is synchronized with a clock pulse signal (CLK) that is first output from a negative logic signal of the selection signal (/CS). 2. N clocked latch circuits (N is a natural number of 3 or more) are connected in series, and the first-stage clocked latch circuit latches the negative logic signal of the selection signal based on the clock pulse signal. The latch signal is latched and outputted by sequentially inverting the subsequent clock latch circuits in response to the rising or falling edge of the clock pulse signal that is sequentially output, and the jth (j is a natural number from 3 to N) and One shot synchronized with the rising or falling edge of the clock pulse signal by inputting both latch signals of the k-th (k is a natural number from 4 to N greater than j) clock latch circuit and at least the latch signal of the j-th latch circuit. 1. A clock pulse detection circuit comprising a logic gate circuit that generates a pulse signal. 3. A clock pulse detection circuit, wherein the logic gate circuit according to claim 2 generates a pulse signal that rises at the latch signal of the j-th latch circuit and falls at the latch signal of the k-th latch circuit.