JP3475018B2 - Data load circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cascade connection of a plurality of integrated circuits having a holding circuit for holding predetermined bit data, and the predetermined bit data is sequentially transferred from an integrated circuit at the first stage to an integrated circuit at the next stage. The present invention relates to a data load circuit that holds the data.

[0002]

2. Description of the Related Art When a character is displayed on a liquid crystal display, a plasma display, etc., display data for displaying the character (for example, "1" indicates display and "0" indicates no display) is associated with the display position. An integrated circuit which holds and supplies the display to drive the display is used. However, since the number of bits of display data that can be held by one integrated circuit is limited, a plurality of integrated circuits can be connected in cascade to increase the number of bits of display data that can be supplied to the display in parallel at once. I am doing it. For example, assuming that the holding circuit built in one integrated circuit can hold 240-bit display data and the specification is such that 720-bit display data is to be displayed in parallel, three integrated circuits can be connected in cascade. It will be. A conventional data load circuit in which three integrated circuits are cascade-connected will be described below with reference to FIG.

In FIG. 3, reference numerals (1), (2) and (3) denote integrated circuits of the first, second and third stages, respectively, and the integrated circuits (1), (2) and (3) are printed circuit boards. Above, they are connected via wiring (4). First-stage integrated circuit (1)
Incorporates a holding circuit (5), which is capable of holding 240-bit display data, in which 240 D flip-flops (not shown) are connected in cascade. The holding circuit (5) has 8
The display data DATA in units of bits is applied in parallel in synchronization with the clock CLK1, that is, the display data DATA in units of 8 bits is sequentially fetched into the holding circuit (5) in synchronization with 30 clocks CLK1, thereby holding circuits. In (5), 240-bit display data is held in all the D flip-flops. The display data DA
TA is applied to the holding circuit (5) through the 8-bit data bus (6), and the enable terminal EI1 that enables the integrated circuit (1) is low active,
It is grounded. Further, the integrated circuit (1) has a clock C
It has a built-in 5-bit counter (7) for counting LK1 and outputs an overflow signal OF1 which becomes "1" when 30 clocks CLK1 are counted. Further, the integrated circuit (1) contains an AND gate (8) for generating the clock CLK1.
The following three inputs, that is, the state of the enable terminal EI1 and the overflow output OF1 of the counter (7) are inverted and applied to the D gate (8) and the original clock CLK is applied. Therefore, since the enable terminal EI1 of the integrated circuit (1) at the first stage is always fixed at the low level, the generation of the clock CLK1 depends only on the overflow signal OF1 of the counter (7), that is, 30 clocks CLK1 are generated. When the holding circuit (5) finishes holding all 240-bit display data, the overflow signal OF1
Becomes "1", and the generation of the clock CLK1 is stopped from the AND gate (8). As a result, the content of the holding circuit (5) is fixed while the 240-bit display data is held, and the counter (7) is fixed while the overflow signal OF1 of "1" is output. The overflow signal OF1 of the counter (7) is output from the terminal EO1 via the inverter (9). If the overflow signal OF1 is "1", the output of the terminal EO1 becomes an enable signal for the integrated circuit (2) in the second stage. The integrated circuits (1), (2), and (3) receive the load signal LOAD before performing so-called data loading for holding the display data in the holding circuit (5), so that the internal holding circuits (5) and The counter (7) is reset.

Since the second-stage integrated circuit (2) and the third-stage integrated circuit (3) have the same structure as the first-stage integrated circuit (1), internal elements of the integrated circuits (2) and (3) In the same structure as the integrated circuit (1), the same number is given,
The description will be omitted. However, since the integrated circuit (3) of the third stage does not need to generate the enable signal to the next stage, the inverter (9) is omitted.

(10), (11) and (12) are 240 stages of D
Flip-flops, which are integrated circuits (1) and (2), respectively
(3) The contents held in the internal holding circuit (5) are set at the timing to be displayed on the display. The individual D flip-flops constituting the holding circuit (5) of each integrated circuit (1) (2) (3) respectively correspond to 240 individual D flip-flops (10) (11) (12). ing. These D flip-flops (10)
When the load signal LOAD is generated, the contents of the holding circuit (5) at the preceding stage are loaded into (11) and (12), and the counter (7) inside the integrated circuits (1), (2) and (3) is loaded.
Is reset to the initial state.

In the above structure, when 240-bit (= 8-bit × 30) display data is held in the integrated circuit (1) at the first stage, the overflow signal OF1 of the counter (7) becomes “1”. The output of the clock CLK1 from the AND gate (8) is stopped, the content of the holding circuit (5) is held as it is, the counter (7) is stopped, and the output of the terminal EO1 becomes "0".

The output of the terminal EO1 of the integrated circuit (1) in the first stage is applied to the enable terminal EI2 of the integrated circuit (2) in the second stage via the wiring (4). This enable terminal EI2
Becomes low level in accordance with "0" of the terminal EO1, the integrated circuit (2) in the second stage is enabled and the clock CLK2 starts to be generated from the AND gate (8). As a result, the next 240-bit display data is held in the second-stage integrated circuit (2). Then, since the overflow signal OF2 of the counter (7) becomes "1", the output of the clock CLK2 from the AND gate (8) is stopped, the content of the holding circuit (5) is held as it is, and the counter (7) is It is stopped and the output of the terminal EO2 becomes "0".

The output of the terminal EO2 of the integrated circuit (2) of the second stage is applied to the enable terminal EI3 of the integrated circuit (3) of the third stage via the wiring (4). This enable terminal EI
When 3 becomes low level according to "0" of terminal EO2, 3
The integrated circuit (3) at the stage is enabled and AND
The clock CLK3 starts to be generated from the gate (8). As a result, the next 240-bit display data is held in the integrated circuit (2) in the third stage. Then, since the overflow signal OF3 of the counter (7) becomes "1", the output of the clock CLK3 from the AND gate (8) is stopped, the contents of the holding circuit (5) are held as they are, and the counter (7) is turned on. Stop the operation.

The display data held in the integrated circuits (1), (2) and (3) in this way is displayed on the display at a predetermined display timing, so that the D flip-flops (10), (11) and (12) are displayed. Held in.

[0010]

By the way, after the display data is output from the integrated circuits (1), (2) and (3) to the corresponding D flip-flops (10), (11) and (12), the following new data is output. Display data as integrated circuit (1) (2)
In order to be taken in by (3), the integrated signals (1), (2) and (3) and the D flip-flop (1
0) (11) (12) must be reset.

However, even if the integrated circuits (1), (2) and (3) are reset, a time constant circuit is formed due to the resistance and capacitance of the wiring (4), which causes the following problems. That is, the terminals EO of the integrated circuits (1) and (2)
1, EO2 instantly goes to a high level upon reset, but the enable terminals EI2 and EI3 of the integrated circuits (2) and (3) respectively connected to the terminals EO1 and EO2 are instantaneously affected by the time constant of the intervening wiring (4). Can't rise to a high level. In other words, integrated circuit (1)
Even though (2) outputs a high level signal for disabling to the integrated circuits (2) and (3), the enable terminals EI2 and E of the integrated circuits (2) and (3) are used.
Due to the time constant of I3, I3 can rise from the low level to the high level only gradually. As a result, the AND gate (8) of the integrated circuits (2) and (3) is reset based on the time constant. The states of the enable terminals EI2 and EI3, which are recognized as low level, are applied only for a predetermined time. As a result, the clock CLK1 is applied to the integrated circuit (1).
The clocks CLK2 and CLK3 are also applied to the integrated circuits (2) and (3) at the same time that the display data to be written in the holding circuit of the integrated circuit (1) is held in the integrated circuits (2) and (3). Also in the circuit (5), there is a problem that writing is performed for a predetermined time based on the time constant.

Therefore, the present invention aims to solve the problem that a predetermined number of bits of data are erroneously simultaneously written to a plurality of integrated circuits after a plurality of cascaded integrated circuits are reset. And

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is characterized by a holding circuit for holding a predetermined number of bits of data in synchronization with a clock. An integrated circuit including: a detection circuit that detects completion of data holding in the holding circuit; and a clock generation circuit that generates the clock based on an enable signal, an output of the detection circuit, and an original clock. The original clock and the
A fixed number of bits of data are transmitted to the plurality of integrated circuits.
It is applied to the larel and installed in the preceding integrated circuit.
The output of the detected detection circuit is set in the next integrated circuit.
The enable signal applied to the clock generation circuit
The integrated circuits at the previous and next stages so that the
Are connected via a line, after resetting the plurality of integrated circuits to perform a data load, the data load circuit Yuku by the data of the predetermined number of bits are sequentially loaded in the integrated circuits unit, wherein reset the plurality of integrated circuits, in response to the output of the detection circuit provided in the preceding stage of the integrated circuit has become one of the logical value to disable the next stage of the integrated circuit, the following the enable signal applied to said clock generating circuit provided in the stage of the integrated circuit is changed from other logic value depending on the time constant owned by the said wire to one logic value, the next stage of the integrated
The period until the clock generation circuit provided in the circuit recognizes the clock provided in the integrated circuit at the next stage .
The point is that a means for prohibiting the creation of the clock in the lock creating circuit is provided. Further, the means for inhibiting the generation of the clock is configured such that, after resetting the plurality of integrated circuits, the enable signal of each integrated circuit changes from one logical value to another logical value and then from one logical value to the other. Detected that it has changed to a logical value and installed it in each integrated circuit
Of the clock in the clock generation circuit
It is characterized by permitting success .

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit diagram showing a data load circuit of the present invention, and each integrated circuit (1) (2) shown in FIG.
(3) Each is provided inside. In FIG. 1, (13)
Is an enable terminal, and each integrated circuit (1) (2)
This corresponds to the enable terminals EI1, EI2, and EI3 in (3). Reference numeral (14) is a D flip-flop in the previous stage, and its D (data) input is connected to the enable terminal (13) via the two-stage series-connected inverters (15) and (16). (17) is the D flip-flop of the latter stage, and the D terminal is the Q of the D flip-flop (14) of the former stage.
Connected to the (output) terminal. Further, the original clock CLK is commonly applied to the C (clock) terminals of the D flip-flops (14) and (17), and the high active load signal LOAD is inverted and applied to the R (reset) terminal through the inverter (18). To be done. Reference numeral (19) is a NAND gate, which inverts the logical product of the output of the * Q (inverted output) terminal of the D flip-flop (14) and the output of the Q terminal of the D flip-flop (17). The NAND gates (20) and (21) form an RS flip-flop, and one input of the NAND gate (20) serving as a set terminal is connected to the output of the NAND gate (19) and serving as a reset terminal. The load signal LOAD is applied to one of the inputs via the inverter (18). Then, from the output of the NAND gate (21), when the RS flip-flop is set in synchronization with the rising of the original clock CLK, enable signals EI1 ′, EI2 ′, EI that fall from high level to low level are output.
3'is output.

In each integrated circuit (1) (2) (3) of FIG. 3, enable terminals EI1, EI2, EI3 and A are provided.
The circuit of FIG. 1 is provided between the enable terminal of the ND gate (8) and the state input, and EI1 ′, EI2 ′ and EI3 ′, which are the reset outputs of the RS flip-flop, are EI.
Instead of 1, EI2 and EI3, the voltage is applied to the AND gate (8). This operation will be described with reference to the waveform chart of FIG. Note that FIG. 2 shows the waveform of the data retention of the integrated circuits (1) and (2).

First, as an initial setting, the load signal LOA
When D becomes high level and occurs for a predetermined time, the internal parts of the integrated circuits (1), (2) and (3) are initialized. Then, the counter (7) is reset, the output of the terminal EO1 of the integrated circuit (1) rises sharply to the high level, and the integrated circuit (2) of the next stage is going to be disabled. However, the input of the enable terminal EI2 of the integrated circuit (2) is connected to the terminal EO1 of the integrated circuit (1) and the integrated circuit (2).
Even if the terminal EO1 rises sharply, it can only rise gradually due to the time constant of the wiring (4) interposed between the terminal EO1 and the enable terminal EI2. The gradual rising of the enable terminal EI2 is sampled at the rising of the original clock CLK by the circuit of FIG.
5) Even if the change from low level to high level is detected by (16), the output of the RS flip-flop remains at high level. That is, the AND gate (8) of the integrated circuit (2) has an enable terminal EI.
EI2 'is applied instead of the state of 2.
AN of integrated circuit (2) due to the high level of EI2 '
The gate of D gate (8) is closed and CKL2
Does not occur. As a result, while the 8-bit unit data DATA is held in the holding circuit (5) inside the integrated circuit (1), the integrated circuit (2) at the next stage stops the data holding operation and erroneously occurs. It is possible to avoid the disadvantage that the data to be held in the integrated circuit (1) is also held in the integrated circuit (2).

After that, when the counter (7) inside the integrated circuit (1) counts 30 rising edges of the clock CLK1 and outputs the high level overflow signal OF1, the terminal EO1 becomes low level and the integrated circuit (2) is turned on. Attempt to enable. However, the integrated circuit (2) may gradually fall due to the time constant of the wiring (4) between the terminal EO1 of the integrated circuit (1) and the enable terminal EI2 of the integrated circuit (2). Can not. Then, the gradual falling edge of the enable terminal EI2 is sampled at the rising edge of the original clock CLK with the threshold voltage Vth of the inverter (16) as a boundary, whereby the data DATA is integrated circuit (1).
In synchronization with the rising edge of the original clock CLK that occurs at the boundary between the last 8-bit unit data 1-30 to be held in the integrated circuit (2) and the first 8-bit unit data 2-1 to be held in the integrated circuit (2). The output of the RS flip-flop falls to low level. As a result, the AND gate (8) of the integrated circuit (2) opens the gate, the clock CLK2 starts to be generated, and the 8-bit unit data DATA2-1, 2-2,
.. are started to be held in the holding circuit (5) in synchronization with the falling edge of the clock CLK2. The same can be said for this operation between the integrated circuits (2) and (3).

From the above, after resetting the integrated circuits (1), (2) and (3), when the waveforms of the enable terminals EI2 and EI3 rise, the generation of the clocks CLK2 and CLK3 is prohibited, and then the enable terminals EI2 and EI3 are disabled. Since the configuration is such that the generation of the clocks CLK2 and CLK3 is permitted when the waveform falls, the data to be held in the integrated circuit (1) is mistakenly held in the integrated circuits (2) and (3) at the same time. The problem can be solved.

The circuit is not limited to the circuit shown in FIG. 1 and, as in the embodiment of the present invention, after resetting the integrated circuits (1), (2) and (3), the rising edges of the enable terminals EI2 and EI3 are ignored. Any structure may be used as long as it can react to the subsequent fall.

[0020]

According to the present invention, when the enable signals of the plurality of integrated circuits change from one logic value to the other logic value after resetting the plurality of integrated circuits, the integrated circuit of the next stage is obtained. Prohibits clock input to hold data to
After that, when the enable signal changes from the other logic value to one logic value, the clock input is allowed. As a result, there is an advantage that it is possible to solve the problem that the data to be held in the integrated circuit in the first stage is simultaneously and simultaneously held in the integrated circuits in the subsequent stages by mistake.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a data load circuit of the present invention.

FIG. 2 is a waveform diagram showing the operation of FIG.

FIG. 3 is a circuit diagram showing a conventional data load circuit.

[Explanation of symbols]

(1) (2) (3) Integrated circuit (4) Wiring (5) Holding circuit (7) Counter (8) AND gate (14) (17) D flip-flop

Claims (2)

(57) [Claims] 1. A holding circuit for holding a predetermined number of bits of data in synchronism with a clock, a detection circuit for detecting completion of data holding in the holding circuit, and an enable signal,
In order to cascade-connect a plurality of integrated circuits each including an output of the detection circuit and a clock generation circuit that generates the clock based on the original clock, the original clock and
The predetermined number of bits of data to the plurality of integrated circuits
It is applied in parallel to the above
The output of the detection circuit provided in the circuit is the integrated circuit of the next stage.
Before applying to the clock generation circuit provided in the circuit
The integration of the previous stage and the next stage so as to become the enable signal.
Are connected via a wiring circuit, after resetting the plurality of integrated circuits to perform a data load, the data load circuit Yuku by the data of the predetermined number of bits are sequentially loaded in the integrated circuits unit the reset of the plurality of integrated circuits, in response to the output of the detection circuit provided in the preceding stage of the integrated circuit has become one of the logical value to disable the next stage of the integrated circuit, The clock provided in the integrated circuit of the next stage
The enable signal applied to the generating circuit changes from other logic value depending on the time constant owned by the said wire to one logic value is recognized by the clock generating circuit provided in the subsequent stage of the integrated circuit Until the clock generation circuit provided in the integrated circuit of the next stage
A data load circuit comprising means for prohibiting generation of a clock . 2. The means for inhibiting the generation of the clock is configured such that, after resetting the plurality of integrated circuits, the enable signal of each integrated circuit changes from one logic value to another logic value and then one logic value. From the other logic value is detected, and the clock provided in each integrated circuit is detected.
2. The data load circuit according to claim 1, wherein generation of the clock in the clock generation circuit is permitted.