JPH02139629A - Fifo buffer device - Google Patents

Abstract

PURPOSE:To obtain a FIFO buffer device which has such constitution that the device is easily made into one chip by inserting data having a higher priority level before first inputted data having a lower priority level by interruption in accordance with priority levels of data. CONSTITUTION:Priority bits of output data of cells 1 in respective stages and priority bits of external input data are compared by plural comparators 4, and the control of data shift between cells including the control of data selection due to selector circuit parts 2 in cells of respective stages is performed by a control circuit 5 in accordance with outputs of these comparators 4. Data having the same priority level are shifted in order in accordance with the principle of FIFO (first in first out), but interrupt insertion to stages corresponding to priority levels is performed with respect to data having different priority levels. Thus, the FIFO buffer device is easily made into one chip.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a FIFO (first-in, first-out) buffer device, and more particularly to a FIFO buffer device having an interrupt insertion function according to the priority of data.

Conventional techniques and problems to be solved A simple first-in, first-out (FIFO) storage of data can be performed using a shift register or a push-up type stack. However, such a simple method cannot be applied to applications where data from a specific data input source among a plurality of data input sources needs to be processed preferentially.

Conventionally, a software (FIFO buffer device) has not been realized in which data with a higher priority is given priority over data with a lower priority that was input earlier, depending on the priority of the data. Instead, a software polling mechanism is used for FIFO with priority processing. However, in this method, the FIFO data must be expanded onto the RAM, which takes time. Also, F
Since the pit (priority bit) indicating the priority of the FIFO data is detected after the IFO final stage is output and priority processing is performed, the original priority processing is performed, i.e. data with a higher priority is given priority over the input data with a lower priority. This is different from the process of inserting an interrupt before data (on the output stage side).

The present invention has been made in view of the above-mentioned problems, and has a function of inserting data with a high priority according to the priority of the data before the data with a low priority that is input earlier. Hardware FIFO that can be easily integrated into a single chip
The purpose is to provide a buffer device.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention comprises a selector circuit section that selects data from a previous stage or external input data, and a latch circuit section that latches the data selected by the selector circuit section. Cells are connected in multiple stages, the priority bits of the output data of each stage cell and the priority bits of external input data are compared by multiple comparators, and data is selected by the selector circuit section in each stage cell by a control circuit according to the outputs of these comparators. By controlling the data shift between cells, including control of data, data with the same priority is shifted in the order according to the FIFO principle, and data with different priorities is shifted to the stage according to the priority. It has a configuration for inserting interrupts.

Effect When data with the same priority is input sequentially from the outside, the control circuit operates according to the comparison results of each comparator.
In order to have the selector circuit section in each stage cell select the output data of the previous stage cell and shift the data of each stage cell, each input data is sequentially shifted from the first stage cell to the subsequent stage cell according to the input order. go. Therefore, data is output in the same order as it was input.

However, if it is found from the comparison results of each comparator that data with a higher priority has been input than the data that has been input up to that point, the control circuit control so that the selector circuit section in the cell of the stage) selects external input data, causes the cells in a specific stage and subsequent stages to perform a data shift, and then causes the cells in the stage before the specific stage to perform a data shift. .

The same is true when data with various priorities are input sequentially, and the earliest stage (specific stage) where data with a priority equal to or higher than that of the external input data is latched.
The selector circuit section in the cell selects external input data to shift data to cells at a specific stage and subsequent stages, and then shifts data to cells at a stage before the specific stage.

In this way, as for data with the same priority, according to the principle of FIFO, the data input first will be shifted to the next stage and output earlier, but for data with different priorities, the data will be output regardless of the order of input. Data with a high inherent priority is inserted into the next stage (interrupt insertion), and is output earlier in preference to data with a lower priority.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram of a FIFO buffer device according to an embodiment of the present invention. ■ is a plurality of cells connected in multiple stages (L stages), each of which receives output data (consisting of data bits and priority bits) of cell 1 in the previous stage or external input data (consisting of data bits Do, priority bits Lo). It consists of a selector circuit section 2 for selection and a latch circuit section 3 for latching the selected data.

4 is a comparator that compares the priority bit of the output data of each stage cell 1 with the priority bit (Lo) of external input data. Reference numeral 5 denotes a control circuit that controls data shift between cells, including control of data selection of the selector circuit section 2 in each stage cell 1, in accordance with the comparison results of each comparator 3 and the like. 6 is an input handshake circuit for handshaking with the data input source.

As input/output interface signals, the input side includes an input data signal Input DATA, an input clock I nput CK for writing input data, and an input ready signal I n that indicates that the device is capable of inputting data.
put Ready, output side is output data signal 0u
There are tput DATA, an output ready signal 0utput Ready indicating that the output data is valid, and an output clock 0utput CK for data extraction.

The basic timing of these interface signals is as shown in FIG.

A further signal applied to the FIFO buffer device is a shift clock 5hift CK.

As shown in Figure 3, data input from the outside and data shifted within the FIFO buffer device have data bit 11, which is the original data information, and priority bit 11, which indicates its priority (priority level). It consists of 12 bits (pit width is X bits).

FIG. 4 is a block diagram showing the configuration of the cell 1 and the control circuit 5. Although only the n-th stage cell 1, a part of the (n-1)th stage cell 1, and the related control circuit 50 are shown in the figure, the same applies to the other stages.

The latch circuit section 3 in the cell 1 has a latch circuit section 21 for latching data bits, a latch circuit section for latching priority bits, and a latch circuit section 3 for controlling data shift between stages. A latch circuit unit for latching a 1-bit valid/invalid signal indicating whether or not the output data of 21°n is valid (whether or not valid data before being shifted to the next stage is held). have.

A selector circuit unit 2 provided in each stage cell 1 for inserting an interrupt according to the priority of data is a selector circuit unit 2 provided in the cell 1 of each stage, and a selector circuit unit 2 is connected to a selector circuit unit 2 in the previous stage of the selector u1 for selecting the data bit of data from the previous stage or the data bit DO of external input data. Selector 5 to select the priority bit of data from LO or the priority bit LO of external input data, and the valid/invalid signal from the previous stage (this means that the data is valid when “1”, and “0” (meaning that the data is invalid, that is, there is no data) or a "1" signal. In addition, the selector 5 and the comparator 4 can also be made into an integrated circuit (selector/comparator).

The control circuit 5 includes clear control gates 27 and latch circuits 21, 22, . It consists of a gate path for creating a latch clock for Z3, and a decoder 4 that receives the output signal of each comparator 4 and generates a signal for selection control of the selector circuit section 2 of each stage and control of the gate 27. Ru. In addition, games corresponding to each stage) 27.28
may be considered as part of cell l.

Note that for the final stage cell l, as shown in FIG. 8, the latch circuit 21. Each output of Z3 is output data 0
output DATA, output ready signal Out p
It is sent to the outside as u tReady, and the output clock 0output CK becomes the clear signal C(Z) of the latch circuit section.

In this FIFO buffer device, data with a high priority is held in the order of the next stage (data with the same priority is held in the order of input), so if the priority of external input data is in the nth stage. If the priority is equal to or lower than the priority of the data held and higher than the priority of the data held in the (n-1)th stage, the output signals 5(1) to 5 of each comparator 4 input to the decoder 4 S < t) is the fifth
As shown in the figure, all the signals from the n-th stage to the subsequent stages are "0", and all the signals from the stages before it are "L". In this case, the decoder 9 outputs the n-th stage output signal S (n). Only “
1", and all output signals of other stages are "θ".

In the above configuration, a normal data shift operation is as follows. In this case, all output signals of decoder 4 are “0”
It is.

Considering the nth stage cell, the valid/invalid signal A (n)ou
When t is "1" (data valid), the shift clock 5hift CK is masked by the gate 28 and the latch clock GCK (n) is not generated, so the data bit D (n-1) out from the previous stage and the priority bit L
(n-1) out, valid/invalid signal A(n-1)ou
t is not latched by the latch circuits 21, 22, and 23.

The data of the nth stage is shifted to the next stage, the latch circuit section is cleared and the mask by the gate path is released, and the shift clock 5hift CK arrives and the latch clock GCK
Only when (n) occurs, data etc. from the previous stage are shifted and latched to the n-th stage. That is, information on the validity/invalidity of data in each stage is fed back to the previous stage, and data shifting between stages is controlled so as not to destroy valid data held in each stage.

The interrupt insertion operation based on data priority is as follows. Here, it is assumed that data with the priority as described with reference to FIG. 5 (data equal to the priority of the n-th stage held data) is input from the outside.

In this case, only the output signal S (n) of decoder 4 is “1”.
”. That is, a request for interrupt insertion to the n-th stage is generated. As a result, each selector 24, 25, 26 of the selector circuit section 2 in the n-th stage cell selects the B input side, so that the external Data pip) Do and priority pip) of input data
“1” signal indicating Lo and data valid is D (n) in
, L (n) in, A (n) in as the nth
The latch circuits 21, 22, . Z3 is latched (the valid data latched in the nth stage has been shifted to the next stage in advance, and the nth stage is in a state where there is no valid data).

At this time, the latch cross GCK(n) of the n-th stage is masked by the gate (27) corresponding to the (n-1)th stage, and
A clear signal C(n-1) to the latch circuit section of the stage n-1)
1) does not occur, and the valid/invalid signal A(n-1) is “
1", the latch clock GCK(n-1) is not generated because it is masked by the gate (G) 28.The (n-2)th
The same applies to each stage before the stage. That is, when external input data is inserted as an interrupt into the n-th stage, the data in the previous stage is stored without being shifted.

After that, the data held in the n-th stage is shifted to the next stage, and the data in the previous stage is further shifted to the n-th stage (at this point, the output signal S (n) of decoder 4 is "0", so The selection of the n-stage selector circuit section 2 is returned to the A input side).

Normal data shifting is similarly performed at each stage before the (n-1)th stage.

FIG. 6 shows the priority comparison at the time of inserting such an interrupt, the decoding of the comparison result, the timing of determining the nth stage cell input, etc.

FIG. 7 shows the configuration of the input handshake circuit 6, in which reference numeral 31 indicates external input data (including priority bits) Input
t is a latch circuit that latches DATA in response to Input CK and supplies it to each stage cell, 32 is a flip-flop that generates the input ready signal Input Ready, and 32 is a circuit that detects the occurrence of an interrupt insertion request. . Latch clock GC of each stage in this circuit
K (1) to GCK Cl) and the corresponding output signals M(1) to M(Z) of decoder 4 are logically multiplied by AND gates corresponding to each stage, and then the outputs of these AND gates 34 are logically summed. Or game) consists of 35. When a data interrupt request is generated for an arbitrary stage, the output signal of the OR gate becomes "1", and the seventh flip-flop 32 is set, and the input ready signal becomes "0", that is, an input disabled state. There is no interrupt request and the output signal of (or game) 35 is “0”
When the input clock InputCK arrives in the state, the flip-flop 32 is reset and the input ready signal Inp
ut Ready becomes "1" (input ready state).

Effects of the Invention As is clear from the above explanation, the present invention compares the priority of the data held in each stage cell arranged in a multi-stage arrangement with external input data, and adjusts the priority level of each stage cell according to the result of this comparison. By performing control to selectively input data from the previous stage or external input data to the stage and data shifting between stages, data with the same priority is shifted from the first stage cell to the second stage cell in order according to the input order, The original priority processing according to the priority of data is such that data with different priorities are inserted into the next stage regardless of the input order, and data with lower priority is output earlier than data with lower priority. This has the advantage that it is possible to realize a hardware FIFO buffer device that is possible, and that the FIFO buffer device can be easily integrated into a single chip because it is a combination of cells with a simple circuit configuration.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a schematic block diagram of a FIFO buffer device having an interrupt insertion function according to an embodiment of the present invention, FIG. 2 is a timing diagram of input/output interface signals of the FIFO buffer device, and FIG. Figure 4 shows the data structure, Figure 4 is a block diagram showing the configuration of cells and control circuits, Figure 5 is a logical explanation diagram of the decoder, Figure 6 is a timing diagram showing the operation when inserting an interrupt, and Figure 7 8 is a block diagram of the input handshake circuit, and FIG. 8 is a block diagram for explaining the final stage cell circuit and output interface signals. DESCRIPTION OF SYMBOLS 1... Cell, 2... Selector circuit diagram, 3... Latch circuit section, 4... Comparator, 5... Control circuit, 6... Input handshake circuit, 21.22
．． Z3...Latch circuit, 24.25.26...Selector, 4...Decoder. Name of agent: Patent attorney Shigetaka Awano ii! or 1 person

Claims (1)

[Claims] A plurality of cells connected in multiple stages, each consisting of a selector circuit section that selects data from the previous stage or external input data, and a latch circuit section that latches the data selected by the selector circuit section, and the output data of the cells in each stage. a plurality of comparators for comparing the priority bits of the external input data with the priority pits of the external input data; and control of data shift between the cells, including control of data selection by a selector circuit section in each stage cell according to the outputs of these comparators. 1. A FIFO buffer device, characterized in that it has a control circuit that performs interrupt insertion according to the priority of data.