JPS62272713A - Input circuit - Google Patents

Abstract

PURPOSE:To evade malfunction by inhibiting different values of input signals from being sent to circuits of the post-stage to block noise or the like if the values of input signals are not the same consecutively two times or over. CONSTITUTION:When outputs of D flip-flops 1, 2 are not coincident, an output Qc of an exclusive NOR gate 3 goes to '0', resulting that outputs of NAND gates 5, 6 are at logical '1' without fail, then an output Vin' of a flip-flop 7 is unchanged. When the outputs of the D flip-flops 1, 2 are coincident, the output Qc of the exclusive NOR gate 3 goes to '1', the inverse of an S input or the inverse of an R input of the flip-flop 7 goes to '0' by the logical '1' or '0' level of the output Q2 of the D flip-flop 2 and the output Vin' is changed or keeps the preceding state. Thus, so long as a signal having a time width including two leading edges or over of the clock phi is not inputted, the state of the flip-flop 7 is unchanged.

Description

Detailed Description of the Invention V. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an input circuit used as an input section of an electronic device.

[Conventional technology]

As shown in FIG. 4, the electronic device 10 is equipped with an input section, but this input section has noise or chattering in the case of a device using a mechanical switch, so that the input signal is To A.

Disturbances as shown in B often occur. For this reason, an analog filter, an integrator, a one-shot multifunction device, or the like is usually used to deal with this problem.

[Problem that the invention seeks to solve]

However, with the above method, as the pulse width of the noise increases as shown by B in Figure 4, a device with a large time constant is required, which not only makes it expensive, but also increases the delay time, making it impractical. The problem arises that it is not enough.

Therefore, an object of the present invention is to provide an input circuit that is resistant to noise and chatter.

[Means for solving problems]

A flip-flop group consisting of at least two or more 7-lip-flops connected in series and sequentially reading input signals from the outside in synchronization with a reference clock signal, and each output of this flip-flop are introduced to check their coincidence. An exclusive NOR gate for detection and a flip-flop that is set or reset only when a predetermined output is obtained from this gate are provided.

[Effect]

When the input signal is read in synchronization with the clock by the above flip-flop group, the value is not transmitted to the subsequent circuit unless the input signal has the same value two or more times in a row. Also a short width signal,
In other words, noise and the like are blocked to avoid malfunctions.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the same figure, 1.2 is a D-type flip-flop (hereinafter referred to as
It is also simply abbreviated as D-FF. ), the signal input to the D terminal at the rising edge of the reference clock φ, for example, is stored. Of course, it is also possible to use D-FFs 1 and 2 that operate at the falling edge of the reference clock φ. 3 is an exclusive NOR gate, and if the values of the outputs Q1sQ2 of the D-FF input to it are equal, *(Ql, Ql-1, or Ql).

Qz-0) Hiro"1#, or 60"' if unequal
Output each. 4 is an inverter gate, and 5.6 is a Nant gate. 7 is a reset cell) (R8) Flip-flop, this is the S input.

Although the type that changes the state when each n input is "0" is used, it may be of the type that changes the state when each input is "1". In that case, the Nant gates 5 and 6 are replaced with AND gates.

@Figure 2 is a time chart for explaining the operation of Figure 1. Now, assuming that the ripple signal φ and the input signal Vln are shown as shown in (A) and (0) in the same figure, respectively, the outputs Q1 and Ql of D-FF1 and D-FF2 are as shown in the figure (A) and (0), respectively.
c), (d).

If the outputs of D-FF1 and D-FF2 do not match, the output Qc of the exclusive NOR gate 3 becomes "0#" as shown in the figure (E), and as a result, the output of the Nant gate 5.6 is always "1". '', so the output V of flip-flop 7 is
ln' is unchanged and maintains its previous state.

On the other hand, if the outputs of D -FFi,2 match,
The output Q0 of the exclusive NOR gate 6 is 11", and in this case, the output Q2 of the D-FF2 is ul" or 1
0'' causes the S input or the R input of the flip-flop 7 to become '0'', and its output Vin' changes accordingly or maintains its previous state. In addition, (f), ()) and (c) in the same figure are flip-flops 7, respectively.
The S input signal, the n input signal, and the output signal Vin' are shown.

Therefore, in this embodiment, unless a signal having a time width including two or more rising edges of clock φ is input, the output Qc of the exclusive NOR gate 3 will not become @1'', and the flip-flop 7 The state of Exclusive Noah Gate 3 remains unchanged.
By using the output Q0 of the flip 70 as a control signal for setting and resetting the knob 7 of the flip 70, noise and the like can be prevented. In this way,
Since a signal from which noise and the like have been removed is obtained from the output of the flip-flop 7, malfunction of the circuit can be avoided by guiding this signal to the subsequent circuit.

In the above, the number of stages of the D-FF is set to two, but generally it is set to n stages (n≧2, an integer), and a wide exclusive NOR gate, such as the one shown in Fig. 3, is used. By inputting the outputs of all D-FFs to this gate, it is possible to cut out noise having a time width shorter than (n-1) times the clock width. It should be noted that FIG. 3 is a circuit diagram showing an example of an exclusive NOR gate, and the supplementary information regarding this is as follows.

That is, this exclusive NOR gate is composed of an n-input AND gate 5a, an n-input COR gate 3b, and a two-man OR gate 5C. AND gate 3a and NOAG) 5b has n D-FF output Q 1s
Q2...Qn is input, and goo) 5a
The output is 1'' only when all tjn inputs are 11, and the output of 5b is 1 only when all n inputs are 0, so from 5C, Qt
a Q2... When all Qn are equal (
Only when there is a match), an output of 11' is obtained.

It goes without saying that the D-FF' mentioned above may be of any type as long as it operates in synchronization with the clock.

〔Effect of the invention〕

According to this invention, by using a plurality of flips 7 and an exclusive NOR gate that operate in synchronization with a reference clock signal, a signal having a time width at least shorter than the period of the reference clock signal is generated. Since the signal is not transmitted to the next-stage circuit, it is possible to avoid noise, chuckling, etc., and the advantage of providing a highly reliable input circuit is also increased.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an embodiment of Jin's invention, and Figure 2 is a block diagram showing the embodiment of Jin's invention.
Figure 3 is a circuit diagram showing an example of an exclusive NOR gate in a broad sense.
FIG. 4 is an explanatory diagram of rounding to illustrate a conventional example. Symbol explanation 1.2...D type flip-flop, 3...
・・Exclusipnoag)、3a・・・・・・n
Input power and gut, 3b...n entry gate, 3c...or gate, 4...inverter gate, 5.6...song nant gate, 7...
・Flip-flop, 10...Electronic device. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki Figure 1 ≠ Figure 2 Figure Vl: W'
-Figure 3 Figure 41! l (a)

Claims (1)

[Claims] Introducing a group of flip-flops configured by cascading at least two flip-flops and sequentially reading external input signals in synchronization with a reference clock signal, and each output of the flip-flops. and a flip-flop that is set or reset only when a predetermined output is obtained from the gate, and has a time width shorter than at least the period of the reference clock signal. An input circuit characterized in that it blocks an input signal that has an input signal.