JPH02242316A - Key scanning circuit - Google Patents

Abstract

PURPOSE:To decrease the power consumption by executing key scanning only when there is a key input. CONSTITUTION:A clock CK supplied from the outside is counted by a counter 2 through an SEQ 11 and an AND gate 1, decoded by a decoder 3, and used as a scanning signal through an OR gate 4 and an open drain buffer group 5. An output SCAN of the SEQ 11 comes to an H level only at the timing of key-scanning, and except the scanning time, counting of the counter 2 is stopped. Also, the counter 2 is reset through an inverter 12, and also, the scanning signal is all set to an L level.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a scan signal as an oven drain output,
This invention relates to a key scanning circuit in which a plurality of keys are arranged in a matrix using a return signal as a pull-up input, and generates corresponding pressed key data according to the pressed state of a key.

[Summary of the Invention] In order to reduce current consumption, the present invention normally stops scanning while waiting for key input, and transmits the scan signal to
All outputs are rLJ. Here, when a key is pressed, the return line corresponding to the pressed key becomes "L", so
As a trigger in this state, scanning is started and data is generated depending on the state of the pressed key. Thereafter, when it is confirmed that the key is turned off, the process returns to the key input waiting state.

In addition, in order to eliminate the need for an external reset switch, the present invention provides the following features: By pressing multiple keys on the key matrix simultaneously,
It has a function to generate a reset signal.

[Conventional technology]

Conventionally, the key scan circuit is always in operation, and a certain amount of current is constantly consumed.

Further, normally, the reset switch of the device is not arranged on the key matrix but is prepared separately.

[Problem 1 to be solved by the invention: When performing a constant key scan, a certain amount of current is always consumed. It becomes a problem.

Further, providing a reset switch other than the key matrix poses problems in terms of space, reliability, waterproofness, etc. in devices such as battery-powered portable devices.

[Means for Solving the Problems] The present invention aims to minimize the current consumption due to key scanning (when no key is pressed, the scan clock is stopped, and only when a key is pressed, Perform a key scan.

Also, by pressing multiple keys on the key matrix at the same time,
By generating a reset signal, it is possible to omit a reset switch from the device configuration.

[Operation] As described above, in the circuit according to the present invention, there is no change in the signal within the circuit in the key input waiting state, and the consumed current is suppressed to a minimum.

Furthermore, by omitting the reset switch, the number of parts can be reduced, resulting in advantages in terms of space, reliability, and cost. Furthermore, since the reset signal is generated by pressing multiple keys simultaneously, there is less risk of erroneous operation.

[Example] Below, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram of an embodiment of the invention. First, let's explain the scanning side of the key.

The clock CK supplied from the outside is 5EQt 1,
It is connected to a counter 2 via an AND gate 1. The signal KSCo"i whose frequency is divided by 8 by the counter 2 is divided into 8 signals IKS0 to IKS7 by the 3-8 decoder 3. IK
The S, -7 signals become scan signals 80-7 via the OR gate group 4 and the oven drain buffer group 5.

The output 5CAN signal of 5EQI 1 is a signal that becomes rHJ during key scanning, and is connected to AND gate 1 to stop supplying clock CK to counter 2 except during scanning. Also, via the inverter 12, it is connected to the reset of the counter 2 and the OR gate group 4, and resets the counter 2 except during scanning, and all the scan signals 80 to 7 are
Set to "L".

Next, I will explain the return side. Return signal R0~, is
Connected to pull-up input buffer group 6. The output RRo-e of the pull-up input buffer group 6 is connected to a priority encoder 7. The signal K E N o ~ 3 encoded by the priority encoder 7 is K
It is latched together with S Co~2 into the primary latch 8 by the KDASET signal. Output KDA of primary latch 8, ~
, are latched in the secondary latch 9 by the KDBSET signal, and the output of the secondary latch 9 is the 3-step buffer group 1.
0, the key data KD, . . .

5EQI 1 includes CK, KSC, ~2, and IK
S ,-, and K E N ,-, and RR,-, and
KDA0~. and KDRD signals are supplied, and 5CAN and
Generate KDASET, KDBSET, and RST signals.

2 and 3 are detailed internal circuit diagrams of 5EQll, which is an embodiment of the present invention.

Return signals RR, . . . are connected to gates 13 and 15. The output KON of the gate 13 is a signal indicating a key press state in which rHJ occurs when any one of RR, . . . , is rI-J. The KON signal sets the F/F 24, passes through the gate 18, resets the F/F 27, resets the counter 30 via the gate 22, and sets the F/F 24 through the gate 18.
, gate 39 , and gate 36 . game h1
5 is supplied with RR, -, and CK, and detects the case where only a specific return line is rLJ, and CK r)! 5PK at J
The 5PKF signal with the F signal set to "H" is connected to gate 16, gate 17, and gate 19. gate 16
is an AND gate of 5PKF and IKS, and the output is,
Set F/F 25. Gate 17 is an AND gate of 5PKF, the output of F/F25, and IKS.
Set F/F26 at output. Gate 19 is SP
The output of KF, the output of F/F 26, and the AND gate of IKSs sets F/F 27. counter 30
is a counter that confirms key-off, and counts IKS, and when it counts up, sets F/F 28. The output of the F/F 28 is a KRST signal representing key-off, which resets the F/F 25 and F/F 26 through the gate 20, resets the F/F 24 through the gates 1-14, and resets the F/F 24 through the gate 23. and reset F/F29,
Resetting the F/F 43 through the gate 38, resetting the F/F 43 through the gate 38 and the gate 41, and resetting the F/F 42.4 through the gate 38 and the gate 41.
4.45 reset.

F/F 24 is set at KON= rHJ, R5
The flip-flop is reset by the T signal and the KRST signal, and the output 5CAN signal is a signal that operates the key scan counter at the output mentioned above.

For F/F 27, when the outputs of F/F 25 and F/F 26 are rH, 5PKF is rH at the timing of IKS8.
It is set when the key is off, that is, KON=rL
”, the output R5T
The signal is a signal detected when three specific keys are pressed at the same time, and is used as a reset signal for the entire device.

F/F 29 is a flip-flop that indicates that a normal key other than the reset key has been pressed, and latches the inverted output of F/F 27 at the falling edge of I K S t to 0R.
Outputs the DK signal.

The match detection 31 detects the data of the pressed key (KENo
-s, KSC, -,) and the key data (KDAO~7) registered in the primary latch. If they match, the match signal becomes rH4. The match signal is
Gate 34 is used as a condition for key data registration.
It is connected to the gate 35 via the gate 32 and the gate 39 as well.

F/F 42 is a flag indicating whether key data is registered in the primary latch, and is generated according to the conditions of gates 32 and 33. Set by KDASET signal,
Logical sum L of RST signal, KRST signal, and KDRD signal
It is reset by the TR3T signal.

F/F 43 is a flag that indicates the state when the key is pressed continuously, and the conditions set by gates 35, 36, 37, and 39 are
It is latched at the rising edge of CK and outputs the 05IF signal.

F/F 44 and F/F 45 are flags indicating whether or not key data is registered in the secondary latch.
．． It is set based on 40 conditions.

FIG. 4 is a flowchart of key scanning, key data registration, and reset output in the embodiment of the present invention. The following description will be made based on the flowchart and the drawings of the embodiments.

While waiting for key input, scan signals S0 to . are all “
When the key is pressed, one of the return signals R0 to R9 is output.

Since the signal becomes "L", the KON signal becomes rHJ, and the 5CAN signal also becomes rH, the counter 2 operates, scanning is started, and signals 80 to 7 start to become rLJ one by one. Also, since KON=rHJ, the OFF counter 30 is reset.

If the pressed key is not the key set for the reset signal, after one scan, at the falling edge of IKS7, 0
In the 6th scan when RDK = rHJ, the primary latch registration flag is "L", so the conditions for registering to the -th latch are met, KDASET becomes rHJ, and the corresponding key data is registered to the -th latch. .

In the next scan, it was confirmed that the -order latch and the input key data matched, and it was registered in the secondary latch as KDBSET=rHJ, and 0SIF=rH.

In subsequent scans, if no other key is pressed and the key is not turned off, match = rHj, - next empty = r
NOJ, secondary empty = rNOJ, no change in state.

Here, when the key is turned off, R0 ~ becomes "rH",
○The FF counter 30 is currented every scan. When the OFF counter 30 counts up, KR
The 3T signal becomes rH4, and the 0RDK, 03IF, and signals become rLJ.

OFF counter 30 and F/F 24.25, 26.4
2.44.45 and stop scanning.

The above is the normal key registration flow.

Next, the flow of the reset signal will be explained.6 In the present invention, three keys on the same return line on the key matrix are set in advance as special keys for generating the reset signal. Even if these keys are pressed one by one or two at the same time, they will operate in the same way as a normal key input, but if three of these keys are pressed at the same time, a reset signal will be generated. If the three corresponding buttons are pressed at the same time, one flag in particular becomes rHJ during one scan, which is the earliest scan, IKS. (F/F25) Next, at the timing of IKS3, especially flag 2 becomes rH, (F/F
26) Next, at the timing of IKS, the R3T signal is
It becomes rJ.

When the R5T signal becomes rHJ, the scan is also stopped and the scan signals S0 to . are all rLJ outputs. Therefore, as long as any of the keys is pressed, the R5T signal remains in the rHJ state.

Once the key is turned off, the R3T signal becomes rLJ and the state shifts to a key input waiting state.

[Effects of the Invention] According to the present invention, current consumption can be minimized in the key input waiting state, so that it can be used in devices expected to have low power consumption, such as battery-powered portable devices.

Further, since the reset switch can be provided on the key matrix, it is possible to omit the reset switch from the device configuration, which is advantageous in terms of space, reliability, cost, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the key scan circuit of the present invention, FIGS. 2 and 3 are circuit diagrams of the sequencer section of the embodiment of FIG. 1, and FIG. FIG. 2 is a flowchart of key scanning, key data registration, and reset output in the embodiment. 1 ・ ・ ・ ・ 2 ・ ・ ・ 3 ・ ・ ・ 4 ・ ・ ・ 5 ・ ・ ・ 6 ・ ・ ・ 7 ・ ・ ・ ・ 8 ・ ・ ・ ・ 9 ・ ・ ・1 l ・ ・ ・ ・ 12 ・ ・ ・ ・ 13-23 ・ 24-29 ・ 30 ・ ・ ・ ・ 31 ・ ・ ・ ・ ・AND gate counter ・3-8 decoder ・OR gate group ・Oven drain buffer group ・Pull Up input buffer group, priority encoder, primary latch, secondary latch, 3-step buffer group, SEQ, inverter, gate, F/F, counter, match detection 32 to 41, gates 42 to 45, F/F Applicant: Seiko Electronic Industries Co., Ltd. Agent Patent Attorney: Takayuki Hayashi, Figure 2

Claims (2)

[Claims] (1) A key scan circuit that normally stops scanning and scans only when there is a key input, thereby reducing current consumption. (2) The key scan circuit according to claim 1, wherein a reset signal is generated by pressing a specific key at a plurality of locations at the same time.