JPS60214141A - Decoding circuit - Google Patents

Abstract

PURPOSE:To prevent mis-detection by storing input data and detecting a BnZS coded pattern included in the data to allow the detected output to interrupt an external output of the BnZS coded pattern. CONSTITUTION:A positive and a negative pattern of bipolar patterns fed to terminals 21, 22 are fed respectively to storage sections 30, 31, converted into a unipolar signal by a bipolar/unipolar converting circuit 20 and after the result is stored into a storage section 32, and when this pattern is not the BnZS pattern, it is transmitted externally from a terminal 23 via a gate circuit 34. When a BnZS detecting section 19 detects the BnZS coded pattern, its detected output controls a switch section 41 to block an external output of the BnZS coded pattern in the data. Thus, even when a VB0VB pattern comes just after the BnZS coded pattern, no 0 conversion is applied and mis-detection is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a decoding circuit, and in particular is used to decode a pattern in which a continuous 0 pattern is converted into a 1,0 pattern using a BnZS encoding pattern. This relates to a decoding circuit.

(b) Prior art and problems In general, if there are consecutive O's in the data, it is not possible to extract the clock, so the transmitting side extracts the pattern of that part by 1,
Converting to a 0 pattern and transmitting it is widely practiced.

BnZS encoding is one of the 1,0 pattern conversion methods.
This is a method of converting into a code in which B and (2) are appropriately combined. The conversion method will be explained by taking as an example a case where n=8, that is, a B8ZS code 000VB OVB pattern consisting of 8 bits.

Note that ■ indicates 1 due to violation, and B indicates 1.

First, a bipolar pattern of 8 consecutive 0 bits can be expressed as follows.

Positive electrode side oooooooo.

Negative electrode side oooooooo.

Next, B12. To convert to the S pattern, set the first V to the same polar side as the last l, the first (7) B to the opposite polarity to the first V, and the second ■ to the same polarity as the first B. If the polarity of the second B is set to 1 so that the polarity is opposite to that of the second V, the above bipolar pattern of 8 consecutive bits O is converted as follows.

Positive electrode (rule 1・・00010001 Negative electrode 14. 0...OO001010 However,... 1: Leather is the conversion pattern.

...-)j, on the receiving side, the converted 1, 0 pattern must be decoded to extract the original 00 continuous pattern.

FIG. 1 shows a conventional example of a B8ZS decoding circuit.

In the figure, 1 to 8 and 11-18 are flip-flop circuits, one is a B8ZS pattern detection circuit, 20 is a bipolar pattern converter circuit, and 21 to 23 are terminals, respectively.

FIG. 2 is a diagram for explaining the operation of FIG. 1.

The operation of the B8ZS decoding circuit shown in FIG. 1 is as follows.

For example, the positive and negative sides of a bipolar pattern are applied to the terminals 21 and 22, respectively. This pattern is a flip-flop: 8 bits are stored in each of the circuits 1 to 8 and 11 to 18, which are then shifted one after another to pass through the bipolar/unipolar conversion circuit 20 and exit from the terminal 23. Part 2 will be sent out.

Here, the B8ZS bang detection section 19 detects the B8ZS
When a pattern is detected, the output from the detection unit 19 of 1 and - is cleared for each flip, note, Il, and I+.
Using the information stored in -1- for d+completeCL,
The A conversion circuit 20 outputs O with 8 consecutive hits.

On the other hand, the T38ZS pattern detection circuit 19 uses a logic circuit composed of, for example, a NAND circuit to detect B 8 ,
The S pattern is being detected, but as shown in Fig. (for simplicity, consider one side).

When this [j circuit 19 detects that the pattern of pinot l□N0.1~) is a B8ZS pattern, it sends the detection output to all flip-flops 8 and 11-11(Q)C.
In addition to the I terminal, all the stored information is set to 0, so a bang (1, Nimru) as shown in Figure 2 (■) is generated.

Next, the F38 Z S pattern detector 19 detects the bin IN (
1.

2 to 9.3-10 is shifted one bit at a time to check whether the pattern is a B 8 Z S pattern, but the bits are shifted by 1 bit to 3-10. 6 to 13 have a B8ZS pattern, so this pattern is converted to 0.

However, VBOVT3 of 7, Hiso 1-No, 9-13 is not originally) 38 Z S pattern, but bit No. 1~
Since 8 was converted to 0, the second bit is N0. The pattern 6-13 has become a B8ZS pattern, and by setting it to 0, information on via No. 9 and 13 will be lost.

In other words, if VBOVB follows the B8ZS pattern, VB
There was a problem that OVH information was lost.

(C) Object of the Invention The present invention has been made in view of the problems of the prior art as described above.
OV B... pattern comes - C also does not perform O conversion -
The purpose is to provide a υ circuit.

(d) Structure of the Invention 1 - The purpose of the invention is to manually record the date and time of a storage section and write it in the storage section 4.
The Bn in the
6. Disable transmission of ZS encoding pattern. This is achieved by providing a decoding circuit characterized by comprising two switch sections.

tel　Embodiments of the invention FIG. 3 shows an embodiment of the invention.

In the figure, 19 is a B 8 Z S pattern detection circuit, 20
is a bipolar/unipolar conversion circuit, and 30 to 32 are 4
A bit shift register (storage part), 33 a game 1/control circuit, 34 a game 1 circuit, 41 a switch part,
21 to 23 indicate the terminals, and Figure 4 shows the terminals.
FIG. 3 is a diagram for explaining the operation of the diagram.

The operation of the decoding circuit shown in FIG. 3 is as follows.

As mentioned above, terminals 21 and 22? , this is added), - The patterns on the positive and negative sides of the hypolabata are not included.
, added to 4 pi1~shift register 30 and :31,
After being converted to unipolar by the hyperpolar/unipolar conversion circuit 20, if this pattern is not a B8ZS pattern, it is sent to the outside from the terminal 23 via the gate circuit 34.

Note that the B8ZS pattern is detected by a B8ZS pattern detection circuit 19 composed of, for example, a JK flip-flop circuit (not shown) and a gate circuit (not shown).
In order to find the above V, the 4-bit shift register 30~
32, the previous state is stored in the LK flip-flop circuit, and the position of 1 among the 8 bits is detected in the gate circuit. Then, based on this information, it is checked whether the pattern added to this detection circuit 19 is a B8ZS pattern.

When the B8ZS pattern is detected, the gate control circuit 33 is driven by this detection signal, and the gate control circuit 33 is activated for 8 bits.
4 will be rejected. There it is decoded to the original pattern.

In the present invention, as shown in Figure 4 (■), the information stored in the 4-bit shift register is not converted to
Keeping the pattern of OVB O, change this pattern to figure 4■
, ■, the B8ZS pattern is detected by shifting one bit at a time.

Incidentally, although the above explanation has been made only regarding the B8ZS pattern, it goes without saying that even a pattern starting from the B6ZS pattern can be used in a circuit for converting to 0.

(fl As described in detail of the invention, according to the present invention, the B8ZS pattern remains in the shift register even after detection, so the VB
Even if an OVB pattern appears, there will be no false detection.

Furthermore, since the flip-flop circuit used for the shift register can be one without a clear terminal, it becomes a synchronous circuit structure and can easily increase the speed.

[Brief explanation of drawings]

Fig. 1 shows an example of a conventional decoding circuit, Fig. 2 is a diagram for explaining the operation of Fig. 1, Fig. 3 shows an example of the present invention, and Fig. 4 explains the operation of Fig. 3. A diagram is shown for each. In the figure, 19 is a B8ZS pattern detection circuit, 20 is a bipolar/unipolar conversion circuit, 30 to 32 are 4-bit shift registers (storage section), 34 is a gate circuit, and 4
0 indicates a storage section, 41 a switch section, and 21 to 23 terminals, respectively. 1st eye 2nd eye) A10 1234547 B 9101112+
3 ■ 0OOVBOVBVBOVB ■ 00000000VBOVB

Claims (1)

[Claims] A storage unit that stores input data, a BnZS encoded pattern detection unit that detects a BnZS encoded pattern included in the data stored in the storage unit, and the BnZ
1. A decoding circuit comprising: a switch section for blocking external transmission of the BnZS encoding pattern in the data output from the storage section as an output of the S encoding pattern detection section.