JPS6298425A - Arithmetic shifter circuit - Google Patents

Abstract

PURPOSE:To decrease remarkably the number of circuit constituting elements, and to detect an overflow by detecting an overflow which is generated at the time of an arithmetic shift of a fixed point data, by a normalized shift quantity detecting circuit which is prepared for a floating point arithmetic, and a comparing circuit which is added newly. CONSTITUTION:A point in which an arithmetic shifter circuit is different from a conventional one is to have provided a comparing circuit 20 instead of a shift overflow detecting circuit. That is to say, the comparing circuit 20 is a circuit for comparing an arithmetic shift quantity designating signal S1 and a normalized shift quantity signal S2, and outputting an overflow output signal 012 corresponding to its comparison, its input terminal is connected to an input terminal 2 and an output terminal of a normalized shift detecting circuit 6, and its output terminal is connected to an overflow use output terminal 21. In such a way, the normalized shift quantity detecting circuit and the comparing circuit are operated so as to detect directly an overflow which is generated at the time of an arithmetic shift of a fixed point data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application in Industry-1-) The present invention relates to an arithmetic shifter circuit that performs arithmetic shifting of data expressed in a fixed-point format in a floating-point arithmetic circuit.

(Prior Art) A floating-point arithmetic circuit is a circuit that arbitrarily specifies the decimal point position of data expressed in a floating-point format consisting of a sign, an exponent part, and a mantissa part (hereinafter simply referred to as floating-point data). This is a circuit that performs calculations.

This floating point arithmetic circuit normally processes N bits or more at a time for digit alignment and normalization of mantissa data.
22) is provided with a barrel shifter circuit that performs the normalization shift (movement). Therefore, by using this barrel shifter circuit, it is possible to perform an arithmetic shift of 2 pints (digits) or more of -1- degrees of data expressed in fixed-point format (hereinafter simply referred to as fixed-point data). At this time, if fixed-point data in two's complement representation is arithmetic shifted to the left (towards the most significant bit), the sign bit changes during the shift, causing an overflow (overflow) and meaningless Since the result may be output, a means for detecting the occurrence of an overflow is required.

However, in the pulse shifter circuit of a floating point arithmetic circuit that generally performs addition and subtraction, an overflow does not occur even if barrel shift is performed in the left force direction for normalization, so an overflow detection circuit is usually provided. Not yet. As a result, if it is attempted to perform arithmetic shift of fixed point data using the barrel shifter circuit in the floating point arithmetic circuit, it becomes necessary to provide a new overflow detection circuit.

Conventionally, as an arithmetic shifter circuit for fixed point data using a barrel shifter circuit in such a floating point arithmetic circuit, there has been a structure as shown in FIG. 2, for example. The configuration will be explained below.

This 12-point shifter circuit has an input terminal 1 for inputting old floating-point data or fixed-point data D2, an input terminal 2 for inputting a q-shift amount designation signal St of fixed-point data D2, and an output for sending out a shifter output signal 01. An output terminal 4 for outputting a terminal r3 and an overflow output value 02 is retained.

The input terminal 1 has a bar shifter circuit 5 and an iI representation,
shift) tt1 detection circuit 6 is connected. The barrel shifter circuit 5 is a circuit that performs a 11: actualization shift on the iγ dynamic point data, or a 1' shift on the fixed point data 02, and sends out a shifter output (1j!301, and the shifter output value) 01 is sent to the output terminal f3. The normalized shift product detection circuit 6 is a circuit that detects the IF normalized shift state for normalizing the floating point data D1 and outputs the normalized shift signal -392.

A selector 7 is connected to the ltl power terminal and the input terminal 2 of the normalization shift) 11 detection circuit 6. Selector 7
is the normalized shift IA signal IS 2 and the arithmetic shift) IJ
This is a circuit that performs vj exchange with the j specified signal S1, and the signal S
2. Also, SL can be connected to the barrel shifter circuit 5. A shift overflow detection circuit 8 is connected to the barrel shifter circuit 5 . The shift overflow detection circuit 8 is a circuit that detects an overflow that occurs when the barrel shifter circuit 5 undergoes an overflow shift, and sends the overflow output value 1302 to the output terminal 4.

FIG. 3 is a circuit diagram of the shift overflow detection circuit 8. This shift overflow detection circuit 8 has a plurality of data input terminals 10 connected to the output terminal of the barrel shifter circuit 5, and the data input terminal -10 has a plurality of exclusive OR circuits (hereinafter referred to as EXOR circuits). A logical sum circuit (hereinafter referred to as an OR circuit) 11 and an OR circuit (hereinafter referred to as an OR circuit) 12 are connected. An overflow output m number 02 is output from the final stage of the OR circuit 12, and is sent to the output terminal 4.

Next, the operation will be explained.

In FIG. 2, when floating point arithmetic is performed, the selector 7 selects the normalized shift star side. At this time,
1 for floating point data D input from input terminal f1
11-shift for firing in the normalization shift amount detection circuit 6)
- The quantity is determined and its normalized shifted ti1 signal S2 is supplied to the barrel shifter circuit 5 through the select 7.

Then, the barrel shifter circuit 5 receives the 1γ dynamic point data DI.
Perform normalization shift on .

On the other hand, when performing a 17-bit shift of the fixed-point data D2, the select L/cut 7 selects the r- side of the shift lit input terminal. Then, the arithmetic shift fit specification signal Sl is set to selector 7.
Ij is sent to the barrel shifter circuit 5 through the Ij. The barrel shifter circuit 5 performs an arithmetic shift using the signal S1 on the fixed point data r]2 input from the input terminal 1.
Perform an arithmetic shift. The overflow that occurs during this arithmetic shift is detected by the shift-off detection circuit 8, and its overflow output signal 02 is output to the outside through the output terminal r4.

Here, the shift overflow detection circuit 8 of FIG. 3 operates as follows. As a result of the arithmetic shift operation performed in the /Hail9F2 circuit 5, data overflowing from the n''f bit is input to the shift overflow detection circuit 8. When all of this overflowing data is content, overflow does not occur; on the other hand, when all of the data is not content, overflow occurs. From this, the EXOR circuit 11 detects whether adjacent bits are the same for the data input to the overflow detection circuit 8,
By ORing the outputs of the EXOR circuit 11 with the OR circuit 12, an overflow output signal 02 of logic "i" is output from the output terminal 4 when an overflow is detected. This makes it possible to detect the bar flow from the outside.

(Problems to be Solved by the Invention) However, since the arithmetic shifter circuit having the one-note configuration requires the shift overflow detection circuit 8, there are the following problems.

When using the overflow detection circuit 8 as shown in FIG.
When the amount of hardware increases, especially when configuring this circuit 8 with 803 circuits, the EXOR circuit 11 with a large number of transistors
, which results in an increase in the number of transistors. Furthermore, in this shift overflow detection circuit 8,
Since the output of the final stage of the barrel shifter circuit 5 is used as the data input, there is a problem in that the shift operation delay increases.

The present invention provides an arithmetic shifter circuit that solves the problems of the prior art, such as an increase in the number of circuit elements r and an increase in shift I and operation delay.

(Means for Solving the Problem) In order to solve the problem, the present invention provides an emphasis shift 1 positive detection circuit that detects a normalization shift amount for normalizing floating point data, and a Arithmetic shifting of the fixed point data is performed based on the arithmetic shift amount of the fixed point data using a floating point arithmetic circuit equipped with a barrel shifter circuit that performs normalized shift of the floating point data based on the conversion shift l, -%. In the arithmetic shifter circuit,
the normalization shift l-iil, and the 1'l technique shift j,
A comparison circuit is provided for detecting an overflow occurring during the arithmetic shift I by comparing the arithmetic shift I and t.

(Function) According to the present invention, since the arithmetic shifter circuit is configured as described below, the it normalized shift I, 1 detection circuit, and comparison circuit can directly handle overflow that occurs during arithmetic shift of fixed-point data. Move 1 to detect. Furthermore, the comparison circuit can be realized with a simple circuit configuration. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a block diagram of an arithmetic shifter circuit showing an embodiment of the present invention. In addition, in the drawing, the same elements as those in the conventional FIG.

The difference between this arithmetic shifter circuit and the conventional one is that a comparison circuit 2 is used instead of the shift overflow detection circuit 8 shown in FIG.
The reason is that 0 is set. That is, the comparator circuit 20 outputs the arithmetic shift designation signal S+ and the 11-selective shift signal S2.
and an overflow output signal 012 corresponding to the comparison.
The input terminal -r is connected to the input terminal 2 and the 111 output terminal of the normalization shift detection circuit 6,
The output terminals f are respectively connected to the overflow output terminals i21.

FIG. 4 is a circuit diagram showing an example of the configuration of the comparison circuit 20.

This comparison circuit 20 is composed of a 4-bit comparator (comparator), and has a 4-bit arithmetic shift sewing designation signal 5l.
(Sl-0 to 5l-3) and normalized Schiff+-! i! Data input terminal f for inputting the signal 52 (S2-0 to S2-3)
-22 (22-01, 22-02 ~ 22-31.22-
32).

1 to 3 pin data input terminal 22-[)1.22-
23-
0 to 23-2, negative circuit (hereinafter referred to as 807 circuit)
24-0 to 24-2, and a NAND circuit (hereinafter, N
(referred to as ANn circuit) 25-0 to 25-2 are connected. In addition, a 4-bit data input terminal 22-31.2
2-32 includes a NOT circuit 24-3 and a NAND circuit 2.
5-3 is disconnected. Furthermore, the NANr1 circuit 25
An AND circuit (hereinafter referred to as an AND circuit) 26 is connected to -0 to 25-3, and the output side of the AND circuit 26 is an I
It is connected to the H power terminal 21.

Since this comparison circuit 20 has a 4-bit configuration, 0 to 15
Applies to arithmetic shifts of bits. When the designation signal 5l (Sl-0 to 5l-3) and the normalized shift li% signal 52 (S2-0 to S2-3) are manually applied to the arithmetic shift for 4 bits, the signals of each of these bits are 5l-0, 52-0
~5l-3, 52-3 are each EXNOR circuit 23-
0 to 23-2 and NOT circuits 24-0 to 24-3. After the magnitudes are compared in NANO circuits 25-0 to 25-3, signals S1 and S are
A comprehensive comparison of 2 is made.

If Sl>S2, an overflow output signal 012 of logic "1'" is sent out from the output terminal 21, and if Sl≦S2, an overflow output signal 012 of logic "O°" is sent out from the output terminal 21.

Next, a description will be given of the operation when performing arithmetic shift of the fixed-point data D2 using the arithmetic shift circuit configured as described above.

First, when fixed point data D2 is input from the input terminal 1, the data D2 is supplied to the barrel shifter circuit 5, and then also supplied to the common number detection circuit 6. Then, the normalized shift amount detection circuit 6 detects how many sign bits of the fixed-point data D2 continue in the direction of the least significant bit (LSB), and detects the normalized shift amount that is the detection result. 11H-signal S2 to comparison circuit 2
Increase by 4 to 0. At this time, the arithmetic shift amount designation signal Sl input from the input terminal r-2 is applied to the comparator circuit 20, and is also selected by the selector 7 and supplied to the barrel shifter circuit 5.

Therefore, the barrel shifter circuit 5 only shifts the shift amount (for example, 0 to 15 bits) of the arithmetic shift presentation designation signal S1.
Arithmetic shift of the fixed-point data D2] is performed, and the shifter output signal 01 is sent from the output terminal r3.

- On the other hand, in the comparison circuit 20, the arithmetic shift 1. A comparison is made between the i, i designation signal 13Sl and the normalized shift jj signal S2.

Here, normalized shift t1! The signal S2 indicates how many consecutive points the sign bit of the fixed-point data D2 has the same content toward the lowest bit, ].
Arithmetic shift early specification a1) St is this 1 [normalized shift f
1. = less than S2, an arithmetic shift will not cause an overflow. Therefore, the overflow output signal 01 outputted from the comparator circuit 20 is
2 becomes logic II O11. Conversely, the arithmetic shift amount designation signal S1 is the normalized shift Ji! If it is larger than signal S2, an overflow will definitely occur, so
Oyatsuro Yuyu signal No. 1 O12 becomes logic "1".

In this way, in the comparator circuit 20, the arithmetic shift l-l and I
By comparing the magnitude relationship with the sintering shift h),
An overflow occurring in an arithmetic shift can be detected, and therefore the occurrence of an overflow can be signaled to the outside through the output terminal 21.

In addition, in the comparator circuit 20 of FIG.
When configured with O9I-transistor (0MO8), 70
The number of transistors required is On the other hand, in order to cope with overflow during arithmetic shift of O to 15 bits in the shift overflow detection circuit 8 of FIG.
The number of transistors required is Therefore, comparison circuit 2
If 0 is used, the hardware scale can be significantly reduced.

The advantages of this embodiment can be summarized as follows.

(1) By using the amount detection circuit 6 (normalization shift prepared for floating point calculations for flow determination), only the comparison circuit 20 can be newly provided.
The hardware 1d can be reduced by 51 points.

Moreover, when the word length of fixed-point data D2 becomes large,
In the conventional overflow detection circuit 8 using an EXOR circuit, the hardware size increases in proportion to the data word length, but according to this embodiment, the number of bits N to be compared can be Log2N, so the larger the number of bits, the more difficult the hardware is. The effect of scale reduction will be greater.

(2) According to this embodiment, the shift overflow is determined by comparing the shift (shift) Ftt with the number of consecutive bits in the direction of the least significant bit of the sign bit. Therefore, an increase in shift operation delay can be prevented.

In the embodiment described in -1- above, a comparator as shown in FIG. 4 was used as the comparison circuit 20, but it is also possible to use various magnitude comparison means such as a subtraction circuit.

(Effects of the Invention) - As explained in detail, according to the present invention, normalized shift product detection prepared for floating point arithmetic is possible! 4 circuit and a newly added comparator circuit to detect overflows that occur during arithmetic shifts of fixed-point data, so the number of circuit components can be significantly reduced, and it is independent of arithmetic shift operations. Since overflow detection can be performed in parallel with this, it is possible to prevent the R delay of the shift operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of an arithmetic shifter circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of the configuration of a conventional arithmetic shifter circuit, and FIG. 3 is a circuit diagram of the shift overflow detection circuit in FIG. FIG. 4 is a circuit diagram of the comparison circuit in FIG. 1. 5... Barrel shifter circuit, 6... Normalization shift detection circuit, 7... Selector, 20...
...Comparison circuit, Dl...Floating point data, D2...Fixed point data, 01...
...Shift output signal, 012... Overflow output signal, Sl... Arithmetic shift amount designation signal, S
2...Normalized shift sewing signal. 7; Set puffer fish Dl: Floating point data D? , Fixed node J4 length Yu5 Tenitor 01, Shift output signal Calculating wart shifter circuit of the present invention, Hayabusa 1 diagram

Claims (1)

[Claims] a normalization shift amount detection circuit that detects a normalization shift amount for normalizing data expressed in floating point format; and a barrel shifter circuit that performs normalization shift of the floating point format data based on the normalization shift amount. In an arithmetic shifter circuit that performs arithmetic shifting of data in fixed-point format based on the amount of arithmetic shift of data expressed in fixed-point format using a floating-point arithmetic circuit comprising:
An arithmetic shifter circuit comprising a comparison circuit that compares the normalized shift amount and the arithmetic shift amount to detect an overflow that occurs during the arithmetic shift.