JPS6128423Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a programmable counter that divides the frequency of an input signal by 1/N. In particular, the frequency division value N can be calculated without increasing the area of the semiconductor chip.
This invention relates to a device that can be set over a wide range of settings.

In recent years, demand for phase lock circuits and other programmable counters has increased. A conventional configuration is shown in FIG. 1 is a binary counter, 2 is a code converter, _p is the input frequency, and _v is the output frequency. Preset data is applied to the counter 1 via the code converter 2 for the binary program values P _p to _{P i} . In devices with such a configuration, the code converter 2 is often configured with a ROM, and if the settable range of the frequency division number N is increased,
This ROM has the disadvantage of being large.

In other words, as an example, the number of channels (the number of programmable values) is 1024, and the frequency division number N is 1600 ~
2623, the number of program input terminals P _p -P _i is 10, the number of digits of the counter is 13, and 13 preset data J _p -J _o of the counter are also required. At this time, if the code converter 2 is configured with a ROM, in order to develop 1024 channels from 10 pieces of binary code data, a ROM of 10 x 1024 = 10240 bits is stored in the first ROM 3 as shown in Figure 2. necessary, and furthermore,
In order to convert 1024 channels into 13-bit preset data, a ROM of 1024×13=13312 bits is required as the second ROM 4. Therefore, the total number of bits of the required ROM is 23,552, which increases the chip area of the semiconductor device.

Furthermore, because two ROMs are used to create preset data from a value of "0" and code conversion is performed, there is a drawback that high speed cannot be achieved.

The present invention is an improvement on this problem, and aims to provide a programmable counter that does not require a large chip area even when the number of channels is large and can increase speed.

The present invention provides a programmable counter having a multi-digit binary counter and a means for inputting preset data to each digit of the binary counter, and an adder having a number of binary adders equal to the number of digits of the binary counter. The minimum value of the preset data is input to one input terminal of the adder, the difference value between the data to be preset and the above minimum value is input to the other input terminal, and the result of their addition is input. It is characterized in that it is output to a preset input terminal of the binary counter.

A 1-digit adder is provided for each program input terminal (P). The sum output of this adder is configured to be input to the preset input terminal (J) of the counter. The lowest value of the preset data is input to the input B _i of the adder. The difference value between the preset data and the lowest value is input to input A _i . Each adder generates a sum S _i obtained by the exclusive OR of the inputs A _i and B _i , the exclusive OR of the carry C _i from the lower digit, and the carry C _{i +1} . When expressed as a logical formula, S _i = A _i B _i C _i + _{i i} C _i + A _{i i i} + _i B _{i i} C _i+1 = A _i B _i + B _i C _i +C _i A _i. Become.

Next, an embodiment of the present invention will be described.

FIG. 3 is a block diagram of a circuit according to an embodiment of the present invention. An input A _i of the adder 6 is connected to each of the preset input terminals P _p to P _o . This adder 6
The input B _i of is connected to the power supply PW, and the carry input C _i is connected to the carry output C _i of the adder of the lower digit. The summation outputs S _p -S _o are connected to preset input terminals J _p -J _o of the binary counter 1.

FIG. 4 shows an example of the configuration of the adder 6. The input B _i of each adder 6 is fixed to a voltage corresponding to the lowest value N _nio of the frequency division number N.

If the frequency division number N is 1600 to 2623, the lowest value N _nio is 1600, and the calculation executed by the adder 6 is as follows: S = N _nio + P (where P is the program value and S is the output preset value) Decimal calculation) becomes. Program values are 0-1023. Thereby, any value between 1600 and 2623 can be selected as the frequency division number N. For example, when presetting 2000, the difference between 2000 and the lowest value 1600 is
Input terminal P _p of adder 6 with 400 as program value
~P _o .

Furthermore, as shown in FIG. 4, the adder 6 for one digit can be realized by about 13 gates, that is, 20 to 26 elements, so the device can be miniaturized. The 13-digit adder described above can be realized with only 260 to 338 elements, so if you compare the same example with a ROM structure like the conventional structure, the area of the semiconductor chip will be much smaller. It will be several tenths.

As described above, according to the present invention, a programmable counter whose chip area does not become large even when the number of channels is large is obtained.

Further, since the adder only needs to add the minimum value to be preset and the difference value therebetween and convert the code, there is an effect that a high-speed programmable counter can be realized.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional device. FIG. 2 is a configuration diagram of a code converter of a conventional device. FIG. 3 is a configuration diagram of an apparatus according to an embodiment of the present invention. FIG. 4 is a diagram showing an example of the configuration of an adder. 1...Binary counter, 2...Code converter, 3, 4...ROM (read-only memory), 6...
Adder.

Claims (1)

[Claims for Utility Model Registration] A programmable counter having a multi-digit binary counter and means for inputting preset data into each digit of the binary counter, wherein the number of binary adders is equal to the number of digits of the binary counter. The minimum value of the preset data is input to one input terminal of the adder, and the difference value between the data to be actually preset and the minimum value is input to the other input terminal of the adder. , and the result of their addition is output to a preset input terminal of the binary counter.