JP2509464Y2 - D / A conversion circuit - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a D / A conversion circuit, and in particular, a simple D / A conversion circuit incorporated in a one-chip microcomputer (hereinafter referred to as a microcomputer). Regarding

(B) Conventional technology In recent years, as microcomputers have become more sophisticated, serial I / O circuits, A / D conversion circuits, or D / A conversion circuits have been installed in one chip.

Conventionally, a general R-2R type ladder resistor network is used for a D / A conversion circuit built in a microcomputer. The R-2R type ladder resistor network is constructed by connecting the output of an inverter corresponding to each bit of digital data to one end of a 2R resistor, as disclosed in Japanese Patent Laid-Open No. 60-105323.

On the other hand, as disclosed in Japanese Patent Laid-Open No. 60-51028, a PWM type D / A conversion circuit for obtaining an analog signal by integrating a pulse having a duty corresponding to digital data is also conceivable.

(C) Problems to be solved by the invention However, the R-2R type ladder resistor network was used.
In order to incorporate a D / A conversion circuit or a PWM type D / A conversion circuit in a microcomputer, the number of constituent elements increases and the chip area must be increased.

In addition, it is uneconomical to use a conventional microcomputer having a built-in D / A conversion circuit when the D / A conversion does not require such high precision.

(D) Means for solving the problems The present invention was created in view of the above points,
A shift register having a parallel input connected to the data bus and a control signal for instructing the start of the operation count the number of shift clocks for controlling the shift operation of the shift register by the number equal to the number of stages of the shift register. Shift register control means for stopping the application and outputting an end signal indicating the end of the shift operation of the shift register, an integrating circuit to which the data sent from the shift register is applied, the data bus, and the end signal By providing the shift register with data setting means for presetting predetermined data based on the above, a simple D / A conversion circuit with a small number of constituent elements can be obtained.

(E) Operation According to the above means, the shift register and the shift register control means can use the serial input / output circuit built in the microcomputer, and the shift register is provided with the data setting means for presetting data. By presetting predetermined data in the shift register and performing a serial output operation, an analog signal is obtained by the integrating circuit to which the data is applied.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, (1) is a 4-bit data bus, (2) is a shift register, (3) is D-FF, (4) is an output buffer, (5) is an input buffer, and (6) is shift control. circuit,
(7) is an integrating circuit, and (8) is a data setting means. The shift register (2) is composed of 4 bits, and each bit of its parallel input is connected to the data bus (1). The output of the shift register (2) shifts the data to the shift clock.
It is applied to D-FF (3) for delaying by a half cycle of SCL, and the output of D-FF (3) is serially output from the serial output terminal (9) via the output buffer (4). Data is applied to the data input D of the shift register (2) from the serial input terminal (10) via the input buffer (5). The shift operation of the shift register (2) is performed by the shift clock SCL applied from the shift control circuit.
And the operation of the D-FF (3) is controlled by the shift clock (5) inverted by the inverter (11). The shift control circuit (6) includes a counter (12) and a R-SFF (13) to which a start signal START for instructing the start of the shift operation is applied to the reset input, and an AND gate (14) for outputting the shift clock SCL Composed. The counter (12) is a counter that counts the shift clock SCL by the same number as the number of stages of the shift register (2), that is, "4", and its output is connected to the set input S of the R-SFF (13). AND gate (14) is R-SFF (13)
The timing pulse IP is output as the shift clock SCL.

These shift register (2) and shift control circuit (6) constitute a serial input / output function provided in the microcomputer (15), and include a serial output terminal (9), a serial input terminal (10), and The shift clock terminal (16) can be used to exchange data with the outside. In this embodiment, D / A conversion is performed by using this serial input / output function, and the resistor R and the capacitor C are connected to the serial output terminal (9).
An integrating circuit (7) composed of the above components is connected, and further a data setting means (8) is provided on the data bus (1). The data setting means (8) is means for creating a pulse train integrated by the integrating circuit (7) from digital data to be converted into an analog signal and presetting it in the shift register (2), and the microcomputer (15). It can be configured by the program.

FIG. 2 is a diagram showing the relationship between the digital data handled by the data setting means (8) and the preset data. Every time the digital data is "1" step, "1" of the preset data is 1 bit. Increase or decrease.

FIG. 3 is a timing diagram showing the operation of the embodiment shown in FIG. Timing pulse IP in this embodiment
Uses a pulse having a cycle that is 64 times the cycle time of the microcomputer (15), which is a timing pulse that is sufficiently longer than the instruction execution time.

First, a start command START is generated by executing a predetermined command, for example, a D / A conversion start command, and a counter (1
2) and R-SFF (13) are reset, and the counter (12) is made ready for counting. Further, the data shown in FIG. 2 is transferred to the data bus (1) by the operation of the data setting means (8).
Is sent to the shift register (2) via the and is preset in the shift register (2) by the write pulse LOAD. When the R-SFF (13) is reset, the AND gate (14) outputs a shift clock SCL which is 64 times the cycle time, and the shift clock SCL shifts the preset data D-FF (3). It is delayed by a half cycle of the clock SCL and applied to the integrating circuit (7). When the counter (12) counts four shift clocks SCL, its output is output as an end signal END indicating the end of data transfer, and R-SFF (13) is set. As a result, the shift clock SCL is cut off in the AND gate (14), and the operation of the shift register (2) is stopped. on the other hand,
An interrupt request is issued to the microcomputer (15) by the end signal END, the data setting means (8) is operated in the interrupt process, and data is preset in the shift register (2) again. Then, the data transfer is executed again by generating the start signal START. At this time, when the same data as the previous time is repeatedly output, the serial output terminal (9) and the serial input terminal (10) are connected to each other, so that the start signal START It only needs to occur.

Further, the operation shown in FIG. 3 is for outputting 4-bit data, but when 8-bit data is sent out by the 4-bit shift register (2), it is shown in FIG. An analog signal of 9 stages can be obtained by transmitting the 8-bit data by dividing the data into 4-bit data twice.

In this way, when the data shown in FIG. 2 or 4 is integrated, an analog signal corresponding to the duty of the applied data is obtained, which is similar to PWM type D / A conversion.
A D / A conversion circuit can be realized.

(G) Effect of the Invention According to the present invention as described above, a simple D / A conversion circuit can be constructed by using a microcomputer having a serial input / output function, and the number of constituent elements for that purpose is extremely large. Few. Therefore, a D / A conversion circuit which does not require so much accuracy can be easily incorporated in the microcomputer, which is economical.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing data for creating an integrated pulse example, and FIG. 3 is a timing diagram showing an operation of the embodiment shown in FIG. , FIG. 4 is a diagram showing 8-bit data. (1) …… Data bus, (2) …… Shift register,
(3) ... D-FF, (4) ... output buffer, (5) ...
... Input buffer, (6) ... Shift control circuit, (7) ...
… Integrator circuit, (8) …… Data setting means.

Claims (1)

(57) [Scope of utility model registration request] 1. A shift register having a parallel input connected to a data bus and a shift clock reset by a control signal for instructing the start of operation to shift the shift register are counted by a number equal to the number of stages of the shift register. A counter that outputs an end signal that indicates the end of the shift operation of the shift register later, a first logic level that is output when the control signal is applied, and a second logic level that is output when the end signal is applied. A logic level output circuit for outputting, a gate circuit for permitting supply of the shift clock to the shift register while the output of the logic level output circuit is at the first logic level, and serial output from the shift register A holding circuit that holds data in synchronization with the shift clock that has passed through the gate circuit; A data setting means that is connected to the data bus and presets predetermined data in the shift register by interrupt processing of the end signal as an interrupt request signal is built in a one-chip microcomputer, and output from the holding circuit. A D / A conversion circuit, which obtains a D / A-converted analog value by integrating the stored data with an integration circuit.