JPS56117424A - Time-division type d-a converter - Google Patents
Time-division type d-a converterInfo
- Publication number
- JPS56117424A JPS56117424A JP2116080A JP2116080A JPS56117424A JP S56117424 A JPS56117424 A JP S56117424A JP 2116080 A JP2116080 A JP 2116080A JP 2116080 A JP2116080 A JP 2116080A JP S56117424 A JPS56117424 A JP S56117424A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pulse
- input
- delivered
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Abstract
PURPOSE:To secure a data holding function with a simple constitution for a time- division type D-A converter, by using a signal generating circuit, a selection circuit, a shift register and an AND circuit each. CONSTITUTION:The control circuit 2 which uses the oscillation pulse supplied from the pulse oscillator 1 for the input delivers alternately the clock signal A that defines n pieces of pulses generated with the time intervals of geometric progression as a period and the 1st pulse signal B generated after the signal A. At the same time, the 2nd pulse signal C is delivered as an on signal while the signal A is delivered. The shift register 3 which uses the n-bit data given from outside for the parallel input feeds the serial output back to the serial input and at the same time supplies the clock signal A as a shift register. The selection circuit 4 which uses the pulse signal B for the input generates the selection signal E only when tne pulse B is supplied under the conditions of the external signal D, and thus the register 3 reads the data of n-bits in parallel. The AND gate 5 delivers the serial output as it is to the integral network 6 while the pulse signal C is delivered and then converts the serial output into an analog signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2116080A JPS56117424A (en) | 1980-02-21 | 1980-02-21 | Time-division type d-a converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2116080A JPS56117424A (en) | 1980-02-21 | 1980-02-21 | Time-division type d-a converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56117424A true JPS56117424A (en) | 1981-09-14 |
Family
ID=12047155
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2116080A Pending JPS56117424A (en) | 1980-02-21 | 1980-02-21 | Time-division type d-a converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56117424A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6399434U (en) * | 1986-12-18 | 1988-06-28 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54153561A (en) * | 1978-05-25 | 1979-12-03 | Mitsubishi Electric Corp | Parallel-serial conversion circuit |
-
1980
- 1980-02-21 JP JP2116080A patent/JPS56117424A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54153561A (en) * | 1978-05-25 | 1979-12-03 | Mitsubishi Electric Corp | Parallel-serial conversion circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6399434U (en) * | 1986-12-18 | 1988-06-28 |
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