JPS5883393A - Shift register - Google Patents

Abstract

PURPOSE:To obtain a shift register for D/A conversion which is obtainable IC- implementation easily while decreasing the number of preset terminals, by connecting preset input terminals of respective shift stages in common according to the number of weightings. CONSTITUTION:Preset input terminals PA-PD of FFs F1-F15 forming respective shift stages of a multistage shift register 5 having, for example, 15 stages are connected in common to flip-flops F1-F15 according to the frequency of weighting. For example, the terminal PA is connected to the F8, the terminal PB to the F4 and F12, the terminal PC to the F2, F6, F10, and F14, and so on the terminal PB to the F4 and F12. When those terminals PA-PD are applied with a binary-coded decimal digital signal, pulses as many as a corresponding to decimal value are outputted. The number of preset terminals of the shift register for D/A conversion is decreased by the common connection to obtain the easily IC-implemented sifht register.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shift register having a preset input terminal, and particularly aims to provide a shift register suitable for use in a digital-to-analog converter. This shows the shift regime. The shift register is, for example, a D-type flip-flop F1~
11"1 can be configured as a cascade of I[ll11.] 1 is a data input terminal, 2 is a clock input terminal, 3 is a preset command input terminal, and P1 to P are each a preset data terminal. The example in the figure shows the case of an 8-stage shift register I, but if you were to create a shift register with 11 f of 00 stages, you would have to draw out 1000 preset data terminals, which would be an obstacle to IC implementation. An object of the present invention is to provide a shift register in which the number of preset terminals can be reduced even in a multi-stage shift register, and therefore, it can be easily integrated into an IC.

A second object of the present invention is to provide a DA converter with a simple configuration by using the shift register obtained by the present invention.

This invention is based on the weight of the digital code.

The preset terminals of each shift stage are commonly connected by the number of stages corresponding to the weighted round number.

A practical example of this invention is shown in ll111. In these six cases, al
A large case is shown in which 70 D-type flips F1 to F1 of Bll are connected in cascade. In the figure, 1 is a data input terminal, 2 is a clock input terminal, %3 is a preset command input terminal, 4 is an output terminal, P1 to P□ are linear flip-flops r, -F,
, o preset terminal, and 5 indicate the entire shift register.

In the present invention, the preset data terminals P1 to P□ of these plurality of flip-flops are connected in common IjI by the number of runs according to the weighting. In the example of Jimari Jin, 4 pits tc
The case where the 02M code is preset in the shift register is shown. p, , Pb, pc.

Pd indicates a digital data input terminal to which digital signals weighted with 1, 2, and 4.8 are supplied. A digital signal with weight l is supplied to input terminal P8. Therefore, in this example, this human input terminal P is the preset terminal P of one D-type flip-flop F.

Connect to. A digital signal with a weight of 2 is supplied to the housing input terminal Pb. Therefore, this flip-flop F4 with long terminal Pbu2 and preset terminals P4 and p of 11m
Hθ1. A digital signal with a weight of 4 is supplied to the input terminal PC. Therefore, in the flip-flop of this human terminal PC#24111; * 11"ge Flll @
'14 preset terminal Pffi l Pl I P
l. , connect to P□4. A digital signal with a weight of 8 is supplied to the input terminal Pd. Therefore, this input terminal Pd is 8
Bond flip-flop F□* 11”, @ “le
FY * ”* @ Fll 1 Fll eFxa
()'94F) 111 child P1 * Ple Pa @
PY * Pl *'i1* Pls e Psi
Continue. This is each 311 child PR.

Pb, pc, Pd preset terminals P1~pts
For connection to terminals p and o@ of weight l are selected at the center of the shift register 5, and the other terminals Pb to Pd are symmetrically connected to K with the center stage of the 7-rippu quadruple F$ in the center stage of the register.
l! It is desirable to continue. The data to be preset must be arranged evenly on the shift register.
I'm okay. The situation is clearly illustrated by the application example shown in FIG.

As mentioned above, the shift register sFi preset proboscis P, ~pd$ according to the present invention is connected to the preset terminals of the number of flip-flops corresponding to the weight of the digital signal given to it. This allows the number of preset terminals to be significantly reduced. Therefore, even when making a large number of shift registers, the number of preset terminals can be reduced, making it easy to apply to ICC Kanakura. FIG. 3 shows an example of application of the shift register according to the present invention. The eQ example shows a case where a D AIR% unit is configured. A clock pulse from a clock signal source 6 is applied to the clock terminal 2 of the shift register 5 to drive the shift register 5. The shift register 5 has the data input terminal 1 and the output terminal 4 commonly connected to form a circular register. A smoothing circuit 8 is connected to the output terminal 4, and a shift register st-*
The smoothed value t-7 of the circular binary pulse train signal is output to the analog output terminal 9. 10 is the preset command signal input terminal 6
The preset signal L] is applied to the preset command signal input terminal 3 of the shift register 5 and one input terminal of the gate circuit 7, and the shift register 5 is temporarily driven during presetting. It is configured to stop.

With this configuration, preset terminals P8 to P
Give a binary encoded 10-way encoded digital signal to d,
By presetting this in the shift register 5, a pulse train signal having a deniity ratio corresponding to the value of the digital signal can be obtained at the output terminal 4. That is, for example, preset terminals P, -'-PdKr1.0.0.
When the OJ digital signal is given and this is preset, the central block flop FsKHIi of the shift register 5 is preset as explained in 82@, so the output terminal 4Ka is outputted to the shift register 6 as shown in FIG. 4B. A pulse signal having a weight ratio of KT/15 can be obtained while the pulse is being used for 5 seconds. By smoothing the normal pulse signal using the smoothing circuit 8, a DC-converted analog voltage can be obtained at the multi-analog output terminal 9. Next, roel is applied to preset terminals P3 to Pd, and 0. When OJ is applied, two pulses are output during one cycle of the shift register 6 as shown in FIG. 4C. By smoothing this pulse, an analog voltage having twice the previous voltage can be obtained at the analog output terminal 9. Preset terminal P, ~
PdFCrl-, 1, O, OJ are applied to the reset terminal Pa- to which three pulses are output during one cycle of the shift register 5 as shown in FIG.
pd to ro, 0, 1. When OJt is applied, four pulses are output during one cycle of the shift register 5, as shown in FIG. 4E. By smoothing this output pulse with the smoothing circuit 8, an analog voltage corresponding to the digital value can be obtained at the analog output terminal 9''.

In this way, according to the circuit configuration shown in FIG. 3, an analog voltage corresponding to the value of the digital signal applied to the preset terminals P8 to Pd can be obtained from the output terminal 9, and the digital value can be converted into an analog voltage. . However, as long as the analog hexagonal clock pulse is not stopped, the value can be maintained semi-permanently, and there is no need to worry about drift. Further, as explained in the example of FIG. 2, when presetting digital values in the shift register 5, the preset terminals Pa to Pd are connected to the preset terminals P0 to F, so that the preset data is evenly arranged on the shift register voice 5.
, the pulses outputted to the output terminal 4 are evenly distributed in the pigeon synchronization in which the shift register goes through one cycle. Therefore, the weight can be reduced by 11g. Furthermore, the time constant of the smoothing path 8 can be made relatively small, so that an analog voltage that quickly responds to changes in the digital signal can be obtained.

As described above, according to the present invention, even a multi-stage shift register with a preset terminal t-waiting can be easily integrated into an IC.
(Using this shift register for r has a simpler structure than K) A change? You can get an I# device. Therefore, the effect of the mineral is great for practical use.

[Brief explanation of the drawing]

Il1 Diagram Butterfly The ninth W to explain the conventional shift register!
Continuation a4, Figure 2 is a rounded connection diagram illustrating an example of the shift register according to the present invention, and Figure 3 is a connection diagram of the shift register according to the present invention.
Application example of shift register by jK to v, #4 6
! Continuation diagram, 48th tl to explain its operation
! , is Lou. ]: Day! Input terminal, 2: Clock input terminal, F1 to F
l: Trip-flop, 3 nib reset command input terminal,
4: Output terminal, P! I~Pd nib reset terminal. Patent Applicant: Matsatsu Electric Manufacturing Co., Ltd. Agent Katsai Kusano 1 Kaita 2 Diagram

Claims (1)

[Claims] (1) A shift register that is derived by commonly connecting the preset registers of each shift stage to each other in accordance with the number of weights, in accordance with a shift register that can preset parallel data.