JPH0370312A - Burst period clock generating circuit - Google Patents

Abstract

PURPOSE:To set a burst period and a burst clock width optionally externally by varying the setting value of 1st and 2nd external switches and using a counter with a large count capacity. CONSTITUTION:The circuit consists of 1st and 2nd external switches 5,6, a counter 7, comparators 8, 9, an SR flip-flop 10 and a clock mask circuit 11. Then the setting value of the 1st and 2nd external switches 5, 6 is varied to set the burst clock width (burst clock pulse number) and the burst period is set according to the capacity of the counter 7 and the clock period. Thus, the burst period and the burst clock width are set optionally externally.

Description

[Detailed Description of the Invention] [Summary] Regarding a burst period clock generation circuit that outputs a periodically intermittent clock train, it is an object of the present invention to provide a burst period clock generation circuit whose burst period and burst clock width can be arbitrarily set from the outside. In a burst cycle clock generation circuit that outputs a periodically intermittent clock train, the first external switch sets the address of the start position of the clock train, and the second external switch sets the address of the end position of the clock train. an external switch, a counter that sets a burst cycle, a first comparator that detects a match between the address set by the first external switch and the output data of the counter, and a burst cycle set by the second external switch. a second comparator that detects a match between the address and the output data of the counter;
An SR flip-flop is set by the output signal of the second comparator and reset by the output signal of the second comparator, and a clock mask circuit is provided for controlling the transmission of the clock train according to the output signal of the SR flip-flop.

[Field of Industrial Application] The present invention relates to a burst period clock generation circuit that outputs a periodically intermittent clock train used for testing LSIs, multiplex data transmission systems, etc. The present invention relates to a burst cycle clock generation circuit whose burst clock width can be arbitrarily set externally.

2. Description of the Related Art In testing LSIs, multiplex data transmission systems, and the like, a burst cycle clock generation circuit that outputs a periodically intermittent clock train is used.

[Prior Art] FIG. 4 is a block diagram showing an example of a conventional burst cycle clock generation circuit. In the figure, a clock generator 1 outputs a master clock, which is applied to a 2n counter 2 and to an input terminal of a clock mask circuit 3. The binary output of counter 2 is applied to decoder 4. The output of the decoder 4 is applied to an input terminal a of the clock mask circuit 3.

FIG. 5 is a timing chart illustrating the operation of FIG. 4. The counter 2 counts the mask clock shown in (a) applied from the clock generator 1 and inputs its binary output to the decoder 4. The decoder 4 decodes the binary output of the counter 2 and inputs a decoded output synchronized with the master clock and having a pulse width multiple times that of the master clock to the input terminal a of the clock mask circuit 3, as shown in FIG. On the other hand, the master clock shown in (a) is inputted to the input terminal of the clock mask circuit 3 at normal times. Here, if the clock mask circuit 3 is formed of, for example, an AND gate, the clock mask circuit 3 will operate while the decoded output inputted to the input terminal a is at H level, as shown in (C). The master clock manually input to the input terminal is selectively output as a burst clock.

[Problem to be Solved by the Invention] However, such a conventional circuit tllD5. In this case, the burst period and the burst clock width (the number of pulses of the burst clock) are fixed by constants at the time of circuit design.

For this reason, if a burst clock other than the set burst clock is required, the circuit must be reconfigured according to the required burst clock.

The present invention has been made in view of the above problems, and an object thereof is to provide a burst cycle clock generation circuit in which the burst cycle and burst clock width can be arbitrarily set and changed by external setting means.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of a burst cycle clock generation circuit according to the present invention. In the figure, 5.6 is an external switch for setting an n-bit address,
7 is a counter for setting the burst period 2'', and outputs n-bit count data.The counter 7
In addition to the reference pulse being manually input, the clock is also manually input. The address data set by the first external switch 5 is applied to one input terminal of the first comparator 8, and the address data set by the second external switch 6 is applied to one input terminal of the second comparator 9. has been added to. The n-bit output data of the counter 7 is applied to the other input terminal of each comparator 8.9. The output signal of the first comparator 8 is applied to the S terminal of the SR flip-flop 10, and the output signal of the second comparator 9 is applied to the R terminal of the SR flip-flop 10. The output signal of the SR flip-flop 10 is applied to one input terminal of a clock mask circuit 11. A clock to be applied to the counter 7 is applied to the other input terminal of the clock mask circuit 11.

The transmission of clocks is stopped.

That is, the burst clock width (the number of pulses of the burst clock) is set by the first external switch 5 and the second external switch 6, and the burst cycle is set according to the capacity of the counter 7 and the clock cycle.

[Function] When the address data set by the first external switch 5 becomes equal to the output data of the counter 7, the SR flip-flop 10 is set according to the output signal of the first comparator 8, and the SR flip-flop 10 is set by the second external switch 6. Since the set address data and the output data of the counter 7 become equal, S
R flip-flops 1-0 are reset. and,
By setting the SR flip-flop 10, the clock is outputted as a burst clock via the clock mask circuit 11, and by resetting the SR flip-flop 10, the clock is parsed. Examples of the invention will be described in detail.

FIG. 2 is a block diagram showing an embodiment of the present invention, and the same parts as in FIG. 1 are designated by the same reference numerals.

In the figure, 4-bit switches are used as the first external switch 5 and the second external switch 6, the first external switch 5 is set to address r0000J, and the second external switch 6 is set to address r0100J. It is set. As the counter 7, a 24 binary counter is used. A clock S1 is applied to the CLK terminal of the counter 7, a reference pulse S2 is applied to the LOAD terminal, and full count data rl 111J is loaded by the reference pulse S2.

The 4-bit output data S3 of the counter 7 is applied to comparators 8 and 9.

A 4-bit multi-comparator is used as the first comparator 8 and the second comparator 9. These multi comparators 8 and 9 are set to L when the human power matches.
level signal S4. S5 is output to the SR flip-flop 10. Output signal S6 of the SR flip-flop 10
is set to the L level when the comparator 8 detects a match between the setting data of the external switch 5 and the output data S3 of the counter 7 and the output signal S4 is at the L level, and the comparator 9 detects the match between the setting data of the external switch 6 and the counter 7. Detecting the coincidence of the output data S3 of 7, the output signal S5 becomes L
It is reset to H level when it is at level. As the clock mask circuit 11, an OR gate is used. The output signal S6 of the SR flip-flop 10 is applied to one input terminal of the clock mask circuit 11, and the clock S1 is applied to the other input terminal. The clock mask circuit 11 receives the output signal S6 of the SR flip-flop 10.
When is at L level, clock S1 is changed to burst clock S
7, and when the output signal S6 of the SR flip-flop 10 is at H level, the clock S1 is prohibited from being output as the burst clock S7.

FIG. 3 is a timing chart illustrating the operation of FIG. 2. (C) is the output data S3 of counter 7
It shows. That is, the output data S3 of the counter 7
becomes the full count data r1.111J when the clock S1 shown in (a) rises while the reference pulse S2 shown in (b) is applied, and becomes ro 000'' at the next rise of the clock S1.

When the output data S3 of the counter 7 becomes ro 000J, the output signal S4 of the comparator 8 becomes L level as shown in (d). As a result, SR flip-flop 1
The output signal S6 of 0 becomes L level as shown in (f), and the clock mask circuit 11 outputs the clock S1 as the burst clock S7 as shown in (g). When the clock S1 is input four times from the state where the output data S3 of the counter 7 is ro 000J, the output data S3 of the counter 7 becomes ro 100J. When the output data S3 of the counter 7 reaches ro 100J, the output signal S5 of the comparator 9 becomes L level as shown in (e). As a result, the output signal S6 of the SR flip-flop 10 becomes (f
), the clock mask circuit 1 becomes H level as shown in
1 prohibits outputting the clock S1 as the burst clock S7 as shown in (g).

That is, according to the settings of the embodiment shown in FIG.
A burst clock with a 4-bit pulse count and a pulse generation position address between ro 000J and "0100" is output.

In the above-described embodiment, each circuit element has 4 bits, but the number of bits may be increased or decreased depending on the application.

Furthermore, an AND gate may be used as the clock mask circuit.

[Effects of the Invention] As described above in detail, according to the present invention, the number of pulses and the pulse generation position of the burst clock can be arbitrarily changed by changing the setting values of the first external switch and the second external switch. In addition, by using a counter with a large counting capacity, it is possible to provide a burst cycle clock generation circuit suitable for testing LSIs, multiplex data transmission systems, etc. in which the cycle can be arbitrarily set.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a timing chart for explaining the operation of Fig. 2, and Fig. 4 is a conventional burst A block diagram showing an example of a periodic clock generation circuit. FIG. 5 is a timing chart for explaining the operation of FIG. 4. In FIGS. 1 and 2, 5.6 is an external switch, 7 is a counter, 8.9 is a comparator, 10 is an SR flip-flop, and 11 is a clock mask circuit.

Claims (1)

[Claims] A burst cycle clock generation circuit that outputs a periodically intermittent clock train, comprising: a first external switch (5) that sets an address at the start position of the clock train; and an address at the end position of the clock train. a second external switch (6) for setting the burst cycle, a counter (7) for setting the burst cycle, and a counter (7) for setting the address and counter (
A first comparator (8) that detects a match with the output data of the counter (7), and a second comparator that detects a match between the address set by the second external switch (6) and the output data of the counter (7). an SR flip-flop (10) set by the output signal of the first comparator (8) and reset by the output signal of the second comparator (9); a clock mask circuit (1) that controls transmission of the clock train according to an output signal of
1) A burst cycle clock generation circuit characterized by providing the following.