SU1437995A2 - Ring counter - Google Patents

Abstract

The invention relates to computational and pulse engineering and can be used as a multi-mode ring counter and a controlled code generator. The purpose of the invention is to expand the functionality and the field of application by ensuring that the device operates in the recalculation mode with a step, changing the time in accordance with a number of natural numbers. The ring counter is made on D-triggers, to the D-inputs of which the transfer signals are received through the AND-OR elements from the inverse outputs of other triggers, depending on the signals on the tires of the selection of the conversion mode. 1 ill., 1 tab.

Description

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with

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The invention relates to computing technology and automation and can be used as a multi-stage ring counter and a controlled generator of code combinations.

The goal of the inventive -1 is to spread the functional capabilities of the device and the field of application by ensuring that the device operates in the conversion mode with waroM changed functions in accordance with a series of natural numbers i - 1f, 2 3,. ". JU, .. ,

Figure 2 shows a functional diagram of a six-bit ring counter.

The table shows the codes describing the operation of the counter in various recalculation modes.

Since for the given example the number six5, equal to the number of bits S, has four .p., I.e., the number six is divided by one, two- by three and six, then for operation as well in additionally entered mode contains five control buses and five AND structures in the AND-OR element of each bit.

The six-ring ring counter contains D-triggers 1.1 - 1.6 and ZK-OR elements, 2.1 - 2.6, the outputs of which, respectively, are connected to D-BXO by discharging triggers 1/1 - 1.6 “bus 3 faults, and input bus i, which are connected respectively with the input I sbtzosa and clock number inputs of all bit triggers 1.1 1., 6, tires 5 - 9 of the choice of cutting the conversion; In each category, the first inputs of the first circuit structures and element 5I-OR are connected, respectively, from the 5th to the 8th management plans. The direct output of the D-trkggera 1.1 of the first bit is connected to the second inputs of the first and fifth structural elements of the 5I-I.Sh 2.2 element of the second bit, to the second input of the second and fifth structures of the 5I-OR 2. element of the third bit Yes, and with the second) 1m input of the third structure AND the element 5I-OR 2.4 of the fourth bit 8 and the inverse output with the second input of the fourth structure. And the element 5И-ШШ 2 ,, 1, the first bit. The direct output of the D-flip-flop is 1 „2 second soybean, is dinane with the second input of the first structure AND

5I-OR 2.3 of the third bit, with the second INPUT of the second structure and the element 5I-OR 2.4 of the fourth bit and with the second input of the third structure

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five

0 5

about

five

0

five

0

five

The elements of AND are also 5I-OR 2.5 of the same bit, and its inverse output is with the second input of the fourth structure AND of the element 5I-OR 2.2 of the second bit. The direct output of the D-flip-flop 1.3 of the third discharge with an oadinen with the second input of the first and fifth structures AND element. 2.4 of the fourth bit, with the second input of the second and the same structures AND element ZI-IZH 2.5 of the same bit and with the second input of the third and fifth structures AND of the element 5I-OR 2.6 of the sixth bit, and its inverse output with the second input of the fourth structure AND of the element 5I-OR 2.3 of the third digit. The direct output of the D-flip-flop 1.4 of the fourth bit is connected to the second input of the first structure AND element 5I-ШШ 2.5 of the fifth bit and to the second input of the second structure And element 2.6 of the sixth discharge and its inverse output to the second input of the third structure And element 2, the first bit and with the second input of the fourth structure AND the element 5I-OR2.4 of the fourth bit. The direct output of the D-flip-flop 1.5 is connected to the second input of the first structure AND element 5I-OR, 2.6 of the sixth bit, and its inverse output is connected to the second input of the second structure AND element 5I-I.PI 2.1 of the first bit, with the second input to the third the structure AND element 5I-OR 2.2 of the second discharge and with the second input of the fourth structure AND element 5Y-OR 2 „5 of the second discharge. The inverse output of the D-flip-flop 1.6 of the sixth bit is connected to the second input of the first and fifth structures AND of the 5I-OR 2.1 element of the first bit, with the second input of the second structure AND of the 5I-OR 2 element. 2 of the second bit, with the second input of the third structure AND of the element 5I-KSh 2.3 of the third bit and with the second input of the fourth structure AND of the element ZI-ShZh 2.6 of the sixth bit.

The device works as follows.

In the initial state, after applying pulses over the reset bus 3, the D-flip-flops 1.1 - 1.6 are set to the zero logical state. Depending on the required conversion mode, a single logical potential is applied to one of the mode selection buses and a zero logical potential is applied to the remaining buses (table).

The table shows tire numbers and control and recalculation codes.

When pulses are supplied to the input bus 4, a tactful filling of D-flip-flops 1.1 - 1.6 units occurs, starting with flip-flop 1.1. In this case, the group of elements AND, to which a single logical potential is applied, participates in the process of functioning.

When working in the first four basic modes, compact filling with units occurs in accordance with the numerical value of the given divisor.

The conversion switch and with zero logic signals on mode selection buses 5-8, upon arrival of the first clock pulse to the input bus 4, a trigger 1.1 of the first digit {table} is set to one state. Upon receipt of the second clock pulse in a single state, the triggers 1.2 and 1.3 of the next two bits are set. Upon receipt of the third clock pulse in single states, triggers 1.4 - 1.6 of the three following bits are set.

j of the number N 6 Sfig, 2), i.e. In the first 15, the fourth jitter pulse, the work start per unit, sets the first j-triggers, in the second also the first 2j-triggers, in the third one, firing to the input bus 4, sets the first trigger 1.1 to the zero state. The fifth clock pulse sets to zero the triggers 1.2 and 1.3 of the second and third bits. The sixth clock pulse sets to the zero state the triggers 1.4 - 1.th quarter of the fifth and sixth bits of the ring counter. Further operation of the counter is cyclically repeated.

W-trigger, etc. before

N

t tact.

wherein all the triggers are set to single states. In the subsequent cycles of the counter, an alternate decrease in the number of units occurs, starting with the first trigger. With the corresponding step j. The full cycle of operation in this counter mode is completed at the 2.N-OM cycle. Subsequent cycles of operation of the device occur similarly to the first cycle.

The change of the conversion step when the counter operates in the additionally introduced fifth mode occurs in accordance with a series of positive integers 1, 2, 3, ...

The number of counter bits to be set in a unit in each clock cycle is determined by the value of the corresponding number of a number of positive integers. The number of bits whose triggers have cross-links is determined by the values of the corresponding members of row S; , where i 1, 2, 3, .... p, .. ,, and S; - partial sums of p and natural numbers

The device operates in five modes as follows.

With a single logical potential on an additional chip 9, the choice of pe15 The fourth clock pulse,

20

25

thirty

Flying to the input bus 4, sets to zero the trigger 1.1 of the first bit. The fifth clock pulse sets to zero the triggers 1.2 and 1.3 of the second and third bits. The sixth clock pulse sets to the zero state the triggers 1.4–1. Of the fourth, fifth, and sixth bits of the ring counter. Further, the counter operation is cyclically repeated.

The number of counter bits at which the most optimal mode of operation is provided in the additionally introduced mode is determined as follows:

 S

(n +

A4.1

Ills

2

.2)

where (n + 1) is the value of the maximum step of recalculation of the N-bit counter in the operation mode with variable step.

Thus, the proposed ring counter provides a mode of recalculation with a revised step varying according to the law of natural numbers.

Claims (1)

Invention Formula Ring counter auth.St. No. 100531.9, characterized in that, in order to extend the functionality by providing a conversion mode with a step varying in accordance with a series of natural numbers i 1,2,3, ..., n, .., contains an additional bus control mode, and the structure of each logical element AND-OR introduced an additional structure AND, the first input of which is connected to the additional control bus of the conversion mode, direct output of the D-flip-flop of each Sj-ro bit, where S; i is partial 5tA379956 the sum of the set Sj p of the nat-discharge, and the inverse output of the D-trigger numbers, is connected to the second of the N-ro discharge and is connected to the second additional structure inputs an AND-OR element with () -ro to (S; +1) an AND-OR element of the first digit. Tire numbers 56789 56789 56789 56789 56789 t Management Code 10,000 01,000 00100 00010 00001 0000000000 (5 0000000000000000000 Codes for re-invoice 100000 110000111000111111100000 accounts 110000 111100111111000000111000 111,000 1 1 1 1 1 1 about about 1 1 1 1 1 1, 1 1 1 1 1 1 1 1 t 111100 001111000000000000011111 111110000011000111 111111000000 .... 000000 o 1 1 1 1 1 ...... 001111 000111 000011 000001 000000 Period