SU1181133A2 - Counter - Google Patents

Abstract

COUNTER by autor. No. 1058068, characterized in that, in order to ensure its functional reliability, in each of the odd bits, the outputs of the first and third elements of J-ILINE are connected to the fourth inputs of the second AND groups, respectively, of the third and second I-ILH-NOT elements, and the output of the second element K-OR-NOT connected to the third input of the second group AND the first element AND-OR-NOT.

Description

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00 11 The invention relates to computing and automation and can be used for counting pulses in a binary code. The purpose of the invention is to ensure the functional reliability of the meter. The drawing shows a diagram of the counters sa. 1 j Social unit rank 1 is odd 1§ ,, bit 2 is even {1e ,. elements I-YSCH-t 1E 3-9 bits, input 10 bits A -, consider the operation of the device in the example of the first two bits. Suppose that at the outputs of elements 4, 7 and 9 of both bits there is logical 1, and at the outputs of elements 6 and 8 - logical O, at the outputs of elements 3 and 5 of the first discharge there are, respectively, logical - O and logical 1, and the outputs of elements 3 and 5 of the second bit of logical 1 and logical O, respectively. Upon arrival at the input 10 of the first bit of a signal equal to logical 1, logical 1 and logical O appear at the outputs of elements 6 and 7 of this bit, respectively, and logical O, which blocks elements 4 and 5, continues to act at the output of element 3 from possible triggering in this step. In the pause after the first counting pulse, logical O appears at the output of element 4 of the first discharge, 32 and logical 1 appears at the outputs of elements 3 and 5. With the arrival of the second counting pulse, 1 appears at the outputs of elements 7 and 8 of the first discharge, and at the outputs of elements 6 and 9, logical O. In this cycle, dangerous states (failures) are absent in the first discharge, since logical O from the output of element 4 blocks elements 3 and 5 from possible triggering in this cycle. Logical 1 from the output of the element 8 switches the second discharge elements 3, 4 and 5 to the state 011. In the pause after the second counting pulse, the code 011 is set at the outputs of the first discharge bits 3, 4 and 5. The action of the third counting pulse is equivalent to the first counting pulse. The fourth counting pulse causes the setting of elements 6–9 of the first bit to the initial state, and logical O from the output of element 8 sets the logical 1 to the output of element 6 of the second bit and logical O to the output of element 7 of the same bit continues to count in binary code. The introduction of new connections to each of the odd bits of the counter prevents the switching of elements 3, 4, and 5 of the odd bits, when a logical 1 signal of any duration is applied to their inputs.

Claims (1)

COUNTER FOR AUTS. No. 1058068, characterized in that, in order to ensure its functional reliability ^ for each of the odd digits, the outputs of the first and third AND-ILINE elements are connected to the fourth inputs of the second AND groups of the third and second AND-OR-NOT elements, respectively, and the output of the second AND element -OR-NOT connected to the third input of the second group AND the first element AND-OR-NOT. SU.> 1181133>