SU1480124A1 - Multistable counting flip-flop - Google Patents

Abstract

The invention relates to digital technology and can be used for pulse counting. The purpose of the invention is to simplify the device. It is achieved due to new functional connections between the circuit elements. The multistable counting trigger contains input bus 1, AND-NOT 2-5 auxiliary elements, AND-NOT 6-9 switching elements and AND-10-16 basic elements. 1 il.

Description

The invention relates to digital technology and can be used to count pulses.

The purpose of the invention is the simplification of a mono-stable countable trigger.

I

The drawing shows a functional diagram of the proposed trigger.

A multistable counting trigger contains an input bus 1 from the first. according to the fourth auxiliary elements AND-NOT 2-5, the first to fourth commuting elements AND-NOT 6-9, 'from the first to seventh basic elements AND-NOT 10-16. The output of the first main AND-NOT 10 element is connected to the input of the first auxiliary AND-NOT 2 element and the inputs of the second 1 1, fourth 13, fifth 14 and seventh 16 of the main AND-NOT elements. The output of the second main AND-NOT 11 element is connected to the input of the second auxiliary AND-NOT 3 element and the inputs of the first 10, third 12, fifth 14 and sixth 15 of the main AND-NOT elements. The output of the third main element AND-NOT 12 is connected to the inputs of the second 11, fourth 13, sixth 15 and seventh 16 of the main elements NAND, the output of the fourth main element AND-NOT 13 is connected to the inputs of the first 10, third 12, fifth 14 and seventh 16 basic elements AND NOT. The output of the fifth main element AND 14 is connected to the inputs of the first 10, second 11, fourth 13 and sixth 15 of the main elements NAND, the output of the sixth main element AND 16 is connected to the inputs of the second 11, third 12, fifth 14 and seventh 16 basic elements AND NOT. The output of the seventh main element AND 16 is connected to the inputs of the first 10, third 1-2, fourth 13 and sixth 15 of the main elements AND. The i-ro output of the AND-NOT switching element (for example, 6) is connected to the input of the i-ro (2nd) auxiliary AND-NOT element _{χ the} output of which is connected to the input. i-ro (6th) switching element AND NOT. The output of the fourth switching element AND-NOT 9 is connected to the input of the first switching element AND ~ NOT 6, The input bus 1 is connected to the inputs of all switching elements AND-NOT 6-9. The output of the first auxiliary element AND-NOT 2 is connected to the input of the fourth switching element which: the rest, 7 and 9

AND-NOT 9, the output of which is connected to the input of the sixth main element AND-NOT 15. The output of the second auxiliary element AND-NOT 3 is connected to the input of the first switching element AND-NOT 6, the output of which is connected to the inputs of all other switching elements AND-NOT 7 -9 and the inputs of the first 1 0 and seventh 16 of the main elements AND NOT '. The output of the third auxiliary AND-NOT element is connected to the input of the second AND-NOT 7 switching element, the output of which is connected to the inputs of the first 6 and third 8 AND-NOT switching elements with the inputs of the second 11 and third 12 main AND-NOT elements. The output of the fourth And-NOT auxiliary element 5 is connected to the input of the third AND-NOT 8 switching element,: is connected to the inputs of all AND-NOT 6 switching elements and the inputs of the fourth 13 and fifth] 4 main AND-NOT elements, The output of the third main AND element -HE 12 is connected to the input of the second auxiliary element AND NOT 3. The outputs of the fourth 13 and fifth 14 of the main elements AND are NOT connected to the inputs of the third auxiliary element AND NOT 4. The output of the sixth main element AND 16 is connected to the input of the fourth auxiliary element

AND NOT 5, the exit of the seventh cop AND NOT 1 b is connected to the first solid vert 9.

the main elec with the inputs help the input of the four-element AND-NOT and the fourth elements AND-NOT commuting

Multistable counting trigger works as follows.

In the initial state, the signal at input 1 is absent (O), at the outputs of the 45 AND-NOT elements 4, 5, 10, and 12 - O, and at the exhausts of the remaining AND-NOT elements - 1.

With the arrival of the first clock pulse, the AND-NOT 6 element is triggered, the output of which sets the code 11010 1101011 on the outputs of the AND-10-16 elements and blocks the AND-NOT 2, 7, 8, 9 elements from possible triggering in this clock cycle ” In a pause after the first clock pulse at the output of the IUNE 2 element, 0 appears, and the de element of the AND-NOT 4 element is 1, and it will be AND-NOT 7. When the second clock output appears, the element of the clock pulse at the output of the AND-NOT element appears О , which sets the outputs of the elements AND-NOT 10-6 code 1111010. In a pause after the second clock the pulse at the output of the AND-NOT 3 element appears 0, and at the outputs of the AND-NOT 2, 5 - 1 elements, and the AND-NOT 8 element is prepared for operation, etc., successively triggered AND-NOT elements 5, 6, 7, and 9 will set the outputs of the NAND 10-16 elements: 1011110, 1010111, 1110101, 0111101. Thus, at the outputs of the multistable trigger 15, executed on the NAND 10-16 elements, seven stable states are obtained :

010111I, 1101011, I 111010, 1011110, 10101111, 1110101, 0111101.

All AND-NOT elements can be replaced with OR-HE elements.

Claims (1)

Claim A multi-stable counting trigger 25 containing an input bus, auxiliary, switching and main AND-NOT elements, the output of the first AND-NOT main element is connected to the input of the first auxiliary AND-30 element and the inputs of the second, fourth, fifth and seventh AND main elements -NOTE, the output of the second main AND-NOT element is connected to the input of the second auxiliary element 35 AND NOT and the inputs of the first, third, fifth and sixth main AND-NOT elements, the output of the third main element AND-NOT is connected to the inputs of the second, fourth, sixth th seventh dd of the main elements AND NOT, the output of the fourth main element AND NOT connected to the inputs of the first, third, fifth and seventh main elements NAND, the output of the fifth main element ^ N NOT connected to the inputs of the first, second, fourth and the sixth main AND-NOT element, the output of the sixth AND-NOT main element is connected to the inputs of the second, third, fifth and seventh main AND-NOT elements, the output of the seventh main AND-NOT element is connected to the inputs of the first, third, fourth and sixth main NAND elements, i-th switching output of the AND-NOT element (i = l, 2,3,4) is connected to the i-ro input of the AND-NOT auxiliary element, the output of which is connected to the i-ro input of the AND-NOT switching element, the output of the fourth switching element AND-NOT connected .n with the input of the first switching element AND-NOT, and with the inputs of all switching elements AND-NOT connected to the input bus, with the exception of the fact that, in order to simplify it, the output of the first auxiliary element AND ^{and is} NOT connected to the fourth input. th switching element AND NOT, you-. the course of which is connected to the input of the sixth main element AND-NOT, the output of the second auxiliary element AND is NOT connected to the input of the first switching element AND, the output of which is connected to the inputs of all other switching elements AND and the inputs of the first and seventh main elements AND NOT, the output of the third auxiliary AND-NOT element is connected to the input of the second AND-NOT switching element, the output of which is connected to the inputs of the first and third switching AND-NOT elements and the inputs of the second and third main AND-NOT elements, output h of the fourth auxiliary AND-NOT element is connected to the input of the third AND-NOT switching element, the output of which is connected to the inputs of all other AND-NOT switching elements and the inputs of the fourth and fifth main AND-NOT elements, the output of the third AND-NOT main element is connected to the input of the second auxiliary element AND NOT, the outputs of the fourth and fifth main elements AND NOT connected to the inputs of the third auxiliary element AND NOT, the output of the sixth main element AND NOT connected to the input of the fourth auxiliary element AND NOT, od seventh basic AND-NO element is connected to the inputs of the first and fourth / auxiliary AND-NO elements and // input of the fourth switching element AND-NO.