SU1390798A1 - Highly stable flip-flop - Google Patents

Abstract

The invention relates to digital technology and can be used to recalculate pulses. The multistable trigger trigger contains input bus 1, auxiliary elements 2–4, AND – NE 5–7 switching elements, which form a three-resistant trigger with information suppression, and 3n + 3 basic AND – HE components 8–13 (, 2 i ...), forming a two-phase, six-stable memory element. The introduction of new electrical connections between functional elements simplifies the device .. 1 sludge.

Description

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with:

Invention. relate to digital technology and can be used to recalculate pulses.

The purpose of the invention is to simplify a multistable counting trigger.

The drawing shows a block diagram of a multistable counting trigger.

Multistable counting trigger containing input bus 1, three auxiliary elements I.NE 2-4, three switching elements AND-NOT 5-7 and 3n + 3 basic elements AND-NOT 8-13 (p in this case) j, output of each main The NAND element, except the first 8 and the last 13, is connected to the inputs of all the rest: the main AND NAND elements, except the previous and the next, the output of the first main element NAND 8 is connected to the inputs of all the other main NAND elements, except the second 9 and the last, 13, the output of which is connected to the inputs of all other elements, except The first 8 and the penultimate 12 output i-ro of the main element AND-NOT (i 1,2,3) is connected to the input i-ro of the auxiliary element AND-NOT, the output of which is connected to the input i-ro of the switching element AND-NOT, the output of which connected to the input of the i-ro main element AND-NOT and the input of the i-ro auxiliary element AND-NOT, the output of the first switching element AND-NOT 5 is connected to the input of the second switching element AND-NOT 6, the output of which is connected to the input of the third switching element AND -NOT 7, the output of the second auxiliary element AND-NOT 3 is connected to the input of the first comm of the decisive element AND-NOT 5, the output of the third auxiliary element AND-NO 4 is connected to the input of the second switching element AND-NOT 6, the clock 1 pin 1 is connected to the inputs of all the switching elements AND-NOT 5-7, the output of the first auxiliary element AND-NOT 2 is connected to the input of the third switching element 7, the output of which is connected to the inputs of the first 5 and second 6 switching elements AND-NOT, the output of the second switching element AND-NOT 6 is connected to the input of the first switching element AND-NOT 5, the output of which is connected to the input third comm tiruyuschego of AND - NO 7, i-fo output switching element AND-NOT

connected to the inputs (i + 3k) -x of the main elements AND-NOT (, 2, ...), ac inputs of the i-ro auxiliary element AND-NOT connected to the outputs (i + 3k) -x of the main elements AND-NOT,

Elements NAND 5-7 form a sin-resistant trigger with clearing of information. The elements AND-NO 8-13 form a two-phase, memory-stable memory element. /

Multistable counting trigger works as follows.

In the initial state, the signal on

bus 1 is missing (O), at the outputs of the elements AND-NOT 4.8 and 9 - the signal O, and at the outputs of the remaining elements and-NOT the signal 1 ..

With the arrival of the first clock pulse, the element AND-NOT 5 is triggered, from the output of which O sets the code 100111 at the outputs of the elements AND-NOT 8-13 and blocks the elements AND-NO 2.6 and 7 from possible triggering

In this cycle (In the pause, after the first clock pulse, O-NE 2 appears at the output of the element, O, 3 and 4 1 are output at the outputs and the element is prepared to operate

AND-NOT 6, With the appearance of a second clock pulse at the output of the element AND-HE 6, O appears, which sets the code 110011 at the outputs of the elements AND-HE 8-13. In the pause after the second clock pulse, the output of the element AND-HE 3 O appears, and at the outputs of the elements AND-NOT 2 and 4 1 and prepared for operation there will be the element AND-NE 7, etc., the successively working elements AND IS-NE 7,5,6 and 7 are installed at the outputs elements AND-EE 8-13 codes: 111001, 111100, 011110 and 001111. Thus, at the outputs of the multistable trigger, on the elements AND-HE 8-13 we get six stable islands: 0011 11, 100111, 110011, 111001, 111100, 011110.

To implement the device scheme, 6 + N NAND elements are required, where N is the number of stable ones from the remains of the multi-stable memory element, and N (N-1) +18 links.

Formula iso. bratis

Multistable counting trigger containing input isnu, three auxiliary elements AND-ЯЕ, three com

mutant elements AND-NOT and Zn + 3 OS-HOBHbtx elements AND-NOT (n 1,2,.,.), the output of each main element AND-NOT, except the first and last, is connected to the inputs of all the other main elements AND-NOT , except for the previous and subsequent, the output of the first main element AND-NOT is connected to the inputs of all other main elements of AND-NOT, except for the second and last, the output of which is connected to the inputs of all the remaining main elements of AND-NOT, except the first and penultimate, output i- ro of the main element AND-NOT (i. 1,2,3) is connected to the input of the i-th auxiliary element AND- E, the output of which is connected to the input of the i-ro switching element AND-NOT, the output of which is connected to the input of the i-ro main element AND-NOT and the input of the i-ro auxiliary element AND-NOT, the output of the first switching element AND-NOT connected to the input the second switching element AND-NOT, the output of which is connected to the input of the third switching

element AND-NOT, the output of the second auxiliary element AND-NOT is connected to the input of the first commutating element AND-NOT, the output of the third auxiliary element AND-NOT is connected to the input of the second switching element AND-NOT, the clock bus is connected to the inputs of all the switching elements AND -NO, characterized in that, for the sake of simplicity, the output of the first auxiliary element AND-NOT is connected to the input of the third switching element AND-NOT, the output of which is connected to the inputs of the first and second switching elements AND-NOT, the output of the second commute it AND-NO element is connected to the input of the first switching element

NAND, the output of which is connected to the input of the third switching element NAND, the output of the i-ro switching element NAND is connected to the inputs

(i + 3k) -x of the main elements AND-NOT (, 2, ...), and the inputs (i + 3k) -x of the main elements of AND-NOT are connected with the inputs of the auxiliary element of the IS-NOT.

Claims (1)

Claim A multi-stable counting trigger containing an input bus, three auxiliary NAND elements, three switching NAND elements and Zn + 3 main NAND elements (n = 1,2,...), The output of each main NAND element except the first and last, $ is connected to the inputs of all the other main AND-NOT elements, except for the previous and subsequent, the output of the first main AND-NOT element is connected to the inputs of all the other main jq AND-NOT elements, except the second and last, the output of which is connected with the inputs of all the other main elements AND NOT, except for the first, etc. Finally, the OUTPUT of the И-ΓΟ BASIC AND-NOT element (i. = 1,2,3) is connected to the i-ro input of the auxiliary AND-NOT element, the output of which is connected to the i-ro input of the AND-NOT switching element, the output of which is connected with the 20 input i-ro of the main AND-NOT element and the input i-ro of the auxiliary AND-NOT element, the output of the first switching element NAND is connected to the input of the second switching element 25 AND-NOT, the output of which is connected to the input of the third switching element AND NOT, the output of the second auxiliary element AND NOT connected to the input of the first switching ele ment AND, the output of the third auxiliary element AND NOT connected to the input of the second switching element AND NOT, the clock bus connected to the inputs of all switching elements AND NOT, characterized in that, for the sake of simplification, the output of the first auxiliary element AND NOT connected to the input of the third switching element NAND, the output of which is connected to the inputs of the first and second switching elements NAND, the output of the second switching element NAND connected to the input of the first switching element NAND, the output of which is connected to the input of a switching AND-NOT switching element, the output of the i-ro switching AND-NOT element is connected to the inputs (i + 3k) -x of the main AND-NOT elements (k = 1,2, ...), and to the inputs of the i-ro auxiliary the AND-NOT element is connected to the outputs (i + 3k) -x of the main AND-NOT elements.