SU1589279A1 - Device for shaping signatures - Google Patents

Abstract

The invention relates to computing and can be used in the construction of test diagnostics systems for memory blocks. The purpose of the invention is to increase the speed and reliability of the control. The device contains a shaper 16 control codes, consisting of a register 19 and adders 17 modulo two, a group of elements And 15, triggers 5 and 9, a counter 7, elements And 10-12, element And - NOT 8, element 6 and element 13 delays. The purpose of the invention is achieved due to the fact that modulo-two adders 17 are minimal in complexity with a given number of monitored sequences at the device inputs, and the control code size in any particular situation may be minimally necessary to ensure the required reliability of control. 1 il.

Description

The invention relates to computer technology and can be used in test diagnostic systems of memory blocks.

The purpose of the invention is to increase the speed of the device.

The drawing shows a structural diagram of a device for forming signatures, '

The device contains η information inputs 1 {“1 _P , input 2 start-stop, input 3 reset, clock input 4, first 5 trigger, element NOT b, counter 7, element NAND 8, second 9 trigger, first 10 , the second 11 and the third 12 elements And, the delay element 13, having outputs 14, the group of elements And 15, the driver 16. control codes, which include adders 17 modulo two and triggers 18, forming a register 19, the Device has outputs 20 ,

In the shaper 16, the ratio between the number of inputs η of the device, the clean adders M, and the width of the register N is η <М £ И, to

I • and the number of device outputs r << N, The device is connected "for example, to" a block of read-only memory (by inputs

1) and to indicators (on outputs 20), the read-only memory block and indicators are not shown in the drawing,

The device operates as follows.

Before starting work with the signal at input 3, triggers 5 and 9, as well as counter 7 are set to zero initial state, Zero state of trigger 5 blocks AND 15 elements, Zero state of trigger 9 blocks the arrival of clock pulses from input 4 to the clock input of register 19. The signal at input 2, passing through. . element NOT 6 and AND-NOT element 8, at the other input of which a logical 1 ”signal from the inverse output of trigger 5 sets register 19 to its initial zero state and its edge. 0/1 sets triggers 5 and 9 to 1, the single state of the direct outputs of which opens the elements And 15 and 10, respectively, Thus, the single state of trigger 5 determines the processing interval of the controlled sequences, i.e., the window of measurements received at input 1, and the single egg state of trigger 9 is the interval at which the process of formation of the control code takes place.

The arrival of the next signal at input 2 of the device switches trigger 5 to the zero state, which again blocks AND elements 15, closing the measurement window. The process of generating the control code in the register 19 continues, since switching the trigger 9 to the zero state is blocked by the zero potential at the input of the AND-NOT element 8 when the inverted signal from the input 2 of the device appears on its other stroke, After switching to trigger 0 from the output 5 element And 11 at the counting input of the counter 7 pulses begin to arrive. The inverse signal from the output of counter 7, passing through the delay element 13 and the And element 12, resets trigger 9. and counter 7 to zero, terminating the process of generating the control code. After the arrival of the next signal to input 2 of the device, the process is repeated. The conversion factor of the counter 7 is selected so that all the distortions of the bits of the register 19 (in the presence of distortions in the controlled sequences from the outputs of the tested memory block), not used as control ones, appear in those bits of the register 19. which are connected to the outputs. devices 2,

Claims (1)

Claim A device for generating signatures comprising a counter, a control codon driver, a first trigger, a first and second AND element, the clock input of the first trigger being a start-stop input of the device, an inverse output of the first trigger connected to the first input of the second AND element, a clock input of the control driver codes and the second input of the second element and are connected to the output of the first element And, the first input of which is the clock input of the device, the outputs of the shaper control codes ~ ·· Codes are the outputs of the device characterized in that, in order to improve the performance of the device ¹ , a second trigger is introduced into it, the element NOT, the third element AND, the element OR-HE, the group of elements AND and the delay element, and the reset input of the first 1589279 ⁶ triggers and the first input of the third AND element are combined and form the reset input of the device, the first inputs of the AND elements are information inputs of the device, the second inputs of the AND elements are connected to the output of the first trigger, the outputs of the AND elements are connected to the corresponding input of the first trigger, the second input element AND NOT through the element is NOT connected to the clock input of the first trigger, connect the output of the second trigger! with the second input of the first AND element, the reset inputs of the second trigger and counter are connected to the output of the third AND element; counter transfer output to the relevant information inputs φορ-jg of the control code revolutionaries, the installation input of which and the clock input of the second trigger are connected to you; the course of the AND-NOT element, the inverse output through the delay element is connected to the second input of the third AND element, the output of the second AND element is connected to the counting input of the counter, the unit input to the second state of the first trigger is connected to the first input of the AND gate and the information trigger is the setting device input.