JPS62224112A - Multi-function timer - Google Patents

Abstract

PURPOSE:To expand the function of a timer and to select the function as required by providing a load circuit setting a desired initial value to a prescaler and a counter circuit. CONSTITUTION:Load registers 3, 4 to set an initial value to each of the prescaler 1 and the counter circuit 2 coupled therewith are provided and the initial value data is set to the load register 3, 4 and the initial value data in the load registers is set to the prescaler 1 and the counter circuit 2 by using a program of a microcomputer. The initial value is set to the prescaler 1 by the software and the prescaler 1 is controlled to function as the counter and the software selects a path through which a signal outputted from the prescaler 1 and a path through which the signal outputted not through the counter 2. Thus, the existing timer is expanded without a counter newly.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a signal control technology and a technology that is particularly effective when applied to control the function of a timer. This invention relates to effective technology that can be used to expand and control functions.

[Conventional technology] A timer built into a microcomputer.

For example, as shown in Figure 3, when receiving an input signal,
Prescaler 1 creates a signal by dividing this frequency into several stages
．． It is composed of a multiplexer 5 that selects one of the plurality of signals frequency-divided by the prescaler 1, a counter circuit 2 that receives the output of the multiplexer 5, a control register 9 that outputs a signal for controlling the operation of the multiplexer 5, etc. For example, it is used to generate a timer interrupt signal to periodically execute a desired process.
(See page 219 of ``TORDATA BOOK 8/16-bit Microcomputer'').

If a function as a 16-bit load timer with a desired cycle setting is also required, an 8-bit counter is provided separately from the existing 8-bit counter circuit, and a 16-bit load timer is also required. One possible method is to do this.

[Problems to be Solved by the Invention] As described above, if a separate counter circuit is provided in order to obtain a new function, the proportion of the counter circuit in the semiconductor chip increases, and furthermore, the area of the semiconductor chip increases. This causes the inconvenience of having to increase the size.

An object of the present invention is to extend the functions of an existing timer without adding a new counter, and to make the functions selectable as necessary.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a load register for setting an initial value is provided for each of the 7 prescalers and the counter circuits that can be coupled thereto, and the initial value data is set in the load register and the initial value data is transferred to the prescaler and the counter in the load register. Setting to the circuit is performed by a microcomputer program, in other words, by software.

[Operation] According to the above-mentioned means, an initial value is set in the prescaler by the software, and the prescaler is controlled to function as a counter, and the signal output from the prescaler is outputted via the counter by the software. By being able to select a route that is output without going through a counter and a route that is output without going through a counter, it is possible to achieve the above objective of extending an existing timer without adding a new counter.

[Embodiment] FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a microcomputer system. In the figure, a circuit designated by numeral 1 is a prescaler that receives a clock sent from the outside or inside via the clock output circuit 8 and divides the frequency of the clock. The prescaler 1 has a capacity of 8 bits, although this is not particularly limited. The prescaler operates as a counter, for example, counting the number of pulse occurrences.

The circuit designated by numeral 2 is a counter circuit consisting of, for example, 58 bits.

The circuits indicated by circuit symbols 3 and 4 are respectively.

This is a load register in which initial values to be given to the prescaler 1 and the counter circuit 2 are set.

Reference numeral 5 designates a multiplexer for selecting the output of prescaler 1 when it functions as a frequency divider.

A circuit designated by the reference numeral 6 is an output control circuit that outputs either the prescaler 1 or the counter circuit 2.

A circuit designated by the reference numeral 7 is an output control circuit that controls the output of the prescaler 1 or the multiplexer 5.

A circuit designated by the reference numeral 8 is a clock output circuit that outputs a reference clock to be supplied to the prescaler 1 in accordance with an internal clock or a reference signal supplied via an external terminal EX.

The circuit code 9 indicates load registers 3 and 4.
, multiplexer 5, multiplexer output circuit 6, output circuit 7, and clock output circuit. The control register 9 has, for example, a 16-bit capacity defined as shown in FIG.

The operation of the illustrated circuit is controlled by a program of a microcomputer (not illustrated). Control data for the control register 9 and data for the load registers 3 and 4 are supplied via the bus DB.

For example, a case where the prescaler 1 and the counter circuit 2 are used as a 16-bit load timer will be described below.

First, set data for setting these bits to a set level such as II II II is written to the operation control bits B and B4 of the control register 9, and the set data for the load registers 3 and 4 is written to the bus DB. initial value data is supplied. by this,
Initial value data sent by the CPU (microprocessor) is written to the load register 3 and the load register 4 via the bus DB.

At the same time as or after the above operation, the prescaler operation control bit B of the control register 9 is set.

and counter circuit operation control bit B, for example, “O1
By writing level data which means an initialization operation such as level 1.

Initial value data of load registers 3 and 4 are written to prescaler 1 and counter circuit 2, respectively.

Next, the prescaler operation control bit B and the counter circuit operation control bit B6 of the control register 9 are respectively set to a count operation instruction level of 1 (17 levels). , placed in a countable state.

The multiplexer output circuit control bit B of control register 9 is set to the appropriate control level simultaneously with or after the presetting of bits such as bits B, B, and so on. Thereby, the signal output from the prescaler 1 is controlled so as to be input to the counter circuit via the path (b).

Bit B5 for prescaler 1 and counter circuit 2
When set data is written to the operation start instruction bits B, , B, at the same time as or after setting the count operation instruction bits B and B to the count operation instruction level.

In response, the clock output circuit 8 outputs a clock to the prescaler 1. In response to this, prescaler 1 starts counting the signal.

Further, the counter circuit 2 starts counting the output of the prescaler 31 supplied via the multiplexer 6.6 The timer shown in FIG. 1 is used as a 16-bit glue load timer under control according to the microcomputer program as described above. be able to.

Furthermore, in the above case, the output control circuit control bit B
If set data at a level indicating selection of path (a) is written in prescaler 1°, prescaler 1
It is possible to directly output the output to the outside via the output control circuit 7 without going through the counter circuit 2. That is, regardless of the operation of the counter circuit 2, the prescaler 1 can realize the function as an 8-bit load timer.

On the other hand, along with the counter circuit 2, a clock output circuit 8
It is also possible to use the prescaler 1 as a frequency divider that changes the reference clock output from the reference clock to an appropriate period. The operation in that case is described below.

In this case, the set data of load registers 3 and 4 are:
For example, they are set to O so that the counts of the prescaler 1 and the counter circuit 2 are not changed. In this case also multiplexer control bit B. -82 is written with data for specifying which of the divided signals output from prescaler 1 to select, and
Multiplexer output control circuit control bit B and output control circuit control bit B engineering. The set data is written to. In this state, the operation control bit B or B.

When the set data is written to the clock output circuit 8,
A reference clock is output to the prescaler 1. This reference clock is frequency-divided by a prescaler 1. A signal with a frequency division ratio designated by control bits 80 to B2 is input to counter circuit 2 via multiplexer 5 and output control circuit 6, whereby counter circuit 2 performs a counting operation. The illustrated circuit at this time is
For example, it is used as a timer interrupt generation circuit that outputs a timer interrupt signal via the output control circuit 7 at predetermined intervals.

In the embodiment described above, the load registers 3 and 4 are provided, and they are controlled by software to set the initial value to the prescaler, and the prescaler is operated as a counter circuit with an appropriate count value. By controlling whether the signal is output via the counter or not via the counter, the function of the existing timer can be expanded.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. 1. For example, although the timer function is controlled by writing data to the control bit of the control register 9, it is also possible to provide a control circuit in place of the control register and control the timer function thereby.

In the above explanation, the invention made by the present inventor was mainly applied to a timer built in a microcomputer, which is the field of application in which the invention was made, but the invention is not limited to this. It can be applied to general systems such as

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, the effect of expanding the functionality of an existing timer can be obtained without adding a new counter.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a timer circuit of a microcomputer. FIG. ... Load register, 5... Multiplexer, 6... Multiplexer output control circuit, 7... Output control circuit,
8...Clock output circuit, 9...Control register, B, -82...Multiplexer control bit, B□...Load register 3 operation control bit, B
,...Load register 4 operation control bit, B,...
...Prescaler operation control bit, B6...Counter circuit operation control bit, B,, B,...Operation start instruction bit, B9...Multiplexer output control circuit control bit, f3to...Output Control circuit control bit. Figure 2

Claims (1)

[Claims] 1. A prescaler that divides an input clock, a counter circuit that can input the output of the prescaler, and a load circuit that sets desired initial values to the prescaler and the counter circuit. A multi-functional timer that is characterized by: 2. The multi-function timer according to claim 1, wherein the operation control of the load circuit is realized by software.