JPH01128152A - Serial i/o circuit - Google Patents

Abstract

PURPOSE:To facilitate the connection among various types of serial I/O circuits by using a data input/output circuit, a polarity switching circuit and a control register. CONSTITUTION:A data input/output circuit 2 performs the LSB fast serial transmission/reception of data in case the switch control is secured by the designation of a control register 4 so that the SOUT and SIN sides of a shift register 1 are connected to the data buses BUS0 and BUS7 respectively. Then the MSB fast serial transmission/reception of data is ensured when said SOUT and SIN sides are connected to the data buses BUS7 and BUS0 respectively. A polarity switching circuit 3 is switched so that the external synchronizing clock signal SCLK is supplied directly as the clock input of the register 1 by a register 4 as long as the register 1 performs the output of data at the fall of a clock. Under such conditions, the register 1 delivers data at the fall of the clock SCLK. Then the register 1 delivers data at the rise of the SCLK in case the inversion of the SCLK is switched so as to secure the clock input of the register 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a serial I/O circuit belonging to electronic circuits.

[Conventional technology]

The conventional serial I/O circuit was as shown in Figure 2. In the figure, (1) is a right-shift shift register, (SIN) is the input of shift register (1), and is used for serial transmission and reception. (SouT) is the output of the shift register (1) and is the transmission output for serial transmission and reception. (SOLK) is the synchronization clock for the shift operation of the shift register (1), (BtlS7) to (BUSO) are the These are bits 7 to 0 of the internal data bus, and input and output data to and from the shift register (1).In the case of this conventional example, the data has an 8-bit configuration, and
Serial transmission and reception are performed starting from the least significant bit (LSB).

Next, the operation will be explained. First, data to be transmitted is set in the shift register (1) through data buses (BUS7) to (BLJSto). Thereafter, when one cycle of the synchronous clock signal (SCLK) is input, the shift register shifts the data by one bit, and the data in the least significant bit is output to (5out,). At the same time, the input data of (SIN) is entered into the least significant bit of the shift register. Similarly, the synchronous clock signal (SoLx
) is input for a total of eight cycles, all the 8-bit data set in the shift register is output to (5OUT), and instead, the 8-bit data input (SIN) is input to the shift register. This received data can be viewed through the data buses (BUS7) to (BUSo). In the case of this conventional example, both the output of data from (5OUT) and the input of data from (SIN) are performed by (S) of the shift register (1).

Since the bit output from the UT) is connected to the least significant bit (BUSo) of the data bus, the least significant bit (BUSo)
BUSo), so it is performed starting from the least significant bit.

[Problem that the invention seeks to solve]

Since conventional serial I/O circuits are configured as described above, the order of the bits of serially transmitted and received data is fixed (in the conventional example, it is fixed from the least significant bit), and the order of the bits of the data transmitted and received serially is fixed (in the conventional example, it is fixed from the least significant bit), and the synchronous clock signal Since the polarity is also fixed, there is a problem in that it is not easy to connect to a different type of serial I/O circuit.

This invention was made to solve the above-mentioned problems, and in order to connect with various types of serial I/O circuits, the order of bits for serial transmission and reception is changed from the highest order to the lowest order. It is an object of the present invention to provide a serial I/O circuit that can be selected and can also switch the polarity of a synchronous clock signal.

[Means for solving problems]

A serial I/O circuit according to the present invention includes a data input/output circuit that can switch between upper and lower connections between a shift register and a data bus, a synchronous clock signal polarity switching circuit, and a control circuit for controlling them. A control register is provided.

[Effect]

The data input/output circuit according to the present invention is capable of handling data set in a shift register, data read from the shift register, or an upper-level internal data bus.

Since the lower-order connections can be changed, even if the shift direction of the shift register is constant, it is possible to switch between relatively upward and downward shifts. In addition, the synchronous clock signal polarity switching circuit can change the polarity of the synchronous clock signal input to the shift register and the synchronous clock signal input from the outside, so even if the synchronous polarity of the shift register is fixed, the polarity switching circuit can The circuit can change the synchronization polarity of the shift register with respect to the synchronization clock input from the outside.

〔Example〕

An embodiment of this invention will be described below with reference to the drawings.

In FIG. 1, (1) is a right shift shift register,
(SIN) is the input of shift register (1), (5OUT
) is the output of shift register (1), (SC■, K) is the synchronous clock signal of shift register (1), (BUS7
) to (BUSO) are bits 7 to 0 of the internal data bus, which are the same as in the conventional bus. (2) is a data input/output circuit that switches the upper and lower connections between the data buses (BUS7) to (BUSo) and the shift register;
3) is a polarity switching circuit that switches the polarity of the clock signal entering the shift register (1), and (4) is a data input/output circuit (
2) and a control register that controls the polarity switching circuit (3).
Bit 1 is connected to the data input/output circuit (2), and bit 0 is connected to the polarity switching circuit (3).

Next, the operation of the serial I/O circuit according to the present invention will be explained. In the figure, the operation of the shift register (1) is the same as that of the conventional serial VO circuit.

In the example of FIG. 1 of this invention, the circuit of FIG. 2 includes a data input/output circuit (2) that switches between upper and lower connections between the data bus and the shift register, and a polarity switching circuit (3) that switches the polarity of the synchronous clock signal. and the control registers that control them (
4).

First, to explain the data input/output circuit (2), according to the specification of the control register (4), the first data output (SOUT) side of the shift register is the lowest bit o (BUSo) of the data bus, and the data input be done (S
UN) side is the most significant bit 7 of the data bus (BUS7
), the serial output (5OUT) of shift register (1) is performed from the lowest bit 0 of the data, and the data input from (SIN) is first input to Since the received data enters bit O (BUSO) of the data bus, serial transmission/reception is performed with the LSB first. Next, the control register (
According to the specification in 4), the first data output (SOUT) side of the shift register is the most significant bit 7 of the data bus.
(BUS7) and the data input side (SIN) are connected to the least significant bit 0 (BUSo) of the data bus, the serial output (SOUT) of the shift register (1) starts from the most significant bit 7 of the data. Since the first data inputted from (SIN) enters bit 7 (BUS7) of the data bus, serial transmission/reception is performed with the MSB first.

Assuming that the shift register (1) is a type that outputs data at the falling edge of the clock, the polarity switching circuit (3) is
If the control register (4) is switched so that the external synchronous clock signal (SOLK) is directly input as the clock input of the shift register (1), the shift register (1) is activated at the falling edge of the synchronous clock (SOLK). The data will be output. In addition, the polarity switching circuit (3
) is switched by the control register (4) so that the inversion of the external synchronous clock (SOLK) becomes the clock input of the shift register (1), the shift register (1) receives the synchronous clock signal (5OLK) Data will be output at the rising edge of .

In the above embodiment, the number of bits of the shift register and the data bus is 8 bits, and the synchronization of the shift register is falling synchronization, but there is no limit to the number of bits of data or the polarity of synchronization of the shift register. Also, shift register,
Data input/output circuit.

There are no restrictions on the structure of the polarity switching circuit and control register.

〔Effect of the invention〕

As described above, according to the present invention, the direction of serial transmission/reception (MSB first, LSB first) and the polarity of the synchronous clock signal can be freely switched by the control register, so that connection with various types of serial I/O circuits is possible. It becomes easy to do.

[Brief explanation of the drawing]

FIG. 1 is a serial input circuit diagram according to an embodiment of the present invention, and FIG. 2 is a conventional serial I/O circuit diagram. In the figure, (1) is a shift register, (2) is a data input/output circuit, (3) is a polarity switching circuit, and (4) is a control register. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A shift register that shifts only in one direction in synchronization with a clock signal, and a system in which high-order and low-order data can be exchanged by specifying in the register in data input/output between this shift register and an internal data bus. A polarity switching circuit that can switch the polarity of a synchronized clock signal that enters the shift register from the outside by specifying a register, and a register that specifies the upper and lower data input/output and the polarity of the clock signal. A serial I/O circuit characterized by: By changing the upper and lower inputs and outputs of the shift register and the data bus, serial transfer can start from the least significant bit or from the most significant bit. 2. The serial I/O circuit according to claim 1, wherein the polarity of the synchronization clock for serial transfer can be changed by designation.