JPH02293928A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the burden of a software and a memory space and to improve the processing speed of the whole system by providing a bit accuracy correcting circuit for executing a correction of an effective digit by a control signal from an arithmetic word length setting circuit. CONSTITUTION:This microcomputer is provided with an arithmetic word length setting circuit 101 for setting an effective digit of an arithmetic circuit, data correcting circuits 103, 104 for generating arithmetic data inputted to the arithmetic circuit by a control signal from the setting circuit 101, and an arithmetic word length variable arithmetical/logical arithmetic circuit 100 for executing an operation by the control signal from the setting circuit 101 and the data from the data correcting circuits 103, 104. Also, this microcomputer is provided with a bit accuracy setting circuit 102 for controlling an effective digit of a result of output of the arithmetic circuit 100, and a bit accuracy correcting circuit 106 for executing a correction of the effective digit by a control signal from the setting circuit 102. Accordingly, in the case the effective digit of the arithmetic circuit is different from the effective digit of the arithmetic data inputted to the arithmetic circuit of the effective digit of a result of output of the desired arithmetic circuit, a program for adjusting the effective digit of the operation by masking or shifting the arithmetic input data or the result of operation becomes unnecessary. In such a way, the burden of a software and the memory space are reduced, and the processing of the whole system is executed at a high speed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a microwave viewer.

[Conventional technology]

In conventional microcomputers, the arithmetic circuit can only perform operations with a specific bit length, so if the significant digits of the arithmetic data input to the arithmetic circuit or the significant digits of the output result of the arithmetic circuit are different, the program The calculation input data and calculation results were masked or shifted to match the valid digits of the calculation.

FIG. 3 is a block diagram showing a conventional example.

When performing arithmetic/logical operations, the operation data register A20
3 and the data set in the operation data register B204 and the value of the flag register 105, the arithmetic/logic operation circuit 200 performs the operation, and the operation result output line 114
is output to internal data bus 107 via.

For example, if the arithmetic/logical operation circuit 200 is an 8-bit operation circuit, the operation data register A203. In contrast to the 8-bit data of significant digits in the calculation data register 204, 8-bit data of significant digits is output to the calculation result output line 114. If the calculation input data has 8 significant digits and the final result you want to obtain does not have 8 significant digits, the arithmetic/logic operation circuit 200 performs the calculation once again to mask or shift the result to make the calculation valid. Match the digits.

[Problem to be solved by the invention]

Conventional microcomputers have significant digits of arithmetic circuits,
If the valid digits of the calculation data input to the calculation circuit or the output result of the calculation circuit to be desired are different, a program is required to mask or shift the calculation input data and calculation results to match the calculation valid digits, so the software This has the disadvantage that the load is heavy, the memory space is large, and the processing speed of the entire system is slowed down.

[Means to solve the problem]

The microcomputer of the present invention includes an operation word length setting circuit for setting significant digits of an operation circuit, a data correction circuit for generating operation data to be input to the operation circuit according to a control signal from the setting circuit, and an arithmetic/logic operation circuit with a variable word length that performs operations using control signals and data from the data correction circuit; a bit precision setting circuit that controls significant digits of the output result of the operation circuit; and control from the setting circuit. The bit precision correction circuit corrects the effective digits based on the signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a microcomputer according to an embodiment of the present invention.

In comparison with the conventional example shown in FIG. 3, FIG.
In place of the arithmetic data register B204, an arithmetic/logic operation circuit 100 with variable arithmetic word length and a data correction circuit A103
and data correction circuit B104.

When an arithmetic instruction is executed, the arithmetic word length setting control signal 118 is sent to the variable arithmetic/logical operation circuit 100 and data according to the arithmetic word length data of the arithmetic word length setting circuit 101 that sets the effective digits of the arithmetic circuit. The data are input to a correction circuit A103 and a data correction circuit B104, respectively. In response to the operation word length setting control signal 118, the operation input data is corrected by the data correction circuit Al 0 3 and the data correction circuit B104, and is input to the arithmetic/logic operation circuit 100 with variable operation word length. In the arithmetic/logical operation circuit 100 with variable operation word length, an operation is performed according to the state of the flag register 105 of the input operation data and the operation word length according to the operation word length setting control signal 118.
The flag register 105 changes depending on the calculation result, and the calculation result of the set word length is input to the bit precision correction circuit 106. The calculation result input to the bit precision correction circuit 106 is
Masking or shifting to effective digits is performed by the bit precision correction control signal 119 from the bit precision setting circuit 102, and the internal data bus 1 is output via the operation result output line 114.
It is output on 07.

An example of the operation of the variable arithmetic word length arithmetic/logical operation circuit 100 will be described with reference to the block diagram of FIG. 2 in the case of an adder with a maximum arithmetic word length of 8 bits.

The 8-bit adder 300 connects the flag input/output line 113
According to the calculation data input through the carry input 2 calculation data input line A115 and the calculation data input line B116, the 8-bit calculation result 305 and the carry output 3
Outputs 04. Here, the sign selection circuit 302 selects the MSB of the operation word length from the 8-bit operation result 305 according to the operation word length setting control signal 118 and sets the sign flag.

Further, the carry selection circuit 303 selects the 8-bit operation result 305 and the carry output 3 according to the operation word length setting control signal 118.
A carry of the operation word length is selected from 04 and a carry flag is set. Furthermore, in accordance with the operation word length setting control signal 118, the operation result control circuit 301 outputs the result of masking the bits other than the operation word length of the 8-bit operation result 305 to "0" from the operation result output line 117. It is output as the output result of the arithmetic/logic operation circuit 10Q.

As described above, such a variable word length arithmetic/logic operation circuit 1
00 can reduce the burden on the software.

〔Effect of the invention〕

The microcomputer according to the present invention masks or shifts the arithmetic input data and the arithmetic result when the effective digits of the arithmetic circuit are different from the effective digits of the arithmetic data input to the arithmetic circuit or the effective digits of the desired output result of the arithmetic circuit. This eliminates the need for a program to match the significant digits of calculations, reduces the burden on software and memory space, and speeds up the processing of the entire system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a microcomputer according to the present invention, FIG. 2 is a block diagram for explaining the operation of the arithmetic and arithmetic circuit shown in FIG. FIG. 2 is a block diagram of a microcomputer. 100... Variable arithmetic/logic operation circuit with operation word length, 101... Operation word length setting circuit, 102...
...Bit precision setting circuit, 103...Data correction circuit A1104...Data correction circuit B, 1
05...Flag register, 106...
Bit precision correction circuit, 107... Internal data bus, 108... Bit precision setting data input/output line, 109... Arithmetic word length setting data input/output line, 110... ...Calculation data input/output line A, 1
11... Arithmetic data input/output line B, 112...
...Flag register input/output line, 113...
...Flag input/output line, 114...Calculation result output line, 115...Calculation data line A, 116...Calculation data line B, 1
17...Calculation result output line, 118...
...Arithmetic word length control signal, 119...Bit precision precision control signal, 200...Arithmetic/logical operation circuit, 203...Arithmetic data register A, 204.
...Calculation data register B, 300...
8-bit arithmetic/logic operation circuit, 301... operation result control circuit, 302... sign selection circuit,
303... Carry selection circuit, 304...
- Carry output, 305... 8-bit operation result. Agent Patent Attorney Shinman Uchihara 27 ノ

Claims (1)

[Claims] an arithmetic word length setting circuit that sets significant digits of the arithmetic circuit; a data correction circuit that generates arithmetic data to be input to the arithmetic circuit according to a control signal from the arithmetic word length setting circuit; and control from the arithmetic length setting circuit. an arithmetic/logic operation circuit with variable operation word length that performs operations based on the signal and data from the data correction circuit; a bit accuracy setting circuit that controls significant digits of the output result of the operation circuit; and from the operation word length setting circuit. A microcomputer comprising: a bit accuracy correction circuit that corrects effective digits according to a control signal.