JPH06290044A - Sequence control circuit - Google Patents

Abstract

PURPOSE:To make it possible to change a branch condition and a polarity judging condition without changing an instruction word stored in an instruction memory. CONSTITUTION:This sequence control circuit is provided with an instruction memory 11 for instruction words, a pipeline register 12 for temporarily storing an instruction, a succeeding address selector 18 for selecting an address for reading out an instruction word from the memory 11, condition registers 13, 14 for setting up plural external state signal selecting values and code controlling values, a condition value selector 15 for selecting the values of the registers 13, 14 based upon the value of the register 12 and outputting an external state selecting value and a code controlling value, a condition code selector 16 for selecting one of external state signals based upon the external state selecting value, and a code controller 17 for judging the polarity of an output signal outputted from the selector 16 based upon the code controlling value. Since the selector 18 selects an address based upon its judging result, a branch condition and a polarity judging condition can be updated only by updating the contents of the condition registers 13, 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence control circuit in a microprocessor system.

[0002]

2. Description of the Related Art In a microprocessor system,
The program flow may be branched and executed depending on the state of the external state signal. A circuit for that purpose is called a sequence control circuit, and a conventional sequence control circuit will be described below.

FIG. 4 is a block diagram of a conventional sequence control circuit. In the figure, an instruction memory 1 is a memory in which instruction words instructing various internal operations are stored in advance. The pipeline register 2 is a register for temporarily storing the instruction output from the instruction memory 1. The condition code selector 3 is means for selecting one from a plurality of external state signals input from the outside. The code controller 4 is means for performing code control of the signal output by the conditional code selector 3. The next address selector 5 is means for selecting a memory address for reading an instruction word from the instruction memory 1. The incrementer 6 is means for incrementing the memory address (for example, adding 1 to the memory address output from the next address selector 5) to generate the non-branch address of the instruction memory 1. The next address register 7 is a means for temporarily storing the non-branch address generated by the adder 6.

The operation of the sequence control circuit configured as above will be described below.

First, the instruction read out from the instruction memory 1 is temporarily stored in the pipeline register 2 and then output to instruct various internal operations. A part of the instruction is used as a signal for controlling the sequence. Output to the condition code selector 3 to select the branch condition in the program order, to the code controller 4 to determine the polarity of the branch condition, and to select the next address as the branch address for the branch. Output to the container 5.

The condition code selector 3 selects 1 from the external state signals (for example, various flag signals such as overflow, zero, code, etc., which are generated by the operation logic result of an operation unit (not shown)). One of the signals is selected using a part of the signal output from the pipeline register 2 and output to the code controller 4. The code controller 4 determines the polarity of the signal output by the conditional code selector 3 using a part of the signal output by the pipeline register 2 and outputs the result to the next address selector 5 as a next address selection signal. .

The next address selector 5 uses the memory address for reading the instruction word from the instruction memory 1 output from the next address selector 5 to increase the value by the incrementer 6 to generate a non-branch address, and then the next address. Either the value temporarily stored in the address register 7 (non-branch address) or the branch address output by the pipeline register 2 is selected using the next address selection signal output by the code controller 4. For example, if the output of the code controller 4 is true (“1”), the next address selector 5 determines the branch address output by the pipeline register 2,
If the output of the code controller 4 is false (“0”), the non-branch address output from the next address register 7 is output to the instruction memory 1 and the adder 6 as a memory address.

As described above, the condition code selector 3 changes the external state signal by the signal output from the pipeline register 2.
And the polarity judgment result by the sign controller 4 is used,
The next address selector 5 selects either the non-branch address output from the next address register 7 or the branch address output from the pipeline register 2 and outputs the selected branch address to the instruction memory 1. Perform control (eg: Ryoichi Mori et al. “Bit Slice Microprocessor” (Sho 5
4.11.30) Maruzen, see Chapter 3).

[0009]

However, in the above-mentioned conventional configuration, the instruction word stored in the instruction memory 1 is used to select the branch condition of the execution order of the program, and the polarity of the selected branch condition is set. Since the determination is made, there is a problem that the changed instruction word must be stored again in the instruction memory when the branch condition or the polarity determination condition is changed.

Further, there is a problem that the operation of the entire sequence control circuit must be temporarily stopped in order to re-store the changed instruction word and re-execute the operation.

The present invention solves the problems of the above-described conventional sequence control circuit, and changes the branch condition or the polarity determination condition without changing the instruction word of the instruction memory (thus without re-storing in the instruction memory). It is an object of the present invention to provide a sequence control circuit that enables the above.

[0012]

According to the present invention, there are provided an instruction memory in which instruction words for instructing various internal operations are stored, a pipeline register for temporarily storing an instruction output from the instruction memory, and an instruction memory. A sequence control circuit having at least a next address selector for selecting an address for reading a command word, wherein a value for selecting a plurality of external state signals input from the outside and a value for code control are previously set. Input the set condition register, the output from the condition register and the output from the pipeline register,
A condition value selector that selects a value set in the condition register based on the contents of the pipeline register and outputs a value for selecting an external state signal and a value for sign control, and an external state signal. One of the signals is selected by using the signal output by the condition value selector and output, and the polarity of the signal output by the condition code selector is selected using the output from the condition value selector. It is provided with a code controller which makes a judgment and outputs the result to the next address selector as a next address selection signal. The next address selector is an order control circuit for selecting an address in accordance with the next address selection signal.

[0013]

According to the present invention, a condition value selector selects a value for selecting an external state signal and a value for sign control by using an instruction output from a pipeline register, and the selected value is used. Since the condition code selector selects a signal from the external state signal and the code controller determines the polarity, the next address selector can select and output a non-branch address or a branch address. When changing the branch condition or the polarity judgment condition of the program order, the branch condition or the polarity judgment condition can be changed by changing the contents of the condition register without changing the instruction word of the instruction memory.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a sequence control circuit according to the first embodiment of the present invention.

In the figure, an instruction memory 11 is a memory in which instruction words for instructing various internal operations are stored in advance. The pipeline register 12 is a register for temporarily storing the instruction output from the instruction memory 11.
In the first condition register 13 and the second condition register 14, a value for selecting a plurality of external state signals input from the outside and a value for sign control are preset.
The condition value selector 15 is means for selecting and outputting either the output signal of the first condition register 13 or the output signal of the second condition register 14. The condition code selector 16 is means for selecting one from a plurality of external state signals input from the outside. The code controller 17 is means for controlling the code of the signal output by the conditional code selector 16. The next address selector 18 is means for selecting a memory address for reading an instruction word from the instruction memory 11. The incrementer 19 is means for increasing the memory address (for example, adding 1 to the memory address output from the next address selector 18) to generate the non-branch address of the instruction memory 11. The next address register 20 is means for temporarily storing the non-branch address generated by the adder 19.

The operation of the sequence control circuit configured as described above will be described below.

First, the instruction read out from the instruction memory 11 is temporarily stored in the pipeline register 12 and then output for instructing various internal operations. A part of the instruction is used as a signal for controlling the sequence. Is output to the condition value selector 15 to select a branch condition in the program order, or the next address selector 1 is used as a branch address for branching.
8 is output.

In the first condition register 13 and the second condition register 14, a value for selecting a plurality of external state signals input from the outside and a value for sign control are set in advance, and the condition value is set. The selector 15 selects the value set in the first condition register 13 or the value set in the second condition register 14 by using a part of the signal output from the pipeline register 12, A value for selecting a state signal is output to the conditional code selector 16 and a value for code control is output to the code controller 17.

The conditional code selector 16 is one of the external state signals (for example, various flag signals such as overflow, zero, code, etc., which are generated as a result of arithmetic logic in an arithmetic unit (not shown)). One of the signals is selected using a part of the signal output by the condition value selector 15 and output to the code controller 17. The code controller 17 determines the polarity of the signal output by the condition code selector 16 using a part of the signal output by the condition value selector 15 and outputs the result to the next address selector 18 as the next address selection signal. To do.

The next address selector 18 increments by the incrementer 19 to generate a non-branch address using the memory address for reading the instruction word from the instruction memory 11 output from the next address selector 18 and then increments it by the incrementer 19. Either the value temporarily stored in the address register 20 (non-branch address) or the branch address output by the pipeline register 12 is selected by using the next address selection signal output by the code controller 17. For example, if the output of the code controller 17 is true (“1”), the next address selector 18 outputs the branch address output from the pipeline register 12, and the output of the code controller 17 is false (“1”).
0 ”), the non-branch address output from the next address register 20 is used as the memory address for the instruction memory 11 and the incrementer 1.
Output to 9.

As described above, according to the present invention, the first condition register 13 and the first condition register 13 in which a value for selecting a plurality of external state signals input from the outside and a value for code control are preset. 2 condition register 14, a condition value selector 15 for selecting a value set in the first condition register 13 and a value set in the second condition register 14, and an external device for selecting an external state signal. The code selector 16 and the code controller 17 that determines the polarity of the signal output by the external code selector 16, the non-branch address output by the next address register 20, and the branch address output by the pipeline register 12 are code controlled. When the branch condition or the polarity judgment condition is changed by providing the next address selector 18 which selects using the next address selection signal output from the device 17 and outputs the memory address, it is changed. The branch condition of the program order or the polarity determination condition of the branch condition can be updated only by updating the content of the first condition register 13 or the second condition register 14 without re-storing the instruction word in the instruction memory. .

In the first embodiment, the condition register is 2
Although the case where there are three condition registers has been described, it is needless to say that the same effect as that of the present embodiment can be obtained with one condition register or with three or more condition registers.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a sequence control circuit according to the second embodiment of the present invention. In the figure, 2
1 is an instruction memory, 22 is a pipeline register, 27 is a code controller, 28 is a next address selector, 29 is an incrementer, 30
Is the next address register, and above is the instruction memory 11, pipeline register 12, code controller 1 in the configuration of FIG.
7, next address selector 18, incrementer 19, next address register 2
The same as 0.

The difference from the configuration of FIG. 1 is that the first condition register 23 and the second condition register 24 have bit pattern values corresponding to the number of a plurality of external state signals input from the outside on a one-to-one basis. Values for code control are preset. The condition value selector 25 is means for selecting and outputting either the output signal of the first condition register 23 or the output signal of the second condition register 24. Further, the comparator 26 is true when the bit pattern of the external state signal matches the bit pattern indicating the condition set in the first condition register 23 or the second condition register 24 and selected by the condition value selector 25. It is means for outputting false ("0") to the code controller 27 when ("1") does not match.

The operation of the sequence control circuit configured as above will be described below.

First, the instruction read out from the instruction memory 21 is temporarily stored in the pipeline register 22 and then output for instructing various internal operations. A part of the instruction is used as a signal for controlling the sequence. Is output to the condition value selector 25 to select a branch condition in the program order, or the next address selector 2 is used as a branch address for branching.
8 is output.

In the first condition register 23 and the second condition register 24, a bit pattern value corresponding to the number of a plurality of external state signals input from the outside on a one-to-one basis and a value for code control are stored in advance. The condition value selector 25 uses the part of the signal output from the pipeline register 22 to set the value set in the first condition register 23 or the second condition register 24. The selected value is output, the bit pattern value is output to the comparator 26, and the value for code control is output to the code controller 27.

The comparator 26 is a bit pattern and a condition value of an external state signal (for example, various flag signals such as overflow, zero, sign, etc., which are generated by the operation logic result of an operation unit (not shown)). The bit patterns output by the selector 25 are compared with each other, and true (“1”) is output to the code controller 27 when they match and false (“0”) when they do not match. The code controller 27 determines the polarity of the signal output by the comparator 26 using a part of the signal output by the condition value selector 25, and outputs the result to the next address selector 28 as a next address selection signal. .

The next address selector 28 uses the memory address for reading the instruction word from the instruction memory 21 output by the next address selector 28 to increase the value by the incrementer 29 to generate the non-branch address, and then the next address. Either the value temporarily stored in the address register 30 (non-branch address) or the branch address output by the pipeline register 22 is selected using the next address selection signal output by the code controller 27. For example, the next address selector 28 outputs the branch address output from the pipeline register 22 when the output of the code controller 27 is true (“1”), and the output of the code controller 27 is false (“”).
0 "), the non-branch address output from the next address register 30 is used as a memory address for the instruction memory 21 and the adder 2
Output to 9.

As described above, according to the present invention, the bit pattern value and the code control value corresponding to the number of signals of the plurality of external state signals input from the outside on a one-to-one basis are preset. A first condition register 23, a second condition register 24, a condition value selector 25 for selecting a value set in the first condition register 23 and a value set in the second condition register 24, A comparator 26 that compares the bit pattern of the external state signal with the bit pattern output by the condition value selector 25, a code controller 27 that determines the polarity of the signal output by the comparator 26, and a next address register 30 output. A non-branch address and a branch address output from the pipeline register 22 are selected using a next address selection signal output from the code controller 27, and a next address selector 28 is output to output a memory address. The Rukoto, when changing the branch condition or polarity determination condition, without re-storing the modified instruction in the instruction memory, the first condition register 23
Alternatively, the branch condition of the program order or the polarity determination condition of the branch condition can be updated simply by updating the content of the second condition register 24.

In the second embodiment, the condition register is 2
Although the case where there are three condition registers has been described, it is needless to say that the same effect as that of the present embodiment can be obtained with one condition register or with three or more condition registers.

The third embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of the sequence control circuit in the third embodiment of the present invention. In the figure, 31
Is an instruction memory, 32 is a pipeline register, 38 is a code controller, 39 is a next address selector, 40 is an incrementer, 41 is a next address register. The above is the instruction memory 21 and pipeline register in the configuration of FIG. 22, code controller 2
7, next address selector 28, incrementer 29, next address register 3
The same as 0.

The difference from the configuration of FIG. 2 is that the first condition register 33 and the second condition register 34 have a mask pattern value corresponding to the number of a plurality of external state signals input from the outside on a one-to-one basis. A bit pattern value indicating the condition and a value for code control are set in advance. Condition value selector 35
Is a means for selecting and outputting either the output signal of the first condition register 33 or the output signal of the second condition register 34. The mask circuit 36 is composed of, for example, a logical product circuit or a logical sum circuit, and the bit pattern of the external state signal is set in the first condition register 33 or the second condition register 34 and selected by the condition value selector 35. Mask with a mask pattern. Further, in the comparator 37, the bit pattern output by the mask circuit 36 matches the bit pattern indicating the condition set in the first condition register 33 or the second condition register 34 and selected by the condition value selector 35. Sometimes true ("1"), false ("
0 ″) is output to the code controller 38.

The operation of the sequence control circuit configured as described above will be described below.

First, the instruction read out from the instruction memory 31 is temporarily stored in the pipeline register 32 and then output to instruct various internal operations. A part of the instruction is used as a signal for controlling the sequence. Is output to the condition value selector 35 to select a branch condition in the program order, or the next address selector 3 is used as a branch address for branching.
9 is output.

The first condition register 33 and the second condition register 34 have a mask pattern value corresponding to the number of signals of a plurality of external state signals input from the outside on a one-to-one basis and a bit pattern value and code indicating the condition. A value for control is set in advance, and the condition value selector 35 uses a part of the signal output from the pipeline register 32 to set the value set in the first condition register 33 or the second condition register 33. The value set in the condition register 34 is selected, the mask pattern value is set in the mask circuit 36, and the bit pattern value is set in the comparator 3.
At 7, the value for code control is output to the code controller 38.

The mask circuit 36 responds to a bit pattern of an external state signal (for example, various flag signals such as overflow, zero, sign, etc., which are generated by the arithmetic logic result in an arithmetic unit (not shown)). Masking is performed with the mask pattern output from the condition value selector 35, and the obtained bit pattern is output to the comparator 37.

The comparator 37 compares the bit pattern output by the mask circuit 36 with the bit pattern output by the condition value selector 35. If they match, true ("1"), and if they do not match, false (" 0 ″) is output to the code controller 38. The code controller 38 determines the polarity of the signal output by the comparator 37 using a part of the signal output by the condition value selector 35, and outputs the result to the next address selector 39 as a next address selection signal.

The next address selector 39 uses the memory address for reading the instruction word from the instruction memory 31 output by the next address selector 39 to increase the number by the incrementer 40 to generate the non-branch address, and then the next address. Either the value temporarily stored in the address register 41 (non-branch address) or the branch address output from the pipeline register 32 is selected by using the next address selection signal output from the code controller 38. For example, the next address selector 39 outputs the branch address output from the pipeline register 32 when the output of the code controller 38 is true ("1"), and the output of the code controller 38 is false ("").
0 ″), the non-branch address output from the next address register 41 is used as a memory address for the instruction memory 31 and the adder 4
Output to 0.

As described above, according to the present invention, a mask pattern value corresponding to the number of a plurality of external state signals input from the outside on a one-to-one basis, a bit pattern value indicating a condition, and a value for code control. Are set in advance, the first condition register 33 and the second condition register 34, the values set in the first condition register 33 and the second condition register 3
Condition value selector 35 for selecting the value set to 4
And the bit pattern of the external state signal to the condition value selector 35.
Mask circuit 36 for masking with the mask pattern output by
A comparator 37 for comparing the bit pattern output by the mask circuit 36 with the bit pattern output by the condition value selector 35; a code controller 38 for determining the polarity of the signal output by the comparator 37; and a next address register. The next address selector 3 which selects the non-branch address output by 41 and the branch address output by the pipeline register 32 using the next address selection signal output by the code controller 38 and outputs the memory address.
By providing 9, the content of the first condition register 33 or the second condition register 34 is updated when the branch condition or the polarity determination condition is changed without re-storing the changed instruction word in the instruction memory. It is possible to update the branch condition of the program order or the polarity determination condition of the branch condition only by itself.

In the third embodiment, the condition register is 2
Although the case where there are three condition registers has been described, it is needless to say that the same effect as that of the present embodiment can be obtained with one condition register or with three or more condition registers.

The circuits, units, registers and the like in the present invention may be realized by using software of a computer.

[0046]

As is apparent from the above description,
According to the present invention, when the branch condition or the polarity determination condition is changed, the branch condition in the program order or the polarity determination of the branch condition is simply updated by updating the contents of the condition register without re-storing the changed instruction word in the instruction memory. It is possible to realize an excellent sequence control circuit capable of updating the conditions.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a sequence control circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a sequence control circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a sequence control circuit according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional sequence control circuit.

[Explanation of symbols]

 11, 21, 31 Instruction memory 12, 22, 32 Pipeline register 13, 23, 33 First condition register 14, 24, 34 Second condition register 15, 25, 35 Condition value selection register 17, 27, 38 Code Controller 18, 28, 39 Next address selector 19, 29, 40 Increaser 20, 30, 41 Next address register 16 Condition code selector 26, 37 Comparator 36 Mask circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hidekazu Suzuki 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. An instruction memory storing instruction words for instructing various internal operations, a pipeline register for temporarily storing an instruction output from the instruction memory, and an instruction word for reading the instruction words from the instruction memory. A sequence control circuit having at least a next address selector for selecting an address, and a condition register in which a value for selecting a plurality of external state signals input from the outside and a value for sign control are preset. , For inputting the output from the condition register and the output from the pipeline register, selecting the value set in the condition register based on the contents of the pipeline register, and selecting the external state signal A condition value selector that outputs a value and a value for sign control, and a signal that the condition value selector outputs one signal from the external state signals. The condition code selector that selects and outputs using the condition code selector and the output from the condition value selector is used to determine the polarity of the signal output by the condition code selector, and the result is sent to the next address selector to the next address selection signal. And a code controller which outputs as, the next address selector selects an address according to the next address selection signal. 2. An instruction memory in which instruction words for instructing various internal operations are stored, a pipeline register for temporarily storing instructions output from the instruction memory, and an instruction word for reading out the instruction words from the instruction memory. A sequence control circuit having at least a next address selector for selecting an address, in which a bit pattern value for selecting a plurality of external state signals input from the outside and a value for code control are set in advance. A register, an output from the condition register and an output from the pipeline register are input, the value set in the condition register is selected based on the contents of the pipeline register, and the external state signal is selected. Condition value selector for outputting a bit pattern value for controlling the sign and a value for sign control, the bit pattern of the external state signal and the condition Comparing the bit patterns output by the value selector, outputting a signal that is true when they match and false when they do not match, and the signal output by the comparator using the output from the condition value selector. And a code controller for determining the polarity and outputting the result to the next address selector as a next address selection signal, and the next address selector selects an address according to the next address selection signal. Sequential control circuit. 3. An instruction memory in which instruction words for instructing various internal operations are stored, a pipeline register for temporarily storing an instruction output from the instruction memory, and an instruction word for reading out the instruction words from the instruction memory. A sequence control circuit having at least a next address selector for selecting an address, a mask pattern value for selecting a plurality of external state signals input from the outside, a bit pattern value indicating a condition, and a code control A condition register whose value is set in advance, an output from the condition register and an output from the pipeline register are input, and the value set in the condition register is selected based on the contents of the pipeline register. A condition value selector that outputs the mask pattern value, the bit pattern value, and the value for the code control, and an external state signal A mask circuit that masks the bit pattern with the mask pattern and outputs the obtained bit pattern is compared with the bit pattern output by the mask circuit and the bit pattern output by the condition value selector. True or false, a comparator that outputs a false signal when there is a disagreement, and the output of the condition value selector is used to determine the polarity of the signal output by the comparator, and the result is sent to the next address selector to the next address. A sequence control circuit comprising: a code controller for outputting as a selection signal, the next address selector selecting an address in accordance with the next address selection signal.