JPH01236327A - Interruption mask control method - Google Patents

Abstract

PURPOSE:To control an expanded interruption mask by naturally expanding the operation of an already existing instruction. CONSTITUTION:A mask register 10 has eight bits composed of I/O interruption mask 0, I/O interruption mask 1, I/O interruption mask 2, I/O interruption mask 3, external interruption mask, program interruption mask, machine check interruption mask, and address conversion control bit in the described order. In case of further increasing an interruption mask when the mask register 10 is fully used, an additional register 12 is used for housing an expansion mask bit B. Data writing or data updating to the mask register 10 is performed by using already existing machine words. In addition, a register 14 is provided to supplying write/update data to the register 12 for housing the expansion mask bit B.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a method for controlling a mask that controls interrupts to a central processing unit (CPU), the present invention provides a method for controlling an extended interrupt mask by naturally extending the operation of an existing instruction. In an interrupt mask control method for expanding interrupt paths that cannot be allocated to existing mask registers, the method includes: a register accommodating expansion mask bits; a register accommodating flag bits that are operands for the mask bits; and a circuit for updating the extended mask bits with the flag bits according to the control signal output by the instruction decoder, so that the existing mask register and the extended mask bit storage register are simultaneously updated by executing an existing machine language instruction. Configure.

[Industrial application field]

The present invention relates to a mask control method for controlling interrupts to a central processing unit (CPU).

For example, the interrupt mask consists of an 8-bit register,
Write data 00101101 to this register and
．． 5.6. Control is performed such that interrupt number 8 is accepted and other interrupts are not accepted. If the data written to the register is changed to, for example, 11010010, the above will be reversed.

There are systems in which the requests of a large number of input/output devices (Ilo) are shared and processed by multiple CPUs, but in such systems, the interrupt mask determines the Ilo that each CPU is responsible for, and changing the interrupt mask data is It is in charge of this and performs control such as changing the value to 0.

[Conventional technology]

When extending the interrupt paths to the CPU, for example, when changing the above 8 paths to 9 paths, a new interrupt mask must be provided to control the interrupts on the 9 paths. However, if a register with an interrupt mask (hereinafter referred to as register A) does not have an empty bit in which to place a new mask bit, the new mask will be provided in another register (hereinafter referred to as register B). In this example, register B may be one register having a bit number of 9 bits or more, or it may be two registers, the conventional 8-bit register and another register.

In any case, the operand of the existing machine language instruction prepared to control register A only corresponds to register A, so this machine language instruction cannot obtain the operand necessary to control register B. I can't. Therefore, it is necessary to obtain the operand for register B by another method.

Conventionally, this problem has been dealt with by using an existing machine language instruction for controlling register A together with a new machine language instruction that can control both register A and register B. In other words, when controlling only register A, an existing machine language instruction is used, and the necessary operands are obtained by the existing machine language instruction as before, whereas register B with an extended interrupt mask is used. If you wanted to control both at the same time, you used new machine language instructions to obtain operands.

[Problem to be solved by the invention]

With this method of using two machine language instructions, the work involved in creating machine language instructions increases, the speed of newly created machine language instructions tends to be slower than conventional instructions, and the machine language This causes problems such as the instruction system becoming complicated and debugging becoming difficult.

The present invention aims to also control extended interrupt masks by naturally extending the operation of existing instructions.

(Means for solving the problem) Figure 1 shows a mask register.
O has 8 bits, each bit in turn: 110 interrupt mask 0.110 interrupt mask 1, i10 interrupt mask 2
, I/1 interrupt mask 3, external interrupt mask, program interrupt mask, machine check interrupt mask, and address conversion control bit. In this way, when the mask register is fully used, another register is used to further increase the interrupt mask, and 12 is an additional register for accommodating the extended mask bit B.

Writing or updating data to the mask register 10 is performed using machine language instructions, and in the present invention, existing machine language instructions (for the mask register 10) are used.

Further, in the present invention, a register 14 is provided for supplying write/update data (flag pins 1-F) to the register 12 that accommodates the extended mask bit B.

FIG. 2 shows an additional circuit for extended mask bit B.
FIG. 3 shows a write/update circuit for mask register 10. The circuit shown in FIG. 2 is installed alongside the circuit shown in FIG. 3.

[Effect]

According to the above configuration, registers 10 and 12 can be updated simultaneously by executing the modified machine language instruction, and even when expanded in this way, each bit of the interrupt mask can be updated simultaneously. However, since the update data to the register 12 is not given by the operand of the machine language instruction, the data (flag bit F) is written in the register 14 in advance and then supplied. Therefore, although the operation is two-stage, the mask register is updated at one time.

〔Example〕

Writing/updating of mask data will be explained in detail with reference to FIGS. 2 and 3.

FIG. 3 shows the existing part, 20 is a system bus interface, to which a memory 22, an instruction code register 24, and a read operand register 28 are connected. An instruction decoder 26 decodes the instruction code taken into the register 24 and outputs a control signal S and the like.

30 is an arithmetic unit that performs processing such as calculating the contents of the register 28 and the register 10 and storing the result in the register 10 again.

FIG. 2 shows a part added in the present invention, which includes a selector 32, an AND gate G1, an OR gate G2, and registers 12 and 14. Register 12.14 therefore bits B, F are
Although one bit is assumed here, it is of course possible to use a plurality of bits, and in the case of a plurality of bits, a plurality of circuits shown in FIG. 2 are provided.

It is assumed that the mask register 10 has 8 bits as shown in FIG. 1, and 1 bit is added to this to make the mask register 9 pins in total. It is also assumed that the mask register is updated using the following three types of instructions.

-And Mask instruction: calculates the logical product of the operand value and the mask register value, and stores this value in the mask register.

■Or Mask instruction: Calculates the logical sum of the operand value and the mask register value, and stores this value in the mask register.

■Load Mask instruction: Loads the value of the operand into the mask register.

A 1-bit flag bit F is provided for the added 1-bit mask bit B. This flag bit F is
It is allocated to the control register (register 14) in the control register (register 14) and updated by the existing Load Control instruction. The circuit shown in FIG. 2 is provided for the expanded mask bits.

The register 24 takes in the command sent through the system bus interface 20, and the decoder 26 decodes it. If it is found that this is an And, Or, or Load Mask command, or none of these, the decoder A control signal S indicating this is output.

As a result, the following control is performed in FIG.

(a) And Masklor Mask/Load
In the case of instructions other than Mask: the path (■) in FIG. 2 is selected, the contents of register 12 are simply written to register 12 again, and the value of expanded mask bit B remains unchanged.

(In the case of the blAnd Mask instruction, 20 paths are selected, and the AND of the extended mask bit B and flag bit F is stored in the register 12, which becomes the new extended mask bit B.

(In the case of the crawl Mask instruction: the path (■) is selected, and the logical sum of the expanded mask bit B and the flag bit F becomes the new expanded mask bit B.

(In the case of the di Load Mask instruction: the route (■) is selected, the contents of the register 14 are sent to the register 12, and the flag bit F becomes the extended mask bit B as is.

The flag bit F of the register 14 is set by another instruction before the above control. Thus, by presetting the flag bit, the existing And Mas
The extended mask bits can be updated naturally by the klor Mask/Load Mask instruction.

The control signal S is also given to the arithmetic unit 30 and the register 10 in FIG. The operation (AndOr, Load, Through) specified by is performed and the result is stored in the mask register 10. The processing in FIG. 3 and the processing in FIG. 2 are performed simultaneously by the control signal S, thus making it possible to update each bit of the extended interrupt mask simultaneously.

Each bit of the interrupt mask requires simultaneous updating. With sequential updates, if two interrupts occur at the same time during an update, the interrupt for the updated route will be processed after the update, and the interrupt for the unupdated route will be processed before the update, resulting in unexpected behavior. .

〔Effect of the invention〕

As described above, according to the present invention, an extended interrupt mask can be controlled without creating new machine language instructions. The part to be changed is to add the circuit shown in FIG.
Just add it to the circuit shown. If the extended interrupt mask is controlled using this method, the execution speed of existing machine language instructions will not change, there will be no need to change the machine language instruction system, and debugging will not become difficult. Therefore, it greatly contributes to improving programming efficiency.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the mask register of the present invention, FIG. 2 is a circuit diagram showing a portion added by the present invention, and FIG. 3 is a block diagram showing the configuration of the existing portion. In Figures 1 to 3, 10 is an existing mask register, 12
is an additional mask register, 14 is a register that accommodates flag bits, Gl and G2 are gate circuits, 32 is a selector,
26 is an instruction decoder.

Claims (1)

[Claims] 1. An interrupt mask control method when extending an interrupt path that cannot be allocated to an existing mask register (10), comprising: a register (12) that accommodates an extension mask bit (B);
A register (14) that accommodates a flag bit (F) that is an operand for the mask bit, and a circuit (G_1) that updates the extended mask bit with the flag bit in accordance with the control signal (S) output from the instruction decoder (26).
, G_2, 32), and the existing mask register and the extended mask bit storage register are simultaneously updated by executing an existing machine language instruction.