JP3588368B2 - Timer update assist method and timer device - Google Patents

Description

[0001]
[Industrial applications]
The present invention is provided with various timer mechanisms for controlling the execution time and the waiting time of the CPU, and does not have hardware bits higher than any bits of the various timer mechanisms. The present invention relates to a timer update assist method and a timer device in a computer in which firmware such as a microprogram controls using an area.
[0002]
Generally, in computer systems, high-speed processing and miniaturization of devices are desired, and similarly, high-speed and miniaturization of timer mechanisms are also desired.
[0003]
[Prior art]
FIG. 5 shows an example of a conventional timer.
In the conventional computer system, as shown in FIG. 5 (a), all bits of a timer mechanism for controlling the execution time and the waiting time of the CPU are provided as hardware logic 50. As shown in FIG. 7, instead of having all bits in hardware, bits higher than a certain bit are placed in the work area 51 of the microprogram, and only lower bits are provided as hardware logic 53. Is monitored, and when the update request flag 52 becomes "1" (ON) due to overflow of the hardware logic 53, a higher-order bit is controlled.
[0004]
The former method is used for a large computer, but generally, for a small computer, the amount of hardware is considerably limited. Therefore, a method in which all bits are implemented by hardware is not often used. In the example shown in FIG. 5B, of the 56 bits from 0 to 55, the upper 32 bits are placed in the work area 51 of the microprogram, and the lower 24 bits are provided as the hardware logic 53. In the following example, an example of a subtraction type timer will be described.
[0005]
FIG. 6 is a flowchart of the microprogram processing when the upper bits of the timer mechanism are included in the work area of the microprogram. FIG. 6A shows processing of a timer update request, and FIG. 6B shows processing of a timer read command.
[0006]
When the count value of the hardware logic 53 shown in FIG. 5B changes from (000000) ₁₆ to (FFFFFF) ₁₆ , the update request flag 52 changes to "1" and a timer update request is issued to the microprogram. It is. (XX ...) ₁₆ represents a hexadecimal number. (A) to (c) in the following description correspond to (a) to (c) shown in FIG.
[0007]
(A) When the update request flag 52 becomes “1”, the microprogram reads the timer high-order bit in the work area 51 of the microprogram.
(B) 1 is subtracted from the read upper bit data.
[0008]
(C) The result of the subtraction is written in the work area 51 of the microprogram.
When a timer read command is issued by the operating system or the like, the microprogram executes the processes (d) to (k) shown in FIG.
[0009]
(D) Read the upper bits of the work area 51 of the microprogram.
(E) Next, the lower bits of the hardware logic 53 are read.
(F) Read the update request flag 52 of the hardware logic.
[0010]
(G) It is determined whether or not the update request flag 52 is “1”. If not, the process proceeds to processing (i).
(H) If the update request flag 52 is “1”, 1 is subtracted from the upper bits read from the work area 51.
[0011]
(I) Next, an addition process of the upper bit and the lower bit is performed.
(J) Write the upper bits to the work area 51 of the microprogram.
(K) Write the processing result of (i) to the operand area specified by the timer read instruction.
[0012]
[Problems to be solved by the invention]
In a conventional computer, as shown in FIG. 6, when a microprogram executes a timer read instruction, an update request flag 52 which is a timer update request signal from the most significant bit of the hardware logic 53 is set. It is necessary to read the data, determine the result, and perform the subtraction processing of the upper bits held in the work area 51 of the microprogram. This is because the update request flag 52 may be set to "1" depending on the timing during execution of the timer read instruction, and overflow from the lower bits may not be reflected in the upper bits. Therefore, the number of static instruction steps and the number of dynamic steps of the microprogram have to be increased.
[0013]
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems, to reduce the instruction storage area of a microprogram, and to reduce the number of dynamic steps of the microprogram.
[0014]
[Means for Solving the Problems]
In the present invention, for example, as shown in FIG. 1, a data extension circuit 14 for extending the value of a timer update request flag 13 is provided, and when a CPU timer (lower bit) 10 of hardware is read, a microprogram work register is used. (A) Data obtained by expanding the value of the update request flag 13 by the number of high-order bits is added to the high order of 15. Further, the CPU reads the value of the CPU timer (upper bit) 12 of the microprogram work area 11 into the microprogram work register (B) 16 and adds this value to the value of the previous microprogram work register (A) 15 to perform an addition operation. Is added by a device (ADDER) 17. The result of the addition is stored in the microprogram work register (C) 18, and this value is notified to the issuer of the timer read command.
[0015]
[Action]
When the update request flag 13 is “0”, (00000000) ₁₆ is placed in the upper bit by the data extension circuit 14, and when the update request flag 13 is “1”, (FFFFFFFF) ₁₆ is placed in the upper bit. Processing can be performed uniformly regardless of the value of the request flag 13.
[0016]
【Example】
FIG. 1 shows a configuration example of the present invention.
The timer of the present embodiment is a subtraction type CPU timer, which is composed of 56 bits, of which the upper 32 bits are provided in the microprogram work area 11 as the CPU timer (upper bit) 12, and the lower 24 bits are hardware. Provided as a CPU timer (low order bit) 10 by logic. The update request flag 13 is a circuit that holds an update request signal from the most significant bit of the CPU timer (lower bit) 10. Set to “1” when the value of the CPU timer (lower bit) 10 changes from (000000) ₁₆ to the value of (FFFFFF) ₁₆ .
[0017]
The data extension circuit 14 is a circuit that extends the value of the update request flag 13 to 32 bits. When reading the CPU timer (lower bit) 10 into the microprogram work register (A) 15, the value of the CPU timer (lower bit) 10 is loaded into the microprogram work register (A) 15 from the 32nd bit to the 55th bit. At the same time, the update request flag 13 is extended to the data extension circuit 14 and loaded from the 0th bit to the 31st bit of the microprogram work register (A) 15. The extension of this data is (00000000) ₁₆ when the update request flag 13 is “0”, and (FFFFFFFF) ₁₆ when the update request flag 13 is “1”.
[0018]
The CPU timer (high-order bit) 12 provided in the microprogram work area 11 is loaded from the 0th bit to the 31st bit of the microprogram work register (B) 16.
[0019]
The adder 17 adds the values of the microprogram work register (A) 15 and the microprogram work register (B) 16 and outputs the result to the microprogram work register (C) 18.
[0020]
FIG. 2 is a processing flowchart of the microprogram according to the embodiment of the present invention.
When a timer update request is made, that is, when the update request flag 13 becomes "1", a timer update process of the microprogram is started by an interrupt or the like. Here, the processes (a) to (d) shown in FIG.
[0021]
(A) The CPU timer (upper bit) 12 provided in the microprogram work area 11 is read into the microprogram work register (B) 16.
(B) The CPU timer (lower-order bit) 10 of the hardware logic is read out to the microprogram work register (A) 15 together with the extended update request flag 13 data.
[0022]
(C) Add the value of the microprogram work register (A) 15 to the value of the microprogram work register (B) 16 and store the result in the microprogram work register (C) 18.
[0023]
(D) Write the upper 32 bits of the microprogram work register (C) 18 to the area of the CPU timer (upper bits) 12.
In response to the timer read command, the microprogram executes the processes (e) to (i) shown in FIG.
[0024]
(E) Read the CPU timer (upper bit) 12 provided in the microprogram work area 11 into the microprogram work register (B) 16.
(F) The CPU timer (lower-order bit) 10 of the hardware logic is read out to the microprogram work register (A) 15 together with the data of the extended update request flag 13.
[0025]
(G) Add the value of the microprogram work register (A) 15 to the value of the microprogram work register (B) 16 and store the result in the microprogram work register (C) 18.
[0026]
(H) Write the upper 32 bits of the microprogram work register (C) 18 to the area of the CPU timer (upper bits) 12.
(I) Write the upper 32 bits of the microprogram work register (C) 18 to the operand area specified by the timer read instruction.
[0027]
As is clear from the above processing, the processing of (a) to (d) and the processing of (e) to (h) can be shared.
FIG. 3 shows an execution example when there is no timer update request in the embodiment of the present invention.
[0028]
Now, it is assumed that the count value of the CPU timer (upper bit) 12 is (AAAAAAAAA) ₁₆ and the count value of the CPU timer (lower bit) 10 is (012345) ₁₆ . When the update request flag 13 is “0” in response to the timer read command, the data of (0000000000001234500) ₁₆ is written in the microprogram work register (A) 15. When this value is added to the value of the microprogram work register (B) 16 on which the upper-bit data (AAAAAAAAA00000000) ₁₆ is loaded by the addition calculator 17, the timer value obtained in the microprogram work register (C) 18 is obtained. AAAAAAAAA01234500) ₁₆ is obtained.
[0029]
FIG. 4 shows an execution example when there is a timer update request in the embodiment of the present invention. The values of the CPU timer (upper bit) 12 and the CPU timer (lower bit) 10 are the same as in the example of FIG.
[0030]
When the update request flag 13 is “1”, the data of (FFFFFFFF01234500) ₁₆ is placed in the microprogram work register (A) 15 in response to the timer read instruction. This value is added to the value of the microprogram work register (B) 16 on which the upper bit data (AAAAAAAAA0000000000) ₁₆ is loaded by the adder 17. The result output to the microprogram work register (C) 18 is (AAAAAAA901234500) ₁₆ . The upper 32 bits of this result are the same as the result of subtracting 1 from (AAAAAAAAA) _{16. When} the update request flag 13 is "1", the upper bits are automatically subtracted.
[0031]
【The invention's effect】
As described above, according to the present invention, the number of dynamic steps (the number of execution steps) of a microprogram can be reduced by adding a small amount of hardware. Further, the execution step at the time of the timer update request and the execution step of the timer read command can be shared.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of the present invention.
FIG. 2 is a processing flowchart of a microprogram according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating an execution example when there is no timer update request in the embodiment of the present invention.
FIG. 4 is a diagram illustrating an execution example when a timer update request is issued in the embodiment of the present invention.
FIG. 5 is a diagram illustrating an example of a conventional timer.
FIG. 6 is a processing flowchart of a conventional technique.
[Explanation of symbols]
10 CPU timer (lower bit)
11 Micro program work area 12 CPU timer (upper bit)
13 Update request flag 14 Data extension circuit 15 Microprogram work register (A)
16 Microprogram work register (B)
17 Addition arithmetic unit 18 Micro program work register (C)

Claims (2)

A timer comprising an n-bit counter used in a computer, wherein the lower m (m <n) bits of the n bits are constituted by a hardware counter, and the upper (nm) bits use a firmware work area. A timer update assist method for generating an update request signal when the hardware counter of the lower m bits reaches a predetermined value and updating the upper (nm) bits by firmware.
A timer update operation is performed by calculating a timer value held in a work area of the firmware by using a signal obtained by expanding the update request signal by upper (nm) bits, thereby updating the work area of the firmware. Assist method. A timer device comprising an n-bit timer is constituted by an m-bit hardware counter (10) and a (nm) -bit firmware work area (11).
A circuit (13) for holding an update request signal generated when the hardware counter changes to a predetermined value;
A data extension circuit (14) for extending the update request signal to (nm) bits;
A timer device comprising: a circuit (17) for adding a timer value to which data expanded by the data expansion circuit is added and a timer value including data of a work area of the firmware.

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