JPH01114940A - Signal processor - Google Patents

Abstract

PURPOSE:To easily change a program on the basis of an instruction from a host processor and to improve the flexibility of signal processing by forming a writable instruction memory, an instruction memory control part, etc., in a signal processor. CONSTITUTION:When necessity for changing the processing contents of the signal processor 22 is generated in the host processor 21, a hold request signal 23 for requesting the temporary stop of instruction word execution is set up in the processor 22. Immediately after ending the instruction being executed, the processor 22 outputs a hold allowable signal 24, stops the updating of a program counter 25 and temporarily stops the execution of the instruction word. Then, an instruction address 28 for specifying which address in the writable instruction memory 27 is to be rewritten and a selection signal 30 are outputted from an instruction memory control part 26. The address 28 is also outputted to an external instruction memory 31 and an instruction word 32 is outputted and written in the memory 27. Consequently, a program can be easily changed by an instruction from the processor 21 and more flexible signal processing can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing device that performs calculations mainly aimed at signal processing.

[Conventional technology]

Figure 5 was shown, for example, in the 1986 IEICE Telecommunications Division National Conference Symposium Proceedings (NIIS 1 G-1). 1 is a simplified block diagram showing a signal processing device controlled by a processor. (1) is a host processor that controls the signal processing device; (21 is a signal processing processor that mainly performs signal processing; 131 is an instruction memory); A selection signal, f41 is a reset signal that initializes the signal processing processor (21), (5) is a program counter (hereinafter abbreviated as PC),
16) is an instruction address, (7) is a read-only instruction memory (8) in which an instruction word is stored in advance, and external instruction memo IJ is also in which an instruction word is stored. 191 is an instruction address for selecting one of the two instruction words. A switching circuit for selecting by signal (3), α1 is an instruction word register (hereinafter r
(abbreviated as R), αD is a decoder that decodes the instruction word,
Ua is an arithmetic processing unit that performs various arithmetic processes, α3 is a control signal, aa is a data memory storing arithmetic data for signal processing, and α9 is arithmetic data. Further, FIG. 6 is a flowchart for explaining the operation.

Next, the operation of this signal processing will be explained based on FIGS. 5 and 6. First, when the power is turned on, the host processor 11) starts operating, and the signal processing processor 12) starts operating.
A selection signal +31 is output for selecting whether to use an internal or external instruction memory. The selection signal (the internal instruction memory is selected when the logic value of 31 is 10", and the external instruction memory is selected when the logic value is 11").Then, the host processor 111 outputs the reset signal 14 to the signal processing processor (2). . The signal processing processor (2) generates a reset signal (4
), it initializes the internal registers, etc.
The value of C+51 was set to zero.

Next, the instruction address (6) indicating address a output from PC (5t) is input to the read-only instruction memory (7) inside the signal processing processor (2) and the external external instruction memory (8), and the address The command words are read out and inputted to the switching circuit (9).The switching circuit (9) selects one of the command words by the selection signal (31) given from the host processor 111, and sets it to IRQ. The instruction word set to IRQ[l is sent to the decoder αυ
The data is decoded to generate control signals for each part. The arithmetic processing unit α2 inside the signal processing processor (2) receives the control signal from the decoder aυ! controlled by 13,
Various calculations are performed on the calculation data α9 in the data memory α4.

When performing complex signal processing with conventional equipment.

As programs tend to become larger, the program capacity of the read-only instruction memory (7) inside the signal processing processor (2) is insufficient and an external instruction memory (8) must be used. When using external instruction memory (8).

Input/output elements are required to output the instruction address (6) and input the instruction word using external terminals to exchange internal signals and external signals of the signal processing processor (2).

The time required to read an instruction word increases due to the extra elements required for reading from the internal read-only instruction memory (7). Therefore, when using the external instruction memory (8), a long-cycle clock must be given to the signal processing processor +2), and after switching the instruction memory, a reset signal (4) must be input and the initial If the settings are not made, it will malfunction.

In addition, the read-only instruction memory (7) inside the signal processing processor (2) is composed of a so-called mask ROM in which a program is written in advance when the processor is manufactured. It is designed to write .

[Problem that the invention sought to solve]

Conventional signal processing devices are configured as described above, and in order to have the signal processing processor perform complex processing or other processing, an external instruction memory is provided.

It is necessary to read and execute commands from outside.

A time loss occurs when reading the instruction words from outside.

In addition to halving the processing efficiency, the instruction memory inside the signal processing processor is a write-only memory, so it is not possible to change the program after the processor is manufactured, and if there is an error or correction in the program, the processor must be manufactured again and the signal processing There were problems such as the need to replace the processor itself, which led to low development efficiency and uneconomical performance.

This invention was made to solve the above-mentioned problems, and allows programs to be easily changed based on instructions from a host processor.

To obtain a signal processing device that can flexibly change processing, such as allowing a signal processing processor to execute complex processing or other processing temporarily, without adding significant hardware or reducing processing efficiency. The purpose was to

[Means for solving problems]

The signal processing device according to the present invention uses a writable instruction memory as an instruction memory inside the signal processing processor, and controls the suspension and restart of the signal processing processor according to instructions from a host processor, and also controls writing and reading of the writable instruction memory. It was designed to be controlled.

[For production]

In the signal processing device according to the present invention, the operation of the signal processing processor is temporarily stopped by the host processor, and after the instruction memory inside the signal processing processor is rewritten, the operation is resumed and other processing can be performed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an example in which so-called verification is performed inside the processor to determine whether the contents written to the instruction memory inside the signal processing processor are correct. r2D is the host processor, ■ is the signal processing processor, and c! 3 is a hold request signal that requests a temporary stop of the instruction execution operation of the signal processing processor, r24 is a hold permission signal that notifies the outside that the instruction execution operation is temporarily stopped, and c! 9 is a program counter, ■ is an instruction memory control unit, ■ is a writable instruction memory that can be rewritten, and @ is an instruction address.

■ is the switching circuit, C31 is the selection signal, and 0υ is the external command memo! J, G3. C (3 is the instruction word, (to) is the comparison circuit, C
6 is the determination result, and (to) is the write end signal. Note 1
In the figure, the arithmetic processing section is omitted because it is the same as in the conventional example.

Moreover, FIG. 2 is a flowchart for explaining the operation.

The operation will be described below based on FIGS. 1 and 2. In the host processor, when it becomes necessary to change the processing content of the signal processing processor 4, a hold request signal is set to the signal processing processor port to request a temporary stop of execution of the instruction word. When the signal processing processor receives a hold request, it immediately outputs a hold permission signal Q4 as soon as the currently executed instruction is completed, and the PCc
The update of a is stopped, and the execution of the instruction word is temporarily suspended.

Next, the instruction memory control unit (to) outputs an instruction address (to) that specifies which address in the writable instruction memory is to be rewritten, and a selection signal ■ to select the instruction address G from the switching circuit. be done. The instruction address (to) is simultaneously output to the external instruction memory 00, from which the instruction word (to) is output and written to the writable instruction memory (2). The instruction word (to) written in the writable instruction memory is read out again from the writable instruction memory, and the read instruction word (to) and the written instruction word (to) are compared to the comparison circuit (to).
A determination is made as to whether the two command words match. If the two instruction words do not match, an error has occurred when writing to the writable instruction memory surface.

Based on the determination result (to), a write error flag inside the instruction memory control unit (to) is set. This flag is not reset until all writes are completed.

The above operation is repeated until writing of one instruction word is completed and rewriting of all instruction words is completed.

After all the writing has been completed, the state of the write error flag in the instruction memory control unit (2) is checked, and if it is set, the flag is reset and writing of the instruction word is started again.

If the write error flag is not set and the rewriting is completed normally, the write end signal (to) is sent to the host processor C! Output to υ.

The host processor 3υ cancels the hold request signal and cancels the - time stop. When the hold request signal Q is released in the signal processor 4, the instruction memory control section outputs a selection signal (to) so that the switching circuit 2 selects the instruction address of the PC 2.

The PC (to) updates the instruction address, and when stopping at -, the instruction is executed from the instruction address next to the instruction address of the last executed instruction word. By making the instruction memory inside the signal processing processor rewritable in this way, it becomes possible to easily change the contents of signal processing. Additionally, a helifi circuit is built inside to prevent malfunctions of the processor due to rewriting errors.

Further, FIG. 3 shows an embodiment in which a determination circuit for determining whether the contents of the writable instruction memory are correct is provided outside the signal processing processor, and FIG. 4 shows a flowchart for explaining its operation.

The operation will be described below based on FIGS. 3 and 4. As in the case of Fig. 1, when it becomes necessary to change the processing contents of the signal processing processor +43 in the host processor circle, the hold request signal is set and the PC (
c) The update is stopped and the execution of the instruction word is temporarily suspended. Upon receiving the hold permission signal Q4, the host processor
From there, the instruction address (to) is output to the external instruction memory r3υ and the signal processing processor 93. External command memo 11
The instruction word (to) read from ) is input to the switching circuit 93, and then input to the signal processing processor by the selection signal 1441 from the host processor I. Next, in response to the write control signal 4 from the host processor I, a selection signal is output from the instruction memory control section (c) to the switching circuit complement, and the instruction number is written into the writable instruction memory (3). Next, a read control signal (49) is output from the host processor 14tl, and the written instruction word is read out from the writable instruction memory, and from the instruction memory control unit to the switching circuit C.
A selection signal (b) is output to η, and the command C is output to switching circuit I.
is input to. Selection signal 14 from host processor circle
4, the command word is input to the comparator circuit. The comparison circuit ω compares the instruction word read from the external instruction memory 17 C1υ with the instruction word read from the writable instruction memory Q'n, and outputs the determination result (51) to the host processor I. do. Based on the determination result (51), the host processor f40 executes writing of the next instruction word if the two instruction words match. If the two instruction words do not match, writing of the instruction word is executed again. When all writing is completed, host processor I releases hold request signal Q.

By restarting the operation of the signal processor 43, the same effects as in the embodiment shown in FIG. 1 can be achieved.

In addition, in this example, mXn (m is an integer of 1 or more, n
is an integer of 2 or more) When reading a bit-width instruction word from an external instruction memory and inputting it to a signal processing processor,
However, by dividing the data into bit widths of m bits and writing into the internal writable instruction memory n times, m external terminals can be used. For example, when inputting a 32-bit wide instruction word, to input it in -degrees, 32 bits are input.
If external terminals are required, divide them into 8-bit widths.

If the input is divided into 4 times, it becomes possible to input with only 8 external terminals, and it takes 4 times the time to rewrite, but it is a very effective method when the number of external terminals is limited. Become.

〔Effect of the invention〕

As described above, according to the present invention, the instruction memory inside the signal processing processor is made into a removable instruction memory, and its operation is temporarily stopped by instructions from the host processor, and the instruction memory inside the signal processing processor is replaced. With this configuration, the program can be changed at will after the processor is manufactured, making development efficient and economical.In addition, the program can be rewritten by temporarily stopping instruction execution even during signal processing.

By restarting instruction execution, it is possible to perform more complex signal processing and to provide a single signal processing processor with various signal processing functions, which has the effect of allowing more flexible signal processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a signal processing device according to an embodiment of the invention, FIG. 2 is a flowchart explaining the operation of the embodiment of FIG. 1, and FIG. 3 shows another embodiment of the invention. A block diagram showing a signal processing device, FIG. 4 is a flowchart explaining the operation of FIG. 3, FIG. 5 is a block diagram showing a conventional signal processing device, and FIG. 6 explains the operation of the conventional example shown in FIG. This is a flowchart. Qυ is a host processor, 123 is a signal processing processor, 0 is a hold request signal, c! 4 is a hold permission signal;
田 is the program counter, Oe is the instruction memory control unit, punishment is the writable instruction memory, @ is the instruction address, (to) is the switching circuit, ■ is the selection circuit, GO is the external instruction memory, country, ■ is the instruction word, C (41 is a comparison circuit, (to) is a determination result, and (lfi is a write end signal.) In FIG. 1, the same reference numerals indicate the same or equivalent parts.

Claims (4)

[Claims] (1) A processor that mainly performs signal processing and is equipped with a writable instruction memory for storing command words instructing various internal operations, a means for instructing the suspension and resumption of the processor operation, and a writable In a signal processing device comprising an instruction memory storing instruction words to be written in the instruction memory and a host processor connected to the instruction memory and controlling them, the operation of the processor is temporarily stopped by an instruction from the host processor; The processor comprises means for reading an instruction word from an instruction memory and writing it into the writable instruction memory, and restarts the operation of the processor according to an instruction from the host processor after a predetermined writing is completed, thereby controlling the processing of the processor. A signal processing device configured to switch. (2) When reading an instruction word from the instruction memory and writing it to the writable instruction memory, an instruction address automatically generated from the processor is output to the instruction memory, and the read instruction word is written to the writable instruction memory. a comparison/determination circuit that reads and compares the instruction word read from the instruction memory and the instruction word written to the writable instruction memory and determines whether they match; and an output that outputs the determination result. The processor includes means for controlling the host processor to write the instruction word into the writable instruction memory again if the instruction word read from the writable instruction memory does not match the written instruction word. A signal processing device according to claim 1, characterized in that: (3) When an instruction word is read from the instruction memory and written to the writable instruction memory, the instruction word is read from the instruction memory according to the instruction address output from the host processor, and the instruction is output from the host processor. after writing to the writable instruction memory by an address and write control signal, reading from the writable instruction memory by a read control signal from the host processor;
The host processor determines whether the read instruction word and the written instruction word match, and if they do not match, the host processor controls to write the instruction word into the writable memory again. A signal processing device according to claim 1. (4) When reading an instruction word from the instruction memory or writing an instruction word to the writable instruction memory, an instruction word with a width of m×n (m is an integer greater than or equal to 1, and n is an integer greater than or equal to 2) bits is converted to m bits. 2. The signal processing device according to claim 1, wherein the signal processing device divides the signal into widths and performs reading and writing n times.