JP3125436B2 - Bit offset calculator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for calculating a bit offset amount.

[0002]

2. Description of the Related Art A conventional selecting means changes the bits taken in by a decoder according to the size information of an operand to be bit-operated, and determines the difference between the number of bits of the operand and the number of bits of the largest operand by a predetermined value using the offset data. An indirect offset amount control system that performs a bit operation is disclosed, for example, in Japanese Patent Application Laid-Open No. 1-134621. FIG. 8 is a block diagram of the conventional offset amount indirect designation control system.
Bit input bus, 81 is an input unit, 82 is a selector, 83
Is a decoder, 84 is an output circuit section, and 85 is an output bus. Offset data based on a bit instruction is taken into the input unit 10 of the 5-bit decoder circuit unit 1 via an internal bus, and the lower 5 bits of the taken data are output as valid data. The lower 3 bits of this data are supplied to the decoder 83, and the upper 2 bits are supplied to the decoder 83 via the selector 82. The decoder 83 converts the bit code into a numerical value. Then, the converted bit at the corresponding position is set to 1 and the other bits are set to 0, and the 32-bit data is output to the internal bus 7 via the output circuit unit 5 to reduce the load on the software and perform high-speed processing. I do.

[0003] Further, the base address of the operation target bit and the offset amount thereof can be obtained by controlling an adder, shift and mask means such as a barrel shifter, and a temporary register capable of saving data by a microprogram.

For example, when obtaining an offset, when controlled by a microprogram, an initial offset is first input to a shift means such as a barrel shifter, arithmetically shifted down by 3 bits, and 3 bits overflowing at the time of downshifting are stored in a temporary register. The initial address and the shifted-down offset are input to the adder and added, and the result is obtained by masking all bits except the lower 2 bits.

When the base address is determined by a microprogram, the initial address and the 3-bit arithmetically shifted down initial offset are input to a 32-bit adder, added, and then added through a bit mask means such as a barrel shifter. It is necessary to perform a bit mask according to the bit size specification. When bit masking is performed using a barrel shifter, for example, when it is desired to mask the lower two bits, first shift down by two bits,
By shifting up by 2 bits, the lower 2 bits are replaced with 0. However, such processing requires at least two clocks.

[0006]

However, in the above configuration, the base address cannot be obtained,
There is a problem that a 32-bit decoder is required, hardware is increased, and several clocks are required when controlled by a microprogram.

[0007]

The present invention solves the above problems.
An address bus for inputting an address to solve the problem;
Offset bus for inputting bit offset value
And a pair whose base is 2 in the bit length of the basic unit of data processing
The smallest unit of data that can be specified by address from the numerical value (M)
Of the bit length of the data minus 2
The number of packets is added, and input from the address bus is performed.
The lowest (MN) bits of the address
Least significant bit of the bit offset input from the
Adder for inputting the first (MN) bits of the
And the least significant N bits of the output have the offset bus
The least significant N bits of the bit offset value input from
And the higher-order (MN) bits are added to the adding means.
Bit offset amount characterized by outputting the output of
It relates to a computing device.

An address bus for inputting an address
And the minimum unit of data that can be specified by the address.
Logarithmic value (N) bit arithmetic shift down with base 2
Offset bus for inputting the bit offset
And an adding means for performing addition, and
Bit mask means for performing bit masking of bits
The output of the address bus is input to one input of the adding means.
And the output of the offset bus is
Connected to another input of the stage, the output of said adding means being
An access base connected to the input of the bit mask means;
The present invention relates to a address calculator.

Furthermore, an address bus for inputting an address
And an offset bar for entering the bit offset value.
And base 2 of the bit length of the basic unit of data processing
Minimum unit that can be specified by address from logarithmic value (M)
Logarithmic value (N) with base 2 of data bit length reduced
The number of bits is added, and the data is input from the address bus.
The lowest (MN) bits of the address to be
Least significant M of the bit offset input from the bit bus
Addition means for inputting the first (MN) bits of the bits
And a complement that outputs the complement of data according to the complement output signal
Output means, and the least significant N bits of the output are turned off.
The least significant bit offset value input from the set bus
N bits are output, and higher (M-N) bits are
The output of the adding means is output, and the output is the complement output.
Bit offset connected to the input of the means.
The present invention relates to a unit-complement calculator.

[0010]

According to the present invention, the least significant (MN) bits of the initial address are added to the first ( MN) bits of the least significant M bits of the initial offset and (MN) bits by the above configuration, and the offset is added. Determine the value and output the offset or the complement of the offset according to the offset complement output signal. The base address is obtained by adding the initial address and the initial offset shifted down by 3 bits and performing bit masking according to the designated size.

[0011]

FIG. 1 is a block diagram showing an offset amount calculating apparatus according to a first embodiment of the present invention. In the figure, 10 is an address bus for supplying a 32-bit initial address, 11 is an offset bus for supplying a 32-bit initial offset, 12 is a 2-bit adder, and 1
3 is a 3-bit bypass.

FIG. 2 is a block diagram showing a base address calculating apparatus according to the first embodiment of the present invention. In the figure, reference numeral 20 denotes an address bus for supplying a 32-bit initial address, and reference numeral 21 denotes 3 bits shifted down by 3 bits.
An offset bus that provides a 2-bit initial offset,
Reference numeral 22 denotes a 32-bit adder, and reference numeral 23 denotes a bit mask device.

Using the above-described device, a bit operation instruction,
When an arbitrary base address and an offset are given as an initial address and an initial offset by a bit field instruction and an arbitrary length bit manipulation instruction, respectively, an offset in a 32-bit word to be accessed (access offset) and a base at that time Calculate the address (access base address). In this embodiment, the processing unit is 32 bits, and the access address basic unit is 2 bits.
** N (N = 3) is 8 bits. The addition means required for calculating the offset amount is (M−N) (log2
(32/8)) = 2-bit addition means. When the processing unit is 64 bits, (M−N) = 3 bit adding means is required. The operation of each device shown in FIGS. 1 and 2 will be described below.

FIG. 3 is a diagram for explaining the operation of the adding means in the calculation of the access offset. The operation of FIG. 1 will be described below with reference to FIG. The two least significant bits of the initial address 10 and the first two bits of the least significant five bits of the initial offset 11, that is, the 27th bit and the 28th bit are input to the 2-bit adder 12, and a 5-bit offset is obtained by performing an operation. Find the first two bits of The lower 3 bits of the 5-bit offset are the same as the lower 3 bits of the initial offset, and are output from the initial offset bus 11 via the bypass 13. Thus, the access offset is obtained.

Actually, as an increase in hardware, an access offset and an access base address can be quickly calculated for microprogram control by adding three logical XOR gates and a logical NOR gate, which has the effect of increasing the operation speed. .

FIG. 4 is a diagram for explaining the operation of the addition means and bit mask means in the calculation of the access base address. The operation of FIG. 2 will be described below with reference to FIG. 32 bits initial address 20 and 3 bits shifted down 3
The 2-bit initial offset 21 is added to the 32-bit adder 22
And add to obtain the access base address.
By specifying the bit size, the lower two bits of the access base address are masked by a bit mask device. For example,
Assuming that the bit size is a halfword (16 bits), a halfword boundary access base address is obtained by masking the lower bits of the base address at the byte boundary. When the bit size is a word, the word boundary access base address is obtained by masking the lower two bits.

In practice, by inputting a word mask signal or a half word mask signal to the bit mask device, the byte boundary access base address, which is the output of the adder, is passed through the two-input logical AND gate to the lower two bits, respectively. Alternatively, it can be easily realized by masking the lower one bit.

The operation of the above-mentioned apparatus will be specifically described with reference to FIG. FIG. 7 is an explanatory diagram showing an access method of an operation target bit in a bit operation instruction and a bit field instruction. Referring to FIG. 7, when an initial offset and an initial address are given, the access base address and the access A method for obtaining the offset will be described. Assume that the initial address is 20h (h: hexadecimal number) and the initial offset is 1BCh. Since this initial offset is a bit offset, it is shifted down by 3 bits to obtain a byte offset.
h and the initial address 20h are added by 32 bits to obtain an access base address 57h. Next, the least significant two bits of the initial address, in this case, 00b (b: binary number) and the 27th and 28th bits of the initial offset, in this case, 11
b is added by 2 bits to obtain the upper 2 bits of the access offset. The least significant three bits of the initial offset, in this case, 100b are used as the least significant three bits of the access offset, and the access offset is 11100b (1C
h). FIG. 9 shows an access base address and an access offset for a byte, a halfword, and a word, respectively, by specifying the bit size.

FIG. 5 is a block diagram showing a complement output device according to a second embodiment of the present invention. In FIG. 5, 10 is an address bus for supplying a 32-bit initial address, 11 is an offset bus for supplying a 32-bit initial offset, 12 is a 2-bit adder, 13 is a 3-bit bypass, and 14 is a complement. Complement output device. As shown in FIG. 1, the calculation of the offset includes the least significant 2 bits of the initial address 10 and the initial offset 11
Of the least significant 5 bits, that is, the 27th bit and the 28th bit are input to the 2-bit adder 12, and the operation is performed to obtain the first 2 bits of the 5-bit offset. The lower 3 bits of the 5-bit offset are the same as the lower 3 bits of the initial offset, and 11 to 13
As an input to the complement output device 14 through the bypass of the comparator. An offset complement is output through a complement output device in accordance with the complement output signal.

FIG. 6 is a diagram for explaining a method of preparing a bit mask by using an offset complement. With reference to FIG. 6, the necessity of calculating the complement of an offset by a complement output device will be described.
For example, the 20th bit of a 32-bit word is an operation target bit in a bit operation instruction. Then, 20
A mask in which 1 is set at the bit is created, and a bit operation is performed. As a method of creating such a mask, the most significant bit is set to 1 and shifted down by an offset, or the least significant bit is set to 1 and shifted up by a complement of a 5-bit offset, offset (31-offset). It is easier to set the least significant bit to 1 than to set the most significant bit to 1. After the offset value is determined, the complement of the offset can be determined by using a logical NOT gate to realize a 5-bit offset faster than by microprogram control.

[0021]

As described above, according to the present invention,
The following effects can be obtained.

By providing an M-bit adder when obtaining the offset, the load on the software can be reduced and the processing speed can be increased.

When the base address is obtained, by providing the bit mask means, the load on the software can be reduced and the processing speed can be increased.

In the bit manipulation instruction, by providing a complement output means for outputting the complement of the offset, the load on the software can be reduced and the processing can be performed at high speed.

The operation can be realized at high speed by attaching such small hardware, and the practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram of an offset amount calculating device according to a first embodiment of the present invention;

FIG. 2 is a block diagram of a base address calculator according to the embodiment;

FIG. 3 is an explanatory diagram of an operation of an adding unit in calculating an offset.

FIG. 4 is a diagram illustrating the operation of an addition unit and a bit mask unit in the calculation of a base address.

FIG. 5 is a block diagram of an offset complement output device according to a second embodiment of the present invention;

FIG. 6 is an explanatory diagram of a bit mask creation method using an offset complement.

FIG. 7 is an explanatory diagram showing an access method of an operation target bit in a bit operation instruction and a bit field instruction.

FIG. 8 is a block diagram of a conventional offset amount indirect designation control system.

FIG. 9 is an explanatory diagram of a difference due to designation of a bit size.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Initial address bus 11 Initial offset bus 12 2 bit addition means 13 3 bit bypass 14 complement output means 22 32 bit addition means 23 bit mask means

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Kiyohara ▲ Taku ▼ 3 1006 Odakadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-2-306339 (JP, A) JP 63-282527 (JP, A) JP-A-3-19029 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/30-9/355 G06F 12/00-12 / 06

Claims (3)

(57) [Claims] And 1. A luer address bus to enter the address, and offset bus for inputting a bit offset value, the address from the value pairs to the base 2 of the bit length of the basic unit of data processing (M) The number of bits obtained by subtracting the logarithmic value (N) from the base 2 of the bit length of the smallest possible data is added, and the least significant (MN) bits of the address input from the address bus and the offset comprising a bit offset which is input from the bus least significant M bits within the head of the (M-N) adder means you enter a bit, bit to the least significant N bits of the output that is input from the offset bus A bit offset amount calculating device for outputting the N least significant bits of the offset value and outputting the output of the adding means to higher (MN) bits. Wherein a luer address bus to enter the address, the bit length of the data of a minimum unit that can be specified by the address 2
Logarithm to the base (N) bit arithmetic shift and offset bus to enter the down bit offset addition means for adding, bit mask means for performing bit <br/> mask of lower bits Ri by the mask signal The output of the address bus is connected to one input of the adding means, the output of the offset bus is connected to another input of the adding means, and the output of the adding means is connected to the input of the bit mask means. Access base address calculator connected to the input. 3. A luer address bus to enter the address, and offset bus for inputting a bit offset value, the address from the value pairs to the base 2 of the bit length of the basic unit of data processing (M) The number of bits obtained by subtracting the logarithmic value (N) from the base 2 of the bit length of the smallest possible data is added, and the least significant (MN) bits of the address input from the address bus and the offset comprising adding means you enter the (M-N) bits of the inner head of the M least significant bits of the bit offset input from the bus, the complement output signal complement output means for performing complement output of the data, the output Output the least significant N bits of the bit offset value inputted from the offset bus, and output the output of the adding means to the higher (MN) bits. Bit offset complement computing device, characterized in that it is connected to the output of said input of said complement output means.