JP2803788B2 - Fast pipeline shifter element with parity prediction and string control - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method for shifting an operand into a shift device.

BACKGROUND OF THE INVENTION Shift registers or shift devices have the ability to transfer information laterally. The shift register is usually
Its output represents an n-stage device consisting of n-bit parallel data words. Applying a single clock cycle to the shift register device shifts the output word one bit position from right to left (or left to right).
The leftmost (or rightmost) bit is lost from the "end" of the register, and the rightmost (or leftmost) bit position is loaded from the serial input terminal.

Shift registers having parallel outputs and having combinational logic supplied from the outputs are very important in digital signal processing and in the coding and decoding of error correction and error detection codes. Such registers are implemented in hardware or software,
It is binary or q-ary. (Hardware embodiments are typically only advantageous for binary and sometimes ternary logic.) Shift devices are commonly used with arithmetic and logic devices. FIG. 1 shows a block diagram of a prior art execution device including a shift device together with an arithmetic device and a logic device. Generally, all of these devices need to be matched in speed to avoid having unbalanced net length and signal propagation time. However, it may be important that the shift device, in particular, match the speed of the arithmetic logic unit.

In some applications, to perform a check on a group of binary numbers (eg, words, bytes, or characters), the parity function is generally calculated by forming a modulo-2 sum of the bits in the group. . The resulting sum or redundant value is called a parity bit. If the number in the original group is even, the parity bit is zero. If the number of ones in the original group is odd, the parity bit is one.

In the parity calculation just defined, the binary extended group (original group + parity bit) will have an even number of ones. This is called even parity. In some cases, it may be desirable to have an odd number of 1s in the extension group due to hardware considerations.
The parity bits are selected such that the total number of the parity bits becomes an odd number. This is called odd parity. A parity check or parity check is the computation of parity bits to determine if a defined parity condition exists, or recomputation for verification.

Shifting devices in applications that include a parity function, since the sum of the bits in each group is changing,
Parity must be restored after each shift operation. This is generally achieved by parity generation after the shift operation. As an additional security function, some applications further include a parity prediction function for predicting a new parity bit regardless of the occurrence of parity of the shift device. Comparing the generated parity bit with the predicted parity bit reveals the disadvantages of either the parity generator or the parity predictor if both parity bits do not match. However, such a parity analysis requires a certain amount of processing time and is therefore particularly important with respect to the required consistency of timing with other processing units.

As shown in FIG. 1, generally, the operand to be shifted (eg, 4 or 8 bits) is read from a data local store (DLS) and the operand register A REG is read.
Or input into B REG. During the next cycle, the data is processed in any one of the processing units, for example, shifted, and written back to the data-in register DI of the DLS. In a parity check system, the byte parity of the shifted data, for example, byte parity P0-P7
Occurs when an additional delay is added to the shifter path.

In a shift operation, for example, a computer based on IBM S / 390 typically performs a 4 or 8 byte shift right or left as a logical or arithmetic operation. In addition, all kinds of special microinstructions are usually executed by the shifting device. The shift amount is typically divided (for example, when a multiplexer with up to four inputs is included) into successively passing 32-16-8-4-2-1 bit shift elements. Therefore, a shift amount of 0 to 63 bits is possible. The level can be bypassed by passing it through. Shifting right or left is done by applying the appropriate multiplexer level to shift right / left.

Parity checking on the data path is generally achieved by generating byte parity.
In parity prediction, a complete double word (8 bytes) parity bit is generated and compared with the predicted double word parity bit. The predicted parity bits are achieved by selecting the byte parity bits of the bytes that are not shifted out. The other bytes are completely shifted out and replaced with zeros,
One byte is partially affected by the shift (one byte
~ 7 bits are shifted out).

If this method is applied to odd parity, the predicted parity is assumed to be the remaining byte parity bits and 1 (odd parity) for the byte parity bits completely shifted out and replaced by zeros. ) And the parity bits of the partially shifted bytes. The original parity bits of the partially shifted byte are flipped out by each one shifted out.

Shifters that shift up to 64 bits typically consist of six multiplexer levels for parity generation and two XOR levels. A shifter that shifts up to 32 bits consists of five multiplexer levels for parity generation and two XOR levels.
Parity prediction requires additional logic levels.

In general, the amount of shift in a byte (8-bit) oriented system is typically 1
-2--4-8-16-32 -...- k / 4-k / 2 bits are divided into shift elements, so that a total shift amount of 0 to k-1 bits is possible. If the amount of shift is greater than or equal to k for a k-bit word, it is usually meaningless because the word is shifted out and represents 0 regardless of the actual amount of shift. However, the signal needs to pass through several logic levels until the desired result is received.
This is very time consuming and a major drawback.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved shift device.

 The object of the invention is solved by the independent claims.

A new functional device is disclosed that can shift data in various ways and perform data truncation on either the left or right side. The speed advantage is achieved by utilizing a pipeline, for example, by dividing the execution into a number of cycles. All operations can be parity checked by predicting the correct parity.

In very general terms, the present invention discloses a shift structure that breaks down shift operations into parallel shifts that can be performed in different pipeline stages. In the first pipe stage,
The at least one partial shift is achieved by reading the operand and placing the operand or a portion of the operand in a register coupled to the shift device. The shift device finally completes the shift operation by performing the remaining partial shifts in the second pipe stage.
This reduces the overall time required for the shift operation, and also allows the partial shifts to be distributed to different pipeline stages to use the remaining time available in the cycle.

The shift device according to the present invention can further reduce the time required for the shift operation during the second cycle.

In the shift device according to the invention, in the first pipe (pipeline) stage, the operand to be shifted is read from the data store and input to one of two operand registers, each of length k / 2 bits. Here, k represents an integer. During the next cycle, in a second pipe stage, the data is processed in a k-bit long shifter and the data
Write to the register again. Also, an optional parity generation device and an optional parity prediction device can be applied to the shift device of the present invention.

The shift structure according to the invention splits the shift into both two pipe stages. Data stores can be individually or
Includes data having a maximum of k / 2 bits each, which can be read as a pair having a bit length. Further, the data store includes a multiplexing device that can place the data in any one of the operand registers.

The function of the multiplexer is part of the shift function and is controlled by a command controller well known in the art. The multiplexor places the k / 2-bit data to be shifted into one of the operand registers, and thus the k-bit data.
By placing it on the right or left side of the shift device,
Perform a 2-bit shift, thus representing a k / 2-bit shift element. Therefore, the shift device of the present invention has
-2-4-8-16-32 -... k / 4 bit shift element only required, and thus one shift element and therefore one shift element for shift devices known in the art.
Level can be saved.

Shift k-bit word left (right) consisting of two k / 2 data words from the data store> =
If shifting by k / 2, during the cycle of the first pipe stage, only the rightmost (leftmost) k / 2 data word is already k / 2
It must be read into the leftmost (right) register of the operand register representing the shift. A continuous shift is then applied by the shift device during the next cycle of the second pipe stage. Shift amount k / 2 already in the first pipe stage
Is implemented, only a total shift amount of k / 2-1 is required in the continuous shifting device of the second pipe stage.

Shifts to the left or to the right with an amount of shift <k / 2 are applied by the shift device only during the cycle of the second pipe stage.

The shift structure of the present invention provides k / 2 in the first pipe stage.
It should be understood that the invention is not limited to shifts only. Still, data can be read into multiple operand registers individually or in combination. The multiplexer then places the read data to be shifted in a plurality of operand registers. Depending on the number of operand registers and their respective bit lengths, different shift possibilities are achievable. For example, 4
K / 4 if one operand register is provided
A shift or k / 2 shift can be implemented. It should be understood that the number of shift levels and the amount of shift in each pipe stage depends on the time given in each cycle.

To further reduce the number of shift levels, and thus the time required for the shift operation, the shift device of the present invention
The shift operation is performed only in one direction, for example, only to the left. Operand bits are shifted in a circular fashion. The shift operation in the opposite direction is performed by shifting to the left by the complement shift amount.

Shifts within the shifter in a cyclic shift manner can be divided into successive shift levels. In general, each shift level allows a certain maximum number of shift gates n, p, q, etc., each having a different amount of shift. Here, n, p, q, etc. represent integers. For example, when applying CMOS technology, the maximum number of shift gates is usually limited to four.

At the first shift level, the next shift amount: 0, k /, where the distance between two adjacent shift amounts is k / (2n).
(2n), 2 * k / (2n), 3 * k / (2n), 4 * k / 2
n, ..., (n-2) * k / (2n), (n-1) * k / (2n)
Are possible up to n shift gates. Second
, The distance between two adjacent shift amounts is k / (2np): 0, k / (2np),
2 * k / (2np), 3 * k / (2np), 4 * k / (2np), ...,
A maximum of p shift gates with (p-2) * k / (2np) and (p-1) * k (2np) are possible. At the third shift level, shift amounts: 0, k / (2npq), and 2 *, where the distance between two adjacent shift amounts is k / (2npq).
k / (2npq), 3 * k / (2npq), 4 * k / (2npq), ...,
Up to q shift gates with (q-2) * k / (2npq) and (q-1) * k / (2npq) are possible. Each successive shift level determines the distance between two adjacent shifts by k /
(2II). Where II represents the maximum shift gate product of the previous shift level to the present. It is clear that each shift amount is only an integer and the last shift level ends with a shift amount of one.

As is evident from the above, the shift device according to the invention reduces the number of shift levels by at least one.
However, in a shift device using a cyclic shift method,
A further significant reduction of the shift level is possible. k / 2
If bit data needs to be shifted, an additional feature is that a copy function that can copy the contents from the operand register is required in the first pipe in the multiplexer.

The resulting data of the cyclic shift operation is, for example, leading / negative to receive the same result as the result from the linear shift operation.
More operations are often required, such as trailing zeros or sign extensions. In a linear shift of data ABCD EFGH (A to H represent individual bytes), the remaining bits of the original data are filled with additional zeros for shift out bits. For example, shifting right (24 bits or 3 bytes) to the data ABCD EFGH results in new data 000A BCDE. However, in this example of a cyclic shift,
Some processing is needed to produce the FGHA BCDE and thus receive the same result from the linear shift. Such processing is preferably performed by individual strings of bit values, such as a control string composed of bit or byte values that correct the cyclic shift result to a linear shift result. The shift amount is decoded into a string that defines the significant bits of the shift result.

Also, strings can control optional parity prediction. The string defines the validity of the data and arbitrarily selects the parity bits for parity prediction. The application of strings greatly reduces the amount of control logic required.

For optional parity prediction, the counting of ones shifted out of the partially shifted byte is preferably achievable only on one side, preferably on the side to which the bits are shifted in a circular fashion. This requires some processing of the data in the first pipeline stage, for example duplication of the data. This reduces the amount of logic circuits that must pass through in the parity prediction logic.

The shift structure of the present invention can be used, for example, in an execution device that performs data operations in a processor device that is part of a processor chip.

Description of the drawings The invention will now be described by way of example with reference to the accompanying drawings.

FIG. 1 is a block diagram of a prior art execution device including a shift device as well as an arithmetic device and a logic device.

 FIG. 2 is a diagram showing a shift device according to the present invention.

FIG. 3 is a diagram showing the structure of one embodiment of the shift device 10 using the cyclic shift method.

FIG. 4a is a diagram illustrating the structure of an embodiment of the shift device 10 and the part 30a of the optional parity prediction device 30 by the cyclic shift method.

FIG. 4b shows the structure of one embodiment of the optional parity prediction device 30b and the optional parity generation device 20.

DETAILED DESCRIPTION OF THE INVENTION FIG. 2 shows a shift device according to the present invention. It should be understood that the shift device of FIG. 2 is part of the execution device of FIG. As already shown in FIG. 1, in the first pipe stage, the operand to be shifted is read from the data local store DLS and stored in operand registers A REG or B REG, each of length k / 2 bits. input. During the next cycle, in the second pipe stage, the data is processed in the shifter 10 and written back to the data-in register DI of the DLS. Further, FIG. 2 shows an optional parity generator 20 and an optional parity predictor 30.
These functions will be described later.

The shift structure according to the invention splits the shift into both two pipe stages 1 and 2. The data local store DLS includes data R0, R1, R2, R3, etc., each having a maximum k / 2-bit length, which can be read individually or as pairs having a k-bit length. Further, the data local store DLS includes a multiplexing device 40 that can place the data R0, R1, R2, R3, etc., in the registers A REG or B REG, respectively.

The function of the multiplexer 40 is already part of the shift function and is controlled by a command controller known in the art, not shown here. Multiplexer 40 performs a k / 2-bit shift, thus representing a k / 2-bit shift element. Therefore, the shift device 10 of the present invention
-2-4-8-16-32 -...- k only requires a 4-bit shift, thus saving one shift element and therefore one shift level for shift devices known in the art. .

If a k-bit word consisting of two k / 2 data words from the data local store DLS is shifted left (right) by a shift amount> = k / 2, during the cycle of the first pipe stage Only the right-most (left-most) k / 2 data words are in register A REG (B REG), which already represents the k / 2 shift
Must be read in. A continuous shift is then applied by the shift device 10 during the next cycle of the second pipe stage.

The shift device 10 according to the embodiment of the present invention executes the shift operation only in one direction, for example, only to the left. Operand bits are shifted in a circular fashion. If it is necessary to further manipulate the resulting data, for example leading / trailing zeros or sign extensions, it is preferred to do so with a control string described below. The shift operation in the opposite direction is performed by shifting the shift amount CS to the left.
This is done by shifting by A.

FIG. 3 shows the structure of one embodiment of the shift device 10 using the cyclic shift method. Where k = 64 and the maximum shift gate is n = 4 at each shift level. Since a shift amount k / 2 = 32 has already been implemented in pipe stage 1, only a total of 31 shift amounts are required. In the first shift level 100, a shift amount 0 in which the distance between two adjacent shift gates is k / (2n) = 8,
8, 16, 24 are possible. In the second shift level 110, the distance between each two adjacent shift gates is
The quantities 0, 2, 4, 6 where k / (2nn) = 2 are possible.
At the third and last shift level 120, only the 0 and 1 shift amounts are needed.

Therefore, another shift device 10 according to the cyclic shift scheme, where k = 128 and the maximum shift amount is n = 4 at each shift level, requires the next shift level. In the first shift level 100, shift amounts 0 and 1 where the distance between two adjacent shift amounts is k / (2n) = 16.
6, 32, 48 are possible. At the second shift level 110, the distance between two adjacent shift amounts is k / (2n
n) = 4, the quantities 0, 4, 8, 12 are possible. The third and final shift level 120 requires 0, 1, 2 and 3 shift amounts.

If k / 2b bits of data need to be shifted, the shift structure has an additional feature that a copy function in the multiplexer that allows the contents from register A REG to be copied to B REG and vice versa. You need 40. For example, insert the characters under the mask (ICM), compare the logical characters under the mask (CLM), and memorize the characters under the mask (STC
M), or duplication is required for IBM S / 390 instructions, such as the truncation function, and for every shift that applies parity prediction.

Circular shifts require some processing to receive the same result as a linear shift operation. In a preferred embodiment of the invention, such processing is performed by individual strings of bit values. The shift amount is
The shift result is decoded into a bit string that defines the significant bits and also controls the optional parity prediction. The bit string defines the validity of the data,
Arbitrarily select a parity bit for parity prediction.

Example: 64-bit shift device An example of an embodiment will be described in order to explain the present invention in detail. This embodiment includes a structure according to FIG. 2 with a 64-bit shift device. The shift device of this example can execute the following operation.

1) Shift 4 or 8 bytes left or right.
The shift is an arithmetic shift (required sign extension) or a logical shift. The shift amount is from 0 bit to 63 bits.

2) IBM S / 390 instruction, insert character under mask (IC
Byte operations such as M). Bytes from adjacent fields in storage equal to the length of the number of ones in the mask are:
Rearranged according to one position in the mask. The operand length is a maximum of 4 bytes. See also Table 4.

Example Storage operand ABC mask 1101 Result AB0C 3) IBM S / 390 instruction, store the character under the mask (STC
M): The byte from the register is selected according to the mask and stored in an adjacent byte location in the storage device. See also Table 5.

Example Register ABCD Mask 0110 Result 00BC 4) Truncate: 4-byte operands are truncated on the left or right. The truncation amount is 0 to 31.

Example Shift Structure The above function is that the shift element applies the six levels of the multiplexer, so that level 1 is left or right
This can be done by being able to perform 32 shift amounts, or by having the shift element pass data through. The additional levels perform 16, 8, 4, 2, 1 shift amounts. However, in that case, the signal needs to pass through six levels of logic to get the result.
This is very time consuming and a major drawback.

FIG. 4a shows the structure of an embodiment of the shift device 10 and the part 30a of the optional parity prediction device 30 based on the cyclic shift method. Figure 4b shows an optional parity prediction device.
2 shows the structure of one embodiment 30b of 30 and optional parity generator 20; Only the three levels of the multiplexer perform the functions in Table 1. Data is provided in the A and B registers according to Table 1. Pipe stage 1 of FIG. 2 can provide the data expected in Table 1. This is required for pipe level 2 shift devices.

Example Shift Unit 10 Shift unit 10 performs all required functions with three multiplexer levels. See FIG. 4a. Shifts with a shift amount SA> = 32 have already been reduced to shifts with amounts 0 to 31 in the first pipe stage. The three levels of the multiplexer (SU levels 1-3) are all shifts of SA0-31, plus the IBM S / 390 instructions ICM, CLM, STCM
And to perform some induction such as various microinstructions. SU level 1 performs a byte shift (8, 16, 24 to the left). These shift levels are required for all byte shifts, especially mask controlled operations such as ICM and STCM. SU level 2 is 2,
A left shift of 4 or 6 bits is performed, and a level 3 shift of 1 is performed only.

All three levels can be bypassed by activating the input STRAIGHT. The bits resulting from the shift are forced to zero by deactivating all gate signals at SU level 3. Use the AUXILIARY input to perform sign extension for arithmetic right shifts and insert a sign for arithmetic left shifts. All byte shifts are performed at shift level 1, and all shifts of quantity <= 7 are performed at levels 2 and 3. For example, IC
M / STCM requires only shift level 1. See Tables 4 and 5.

Example String Embodiment The shift amount defines the significant bits of the shift result and is decoded into a bit string that controls parity prediction.
The string defines the validity of the data and selects the parity bits for parity prediction. See Table 3.

Table 1 shows the function of the control string S. The string is 32 in width, but controls up to 64 bits of shifter result. This is because the second half of the string is either completely "0" or completely "1". Logically, this string is considered a 64-bit string. In the case of a logical shift in which the empty bit position is replaced by 0, or in the case of an arithmetic shift in which the sign bit is extended (arithmetic right shift SRA), the control string S (i)
Apply i = 0-63 to define leading zeros or define bit positions that carry the sign. Control string S
Is generated from the shift amount SA. For example, if SA = 16,
Si = 1, i = 0-47, Sj = 0, j = 48-63. The string S contains 48 ones on the left and 16 zeros on the right. As is apparent from FIG. 4, each bit position i of Si
Controls the bit position i of level 3 of the shift device.
If none of the inputs (STRAIGHT, LEFT1, AUXILIARY) are activated, the output of MUXi is zero.

For a logical left shift, the strings can be applied directly.
In the case of a logical right shift, considering the above example, the strings are swapped such that 16 zeros are on the left and 48 ones are on the right.

For arithmetic shifts where the sign is extended (arithmetic right shift SRA) or the original sign retains its position (arithmetic left shift SLA), the MUX level 3 AUXILIARY input is used to drive the sign bit. For SRA, the code is S (i)
i = 0-63 are driven to all bit positions that carry zero.

Table 1 shows the IBM S / 390 shift instruction, the applied control string S, and the A RE of the operation at pipe level 1.
Shows relevant results in G and B REGs. 2 shifts access the operand ABCD EFGH, 4 byte shift is A
Assume that you only access BCD. Here, A to H each represent a byte.

Example String Support for Parity Prediction In FIG. 4b, the parity prediction logic generally reduces significantly the amount of control logic required for parity prediction. The generated double word parity (signal + generated double word parity) is compared to the predicted double word parity. In that case, the parity bits of the original shift operand are selected according to the control string S. See Table 2. The selected parity bit produces the predicted double word parity. This predicted double-word parity is re-established by sign insertion (for arithmetic left shift) or sign extension (for arithmetic right shift), and by partially shifted out bits (signal PARITY OF PART.SHIFTED BYTE). Operated.

For a right shift, bits 7, 15, 23 and 31 of the exchanged control string define the parity bits of the original operand to be taken for parity prediction. For a left shift, control string bits 0, 8, 16, and 24 define the parity bits for prediction.

Other examples Example 1) Left shift double SLDL when shift amount SA <32
(Register pair Ri, Ri + 1, i = 8 byte operand from even) RA addresses register Ri, and RB registers Ri +
Address one. Therefore, the original operand AB
CD EFGH is input to AREG as ABCD, and input to BREG as EFGH.

Example 2) SLDL RA for SA> = 32 addresses Ri + 1 and RB addresses Ri. Thus, AREG contains EFGH and BREG contains ABCD. The cyclic shift of the 32-bit position was performed without any delay. Original operand ABCD EFGH is EFG to A / BREG
H ABCD and read.

Example 3) Right shift double SRDL when SA <32 (8 bytes) RA addresses Ri + 1 and RB addresses Ri. Thus, the original data ABCD EFGH appears as EFGH in AREG and as ABCD in BREG. This exchange is necessary when performing a right shift by performing a cyclic left shift with the complement of the shift amount. Shift 32 is pipe 1
CSA = 32−SA.

Example 4) Arithmetic shift right double SRDA for SA <32 (8 bytes) RA addresses Ri + 1 and RB addresses Ri. Thus, the original data ABCD EFGH appears as EFGH in AREG and as ABCD in BREG. This exchange is necessary when performing a right shift by performing a cyclic left shift with the complement of the shift amount. Shift 32 is pipe 1
CSA = 32−SA. Arithmetic shift requires sign extension. Every bit position in the string S that carries a zero indicates a bit position to which the sign is extended. The sign is AUXILIAR of SU level 3
Driven at the Y input.

Example 5) Arithmetic right shift SRA with SA = 19 (4 bytes) For all instructions executed by the shifter 10 applying only 4 bytes, RA and RB address the same register. Therefore, the operand is copied to AREG and BREG. Copying is also required for parity prediction. The shifted out bits of the partially shifted byte are detected only at the shifter byte 0 position. See FIG. Table 6 shows an arithmetic right shift SRA (4 bytes) operation when SA = 19 as an example.

Example 6) SRA of Example 5 for SA <32 Table 2 shows the selection of parity bits that contribute to parity prediction. The SRA in the case of SA <32 will be described as in the case of the above Example 5. Assume that the byte parity is odd.

Table 7 shows an example of arithmetic right shift SRA when SA <32.
(4 bytes) Indicates an operation. Bit position CSA (31,23) is P
Select 0 = 1 and P1 = 0, and P2, P3 and P4-P7 are 1
Is driven. Predicted double word parity PD is P0 ~
Consists of P7. Since the shift amount SA is an odd number, an odd number of sign bits are extended. Furthermore, for the last predicted parity, it is necessary to consider the parity of the partially shifted bytes.

Continued on the front page (72) Inventor Pffeffe, Erwin Holzgarlingen, Germany, Techstutras 12 (72) Inventor Gertner, Oute Germany, Schöneich, Walden Becker Strasse 30/1 (72) Inventors Geavig, Gunter Germany Simotzheim, Im Schrebuch 9 (58) Fields studied (Int.Cl. ⁶ , DB name) G06F 5 / 01,7 / 00

Claims (17)

(57) [Claims] A plurality of operand registers (A REG, BR
EG) and a data store (DLS) containing data (R0-R3) that can be read individually or in combination, and a shift device (AREG, BREG) coupled to the outputs of the operand registers (AREG, BREG). 10) and coupled to the output of the data store (DLS) to read the data to be shifted (R0-R3) into a plurality of operands.
A shift structure for performing a shift operation, characterized by a multiplexing device (40) for performing at least one shift operation when required by placing it in a register (A REG, B REG). 2. The method according to claim 1, wherein the shift operation is performed in two consecutive pipe stages, provided that the data store (DLS) and the multiplexer (40) are in the first stage of the pipe stage and the shift device (10). Shift structure according to claim 1, characterized in that is in the second stage of the pipe stage. 3. The data store (DLS) has a maximum of k / 2
Including data (R0 to R3) having a bit length, data (R0
R3) can be read individually or as pairs having a maximum length of k bits into a pair of operand registers (A REG, B REG) each having a length of k / 2 bits, a shift device having a length of k bits (10) is the operand
The multiplexer (40) is coupled to a pair of registers (A REG, B REG) and includes a plurality of shift elements, and the multiplexer (40) stores the k / 2-bit data (R0-R3) to be shifted in each of the operand registers (R0-R3). A REG, B
REG) to perform a k / 2-bit shift when necessary, wherein the shift device (10) requires only a shift element having a maximum shift amount of k / 4. The shift structure according to claim 1, wherein 4. The device according to claim 1, wherein the multiplexing device includes a copying device for copying the contents of the operand registers. Shift structure. 5. The method according to claim 1, wherein n and p have different shift amounts.
, P, q, etc., and the amount of shift represents an integer, and at the first shift level, the shift gates are: Shift amounts in which the distance between two adjacent shift amounts is k / (2n): 0, k / (2n), 2 * k / (2n), 3 * k / (2
n), 4 * k / (2n), ..., (n-2) * k / (2n), (n
-1) * k / (2n), at each successive shift level the distance between two adjacent shift amounts is divided into k / (2II), where II is the previous shift level up to now Shift device having a k-bit length, which can be used in the shift structure according to any one of claims 1 to 4 and performs a shift operation in one direction only in a cyclic manner (Ten). 6. The shift device according to claim 5, wherein the last shift level ends with a shift amount of one.
0). 7. A string comprising individual bit values or byte values, wherein the cyclic shift result is corrected to a linear shift result, whereby the amount of shift to be shifted is decoded into a string defining the significant bits of the shift result. Shifting device (10) according to claim 5 or 6, characterized in that the shifting is performed. 8. A shift device (10) according to any one of claims 5 to 7, characterized in that it comprises a parity prediction device (30). 9. A shift as claimed in claim 8, wherein the counting of the bits shifted out of the partially shifted bytes is effected only on one side in the parity estimator (30). Equipment (10). 10. In the parity predictor (30), the counting of bits shifted out of the partially shifted bytes is achieved only on the side shifting the bits in a cyclic manner. The shift device (1) according to claim 9,
0). 11. The apparatus according to claim 10, wherein the string is a parity prediction device.
Shift device (10) according to one of the claims 8 to 10, characterized in that the parity prediction can be controlled by selecting the parity bits for the parity prediction within. 12. An execution device for performing data operations in a processor device, characterized in that it comprises a shift structure or a shift device (10) according to any one of the preceding claims. 13. A processor chip, characterized by a shift structure or a shift device (10) or an execution device according to any one of the preceding claims. 14. Reading an operand to be shifted from a data store (DLS), and inputting the operand by a multiplexer (40) into a plurality of operand registers (A REG, B REG), thereby requiring Performing at least one partial shift if necessary, and shifting the operand by performing the remaining partial shifts by the shift device (10). Reading the operand to be shifted and inputting the operand into a plurality of operand registers in a first pipe stage during a first cycle; 15. The method of claim 14, wherein shifting the operand by performing a remaining partial shift is performed in a second pipe stage during a next cycle. 16. Operands to be shifted each have a length.
Input to one of a pair of k / 2-bit operand registers, where k represents an integer, so that
16. The method according to claim 14, wherein a k / 2-bit shift is performed, and the shifting of the operands is performed by successively shifting the remaining partial shifts in a shift device of length k bits. The described method. 17. To shift left / right by a shift amount> = k / 2, only the rightmost / leftmost k / 2 data words are placed in the leftmost / right register of the operand register pair. 17. The method of claim 16, wherein the reading represents a k / 2 shift during a cycle in the first pipe stage.