JPH10326187A - Digital signal processor and integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the total operation speed of a digital signal processor by generating codes from one instruction code in an instruction ROM and controlling internal circuits with those instruction codes. SOLUTION: A ROM address counter 1 specifies an address of the instruction ROM 2 and an instruction code stored in the instruction ROM 2 is outputted from the specified address to a ROM data converter 3. The ROM data converter 3 processes part or the whole of the instruction code by bit inversion, etc., to convert the instruction code into more than one codes. For the block of those codes, the control signal by the ROM data converter 3 is outputted under the control of a system controller 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor (DSP) for performing internal control by an instruction (instruction) code or an integrated circuit (particularly, an LSI) including a microcomputer for similarly performing internal control by an instruction code. ).

[0002]

2. Description of the Related Art In a conventional digital signal processor in which internal control is performed by an instruction code,
One operation is performed by one instruction code. For details of the digital signal processor according to the related art,
This will be described in (Embodiment 1) of the “Embodiment of the Invention”.

[0003]

In order to increase the operating speed of a digital signal processor, it is necessary to increase the operating speed of a built-in instruction ROM itself. Basically, to increase the operating speed of LSI,
In general, it is necessary to increase the voltage so that a large amount of current flows, and for this purpose, it is necessary to reduce the resistance value of the pattern, which is the path of the current. As a countermeasure for easily realizing this, it is usual to widen the pattern, and in that case, the area of the LSI chip constituting the instruction ROM necessarily becomes large. This leads to an increase in power consumption. In addition, the operation speed of the instruction ROM is only one tenth of the operation speed of the gate inside the LSI, and it is not easy to increase the operation speed.

The present invention has been made in view of such circumstances, and has been developed as a digital signal processor or an integrated circuit itself without being restricted to the improvement of the operation speed of an instruction ROM accompanied by manufacturing difficulties. It is intended to substantially improve the overall operation speed of the.

[0005]

According to the digital signal processor of the present invention, a plurality of instruction codes output from an instruction ROM are processed by a method such as bit inversion of a part or all of the instruction codes. And a plurality of internal circuits are controlled by these instruction codes.Without being bound by the difficulty of increasing the operation speed of the instruction ROM, the overall digital signal processor itself is constructed. The operating speed can be substantially improved. In particular, when controlling using an N-ary counter, the apparent speed can be increased by N times.

[0006] Further, by providing a control code for determining whether or not to invert bits, or providing a control code for determining the validity of a count value of an N-ary count, the above-mentioned only for a necessary portion is provided. Processing can be performed to prevent an unnecessary increase in power consumption due to an increase in operation speed.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of a digital signal processor according to the present invention will be described in detail with reference to the drawings.

[General Structure of Digital Signal Processor] FIG. 1 is a block diagram showing the structure of a main part of a digital signal processor. In FIG. 1, reference numeral 1 denotes a ROM for designating an address of an instruction ROM 2.
An address counter 2, an instruction ROM (built-in ROM) in which instruction (instruction) codes are stored, a ROM data converter 3 for converting an instruction code output from the instruction ROM 2 according to the method of the present invention, and a reference numeral 5 A system controller for outputting a control signal from the ROM data converter 3 to the blocks from 1 to 16; 5, a temporary register for temporarily waiting data; 6, a table ROM (built-in) for storing constants used for calculations and the like. R
OM), 7 is a RAM for storing data (built-in RAM), 8
Is a multiplier (multiplier), 9 is an ALU (logical operation unit) that performs addition / subtraction / logical operation, etc., 10 (ACC
0) and 11 (ACC1) are first and second save registers (accumulators) for saving the output from the ALU 9;
12 is a data bus to which data such as calculation results are transferred,
13 is a first count register (0) for conditional jump
When the value is set, the judgment condition (JC0 or JNC
Each time (0) is executed, the countdown is performed by one.
Reference numeral 14 denotes a second count register (1) for a conditional jump. When a value is set, the count is decremented by one each time a judgment condition (JC1 or JNC1) is executed. 15 is a RAM for addressing the RAM 7
In the address counter, increment bit "Ra co"
Is set to "1", the count is incremented by one, and the value of the counter is output as an address of the RAM 7. Reference numeral 16 denotes a ROM address counter for specifying an address for the table ROM 6. When an increment bit "Ro co" is set to "1", the ROM address counter 16 counts up by one and outputs the value of the counter as an address of the table ROM 6.

(Description of Prior Art) FIG. 2A shows a structure of a conversion code for calling an instruction code stored in an instruction ROM 2 based on an assembler, and FIG. 2B shows a structure of the conversion code. The specific contents of each component are shown. The one shown in FIG. 2 relates to the prior art. The instruction code has a configuration of 15 bits from 0 to 14.

The "multiplication" on the 14th bit in FIG. 2A is for the multiplier 8 in FIG. 1, and as shown in FIG. 2B, inactive: does not operate. Perform multiplication.

"Control" consisting of 3 bits of bits 11 to 13 in FIG. 2A controls the entire digital signal processor. As shown in FIG. 2B, NOP: No operation is performed. JMP: Change the address of the instruction ROM 2 to the address of the value specified in the “Address” column CALL: Change the address of the instruction ROM 2 to the address of the value specified in the “Address” column RTN: CALL is executed MVI: Change the value specified in the “Immediate” column to “DBU”
MOV: Transfer from the circuit indicated by “DBUS src” to the circuit indicated by “DBUS src”
ALU: Transfers a value to the circuit indicated by "S dst" through the data bus 12. ALU: Performs the operation indicated by "Alu OP".

In the case of “JMP Condition” in FIG. 2A, 8 bits 0 to 7 indicate “Address”, and “DBU”
In the case of “S dst”, the 8 bits 0 to 7 are “Immediate”
(Immediate value).

The "JMP Condition" consisting of the 3rd 8th to 10th bits in FIG. 2A performs the following processing as shown in FIG. 2B.

C0: first count register (0) 13
When the count value of the instruction ROM becomes "00h"("h" is hexadecimal (hexadecimal)), the address of the instruction ROM 2 is changed to the address of the value specified in the "Address" column. NC0: First count register (0) If the count value of the counter 13 is not "00h", the address of the instruction ROM 2 is changed to the address of the value specified in the "Address" column. C1: The count value of the second count register (1) 14 is "00h". When the value becomes, the address of the instruction ROM 2 is changed to the address of the value specified in the “Address” column. NC1: If the count value of the second count register 14 (1) is not “00h”, the address of the “Address” column is displayed. Changes the address of the instruction ROM 2 to the address of the specified value. S: Supports the value of the calculation result of ALU9. When the inflag becomes "1", the address of the instruction ROM 2 is changed to the address of the value specified in the "Address" column. NS: The sign flag of the value of the calculation result of the ALU 9 is "1".
If not, the address of the instruction ROM 2 is changed to the address of the value specified in the “Address” column. Z: When the value of the calculation result of the ALU 9 becomes “0”, “Add”
The address of the instruction ROM 2 is changed to the address of the value specified in the “ress” column. If the value of the calculation result of NZ: ALU9 is not “0”,
The address of the instruction ROM 2 is changed to the address of the value specified in the “Address” column.

"DBUS dst" consisting of the 3rd 8th to 10th bits in FIG. 2A indicates the output destination of the data bus 12 in FIG. 1, and as shown in FIG. 2B, NIL: no destination RAM: Output to RAM7 ALU: Output to Alu Bin CNT0: Output to first count register (0) 13 CNT1: Output to second count register (1) 14 TREG: Output to temporary register 5 RAMA : Output to the RAM address counter 15 ROMA: Output to the ROM address counter 16

"DBUS src" consisting of 3 bits of the second to fourth bits in FIG. 2A indicates an output source of the data bus 12 in FIG. 1, and as shown in FIG. 2B, NIL: output source None RAM: Output from RAM 7 ROM: Output from table ROM 6 ACC0: Output from first save register (ACC0) 10 ACC1: Output from second save register (ACC1) 11 TREG: Output from temporary register 5 It has become.

The first bit "RAMA cou" of FIG.
nt "(" Ra co ") is the RAM address counter 1 in FIG.
As shown in FIG. 2B, NOP is not counted up, and UP is incremented by +1.

The "ROMA coupe" of the 0th bit in FIG.
nt "(" Ro co ") is the ROM address counter 1 in FIG.
As shown in FIG. 2B, NOP is not counted up, and UP is incremented by +1.

"Alu OP" consisting of the 3rd 8th to 10th bits in FIG. 2A is a code for the ALU 9 in FIG. 1, and is defined as shown in FIG. 2B. .

NOP: Do nothing EOR: Output exclusive OR of input signals specified by Alu Ain and Alu Bin OR: Output logical sum of input signals specified by Alu Ain and Alu Bin AND: Alu Outputs the logical product of the input signals specified by Ain and Alu Bin ADD: Outputs the addition of the input signals specified by Alu Ain and Alu Bin SBA: Ain-Bin for the input signals specified by Alu Ain and Alu Bin SBB: Output Bin-Ain for the input signal specified by Alu Ain and Alu Bin CLR: ALL0 (all zero) regardless of the input
"Alu" consisting of 2 bits of the 6th to 7th bits in FIG.
"out" indicates an output destination from the ALU 9, and as shown in FIG. 2B, ACC0: output to the first save register (ACC0) 10 ACC1: output to the second save register (ACC1) 11 Has become.

2A, "Alu Ain", which consists of the fourth and fifth bits, indicates the input source to Ain of ALU 9, and as shown in FIG. 2B, ACC0: first save. Input from the register (ACC0) 10 P: Input from the multiplier 8

In FIG. 2A, "Alu Bin" consisting of two bits, the second and third bits, indicates the input source to Bin of ALU9. ACC1: Input from second save register (ACC1) 11 DBUS: Data Input from the bus 12.

The instruction code is a code obtained by converting the assembler shown in FIG. 3 by the conversion code shown in FIG. Hereinafter, description will be made based on the assembler of FIG. FIG. 3 shows a source program written in an assembler language. The processing content of the source program is to multiply the data at address 0 in the RAM 7 by the data at address 0 in the table ROM 6, and to multiply the result by the second save register (ACC 1) 11. And the result of multiplying the data at address 0 of the RAM 7 by the data at address 1 of the table ROM 6 is the second result.
Is subtracted from the save register (ACC1) 11 and such processing is performed until the address of the table ROM 6 becomes address 15. Further, the above processing is performed by setting the address of the RAM 7 to 1
It is repeatedly executed until the address becomes 5.

"STT:" and "A" shown in FIG.
A: ”and“ END: ”are comments, which usually correspond to the address (here, the line number) when assembling. In the case of FIG. 3,“ STT: ”indicates the first line,
“AA:” indicates the sixth line, and “END:” indicates the thirteenth line.

Here, as a preparation for the description, the first line in FIG. 3 will be described. The first line in FIG. 3 is STT: CL
R (A0), and in this case, “CL
Search for the code “R” and select “CL” from the “Alu OP” column.
It is found that the code of "R" is "111", and since this code was in the column of "Alu OP", ALU9
It turns out that the code is "Contro
“l” becomes “110” of “ALU.” Next, “A0”
Finds that “A0” is a short form of “ACC0” and “CL0”
Since "R" is a code related to the output of ALU9, "A"
From the column of “lu out”, it can be seen that the code of “ACC0” is “00.” In this case, since there is no other code notation, the instruction code in this case is
As shown in FIG.

FIG. 5 shows an instruction code when the program of FIG. 3 is converted according to the conversion code of FIG. 2 by the conventional method. The numbers correspond to the numbers in FIG. FIG. 6 shows a state in which the assembler code of FIG. 3 is compared with the instruction code of FIG.

Hereinafter, the processing of the program shown in FIG. 3 according to the conventional method will be described step by step.

First, the instruction ROM 2 outputs an instruction code corresponding to the first line of the assembler code. ALU 9 is designated by the ALU instruction (“110”) of “Control”, and “Alu O
“Alu out” is “0” in the CLR instruction (“111”) of “P”.
"Alu Ain" is also set to "00", "Alu Bin" is also set to "00", and "RA
MA count ”(“ Raco ”) is set to“ 0 ”,
“ROMA count” (“Ro co”) is also set to “0”. As a result, as described above, the first save register (ACC0) 10 is cleared to “00” by the ALU 9 as described above.

Next, the second line is executed, and the MVI instruction of “Control” (“100”) is used to set “0” as “Address” with the RAMA instruction (“110”) of “DBUS dst”.
00000000 "is set, and the RAM address counter 15 (" RAA ") is cleared to" 0 ".

Next, the third line is executed, and the MVI instruction (“100”) of “Control” is used to set “0” as “Address” by the ROMA instruction (“111”) of “DBUS dst”.
00000000 "is set, and the ROM address counter 16 (" ROA ") is cleared to" 0 ".

Next, the fourth line is executed, and the CNT0 of “DBUS dst” is executed by the MVI instruction (“100”).
("011"), the first count register (0) 13 stores "0fh"("h" is hexadecimal (hexadecimal)).
“0fh” is “000011111” in binary notation, “15” in decimal notation) is stored, and the 14th multiplication bit (MULT) is set to “1”.

Next, the fifth line is executed, and the CNT1 of “DBUS dst” is executed by the MVI instruction (“100”).
At ("100"), "0fh"("00001111" in binary notation) is stored in the second count register (1) 14, and the multiplication bit (MULT) is set to "1".

Next, the sixth line is executed, and the ALU 9 is designated by the ALU instruction ("110") of "Control".
“Alu ou” by the ADD instruction (“100”) of “Alu OP”
t ”, the second save register (ACC1) 11 (“ 0
1)), and the multiplier 8 (“0”) as “AluAin”.
1)), the second save register (ACC1) 11 (“00”) is specified as “Alu Bin”, and “R
The count-up is not designated as “AMA count” (“Ra co”) (“0”), and “ROMA count”
("Ro co") designates a count-up ("1"), and the multiplication bit (MULT) remains set to "1". That is, the contents of the second save register (ACC1) 11 and the multiplication result of the multiplier 8 are added, and the addition result is again stored in the second save register (AC1).
C1), and the ROM address counter 16 counts up by +1.

Next, the seventh line is executed, and the ALU 9 is specified by the ALU instruction (“110”) of “Control”.
Similarly to the above, the second save register (ACC) is set as “Alu out” by the SBA instruction (“101”) of “Alu OP”.
1) 11 (“01”) is designated, the multiplier 8 (“01”) is designated as “Alu Ain”, and the second save register (ACC1) 11 (“00”) is designated as “Alu Bin”.
Is designated, the count-up is not designated as “RAMA count” (“Ra co”) (“0”), and “ROA
The count-up is designated as “MA count” (“Ro co”) (“1”), and the multiplication bit (MULT) remains set to “1”.
Is subtracted from the output of the second save register (ACC1) 11, the result of the subtraction is output again to the second save register (ACC1) 11, and the ROM address counter 16 is incremented by one.

Next, the eighth line is executed, and "JMPCondition" is designated by a JNC0 instruction (this is a display of both JMP and NC0), that is, a JMP instruction ("001") of "Control". First count register (0) 1 by NC0 instruction (“001”)
It is determined whether the value of 3 is “00h”,
If it is not "0", "Address" for the ROM address counter 16 is set to "00000110"("6" in decimal notation) for the ROM address counter 16 according to the address indicated by "AA" (in this case, the sixth line), and the first count is performed. Register (0) 1
The count value of 3 is subtracted by -1.

Next, since the address of the ROM address counter 16 is set to "6", the sixth line is executed again. The work from the sixth line to the eighth line is performed when the value of the first count register (0) 13 is changed from “0fh” to “00h”.
, Ie, 16 times, and when the value of the first count register (0) 13 becomes “00h”,
Next, go to line 9.

The ninth line is executed, and the MOV of “Control” is
In the instruction (“101”), the RAM 7 is specified by the RAMA instruction (“110”) as the transfer destination of “DBUS dst”, and the first save register (“011”) is specified by the ACC0 instruction (“011”) as the transfer source of “DBUS src”. ACC0)
10 is designated, count-up ("1") is designated as "RAMA count"("Raco"), and "ROM
A count ”(“ Ro co ”) is not designated to count up (“ 0 ”), and the multiplication bit (MUL)
T) is reset to "0". That is, the value of the first save register (ACC0) 10 is output to the RAM 7,
The address of the RAM address counter 15 is incremented by +1.

Next, the tenth line is executed, and "Control" is executed.
"DBUS dst" by the MVI instruction ("101")
In the "ROMA instruction (" 111 ")," 00000000 "is set as" Address ", and the ROM address counter 16 (" ROA ") is cleared to" 0 ".

Next, the eleventh line is executed, and "Control" is executed.
ALU 9 (“110”) designates ALU 9, and “Alu OP” CLR instruction (“111”) stores the first save register (ACC 0) 10 in the same manner as in the case of the first row. The value is cleared to "00".

Next, the twelfth line is executed, and "JMP Condition" is specified by the JNC1 instruction (this is a display of JMP and NC1 together), that is, the JMP instruction ("001") of "Control". The NC1 instruction (“011”) causes the second count register (1) 1
It is determined whether the value of 4 is “00h”,
If not "00h", "Address" for the ROM address counter 16 is set to "00000110"("6" in decimal notation) for the ROM address counter 16 at the address indicated by "AA" (in this case, the sixth line), and the second count is performed. Register (1)
The count value of 14 is subtracted by -1.

Next, since the address of the ROM address counter 16 is set to "6", the sixth line is executed again. The work from the sixth line to the twelfth line is performed when the value of the second count register (1) 14 is changed from “0fh” to “00”.
h ”, that is, 16 times, and when the value of the second count register (1) 14 becomes“ 00h ”, the next thirteenth line is executed, and the processing of this program ends.

The above is the description of the operation in the conventional system.

When this program is executed by the conventional method, the first line to the fifth line are executed once, and the first count register (0) 13 is set to “0” from the sixth line to the eighth line.
fh "to" 00h "is repeated 16 times, and the fourth row from the ninth row to the twelfth row is added to the 16 repetitions from the sixth row to the eighth row. (1) It is repeatedly executed 16 times until 14 changes from “0fh” to “00h”.
The total number of times of execution is 5 + [{(3 × 16) +4} × 16] = 837 (1), that is, 837 times in total. Here, “times” corresponds to the number of system clocks.

(Embodiment 1) Next, an essential part of the digital signal processor according to Embodiment 1 of the present invention will be described. The first embodiment of the present invention is configured to have a function of controlling a plurality of circuits with one code by inverting a part or all of the instruction code.

For example, "ADD" in the sixth row in FIG.
Is given the meaning of “SBA” and the other inverted code is “NOP” (No operation is performed), the assembler of FIG. 3 is regarded as shown in FIG.

The instruction code is "Alu O
Only bits containing P "(10 bits from the 8th bit in FIG. 2)
Bits are inverted for each row. Then
The instruction code is as shown in FIG. 8, in which “ADD” = “10” of the 8th to 10th bits of “Alu OP”, which is the bit position of “Alu Bin”.
0 is left as it is, and “SBA” = “101” (FIG. 2
(See (b) and FIG. 6) to make “SBA” = “011” of the inverted bit of “ADD” = “100”, the original “AND” = “011” and the original “SBA” = “101” "
A code table shown in "Alu OP" in FIG. 9 in which "Alu OP" in FIG. FIG. 9A shows the instruction RO shown in FIG.
FIG. 9 shows the structure of a conversion code for calling the instruction code stored in M2 based on the assembler, and FIG. 9B shows the specific contents of each component of the conversion code. The structure of FIG. 9A is exactly the same as the structure of FIG. This conversion process is executed by the ROM data converter 3 of FIG.

FIG. 9 (b) differs from FIG. 2 (b) only in "Alu OP" corresponding to the 8th to 10th bits. That is, in “Alu OP”, “SB
“A” is “SBA” = “011” which is replaced with “AND” = “011” in FIG. 2B, and this “SBA”
= “011” is an inverted bit of “ADD” = “100”. That is, for all bits, the bit “0” is inverted to “1” and the bit “1” is inverted to “0”.

If the code of "Control" before bit inversion is other than "ALU", the code of "Control" is set to "0".
The circuit is configured to be "00".

FIG. 8 shows the instruction code.
Is the same as the first line in FIG. The second line in FIG. 8 is “Alu OP” corresponding to the 8th to 10th bits in the first line.
Of "111" is inverted to "000". The third line in FIG. 8 is the same as the second line in FIG. FIG.
In the fourth row, “110” of “Alu OP” in the third row is bit-inverted to “001”. The fifth line in FIG. 8 is the same as the third line in FIG. In the sixth row of FIG. 8, "111" of "Alu OP" in the fifth row is bit-inverted to "0".
The seventh line in FIG. 8 is the same as the fourth line in FIG. 6. The eighth line in FIG.
The bit inversion of “011” of “P” is changed to “100.” The ninth row in FIG. 8 is the same as the fifth row in FIG.
The 10th line in FIG. 8 is “10” of “Alu OP” in the 9th line.
"0" is bit-inverted to "011".

Further, the eleventh line in FIG. 8 is the same as the sixth line in FIG. The twelfth line in FIG. 8 is “Alu O
The bit “100” of “P” is inverted to “011.” The instruction code on line 11 is “A”.
DD ”, and the instruction code on the twelfth line obtained by bit-inverting the“ Alu OP ”portion of the instruction code on the eleventh line is“ S
BA ". This point is a feature of the first embodiment.

The 13th line in FIG. 8 is the same as the 8th line in FIG. The 14th line in FIG. 8 is obtained by inverting “001” of “Alu OP” in the 13th line to “110”. Here, it should be noted that the seventh line in FIG. 6 has been skipped.

The 15th line in FIG. 8 is the same as the 9th line in FIG. The 16th line in FIG. 8 is obtained by inverting “110” of “Alu OP” in the 15th line into “001”. The 17th line in FIG. 8 is the same as the 10th line in FIG. The 18th line in FIG. 8 corresponds to “11” of “Alu OP” on the 17th line.
8 is the same as the eleventh row in FIG.
On the 0th line, “111” of “Alu OP” on the 19th line is bit-inverted to “000”. 8 in FIG.
The row is the same as the twelfth row in FIG. The 22nd line in FIG. 8 is obtained by inverting “011” of “AluOP” in the 21st line to “100”. The last line 23 in FIG. 8 is the same as line 13 in FIG.

The right side of FIG. 8 shows an assembler code obtained by performing an inverse conversion from the instruction code shown on the left side. This is because if the "Control" code is set to "000" when the bit inversion is other than "ALU", "000" of the "Control" code corresponds to "NOP" in the assembler code, and the other bits are set. No matter what, the system does nothing. However, if it is any other code,
Since the operation according to the l "code is performed, the assembler of FIG. 3 is equivalent to that shown in FIG.

7 and 8, there is no "NOP" between "ADD" and "SBA", and "SB"
It should be noted that there is no "NOP" between "A" and "JNC0".

When the program of FIG. 7 is executed with a clock which is twice as fast as that of the conventional method, the first line is
Rows 0 to 1 are executed once each, rows 11 to 14 are repeatedly executed 16 times until the first count register (0) 13 changes from “0fh” to “00h”. 8 rows from the 15th row to the 22nd row are added to the 16 repetitions of the 14th row, and 1 is added until the second count register (1) 14 changes from “0fh” to “00h”.
This will be repeated six times. Therefore, the number of executions is 10 + [{(4 × 16) +8} × 16] = 1162 as a whole, which is 1162 times in total.

However, this is the number of executions when a clock whose speed is twice as high is used. When comparing this with the conventional method, the number of executions can be reduced by half. 1162 ÷ 2 = 581… （… （（（３ （（３ ３ ３ ３ ３ ３ ３ ３ ３ ３ ３ ３ ３ ３ ３ ３ (3) Compared with the conventional method, (837-581) ÷ 837 = 0.306 ... (4), and can be executed in about 30% less times.

As described above, by inverting the bits of the instruction code, a plurality of codes can be generated by one code and a plurality of circuits can be controlled. Thereby, the substantial operation speed of the digital signal processor can be improved without increasing the operation speed of the instruction ROM 2. Further, the bit inversion of the instruction code can be realized by simple means.

However, in order to execute a plurality of codes as described above, a clock that is a multiple of the clock for operating the instruction ROM 2 is required. That is, in the above case, the number of times shown in Expression (2) is the actual clock. The power consumption of the LSI tends to increase as the number of clocks increases, and becomes 1162 ÷ 837 = 1.388... (5). , A new problem that the power consumption is increased about 1.3 times as compared with the above.

(Embodiment 2) The digital signal processor according to Embodiment 2 attempts to reduce power consumption by providing a control code for controlling whether or not the instruction code is bit-inverted. is there.

More specifically, when the inverted code is "NOP", a bit for preventing the generation of a clock is added to reduce the number of times of execution when the clock is doubled. Thus, power consumption is reduced.

FIG. 10 is a block diagram showing the configuration of the ROM data converter 3 for reducing the number of executions, and FIG. 11 is a diagram showing its timing.

The instruction code output from the instruction ROM 2 is divided into an instruction code I and a control code A, and the ROM data converter 3
The instruction code I is input to the Q input of the data selector 3a and the ROM data inverter 3b. The ROM data inverter 3b inverts only the bit portion of "Alu OP" corresponding to the 8th to 10th bits of the instruction code I, and inputs it to the Q 'input of the data selector 3a. The double clock is input to the 1/2 frequency divider 3c, and the 1/2 frequency output B from the 1/2 frequency divider 3c is input to the select input of the data selector 3a and the OR gate 3d. When the 1/2 frequency divider output B of the 1/2 frequency divider 3c connected to the select input is "1", the data selector 3a outputs the Q input as an instruction.
When the frequency division output B is "0", the Q 'input is output as an instruction.

The control code A from the instruction ROM 2 and the 1/2 frequency divider output B from the 1/2 frequency divider 3c are input to the OR gate 3d, and the output of the OR gate 3d is A
Input to ND gate 3e. The double clock is A
Input to ND gate 3e. When at least one of the 1/2 frequency divided output B and the control code A is "1", the output of the OR gate 3d becomes "H" and the double clock is output from the AND gate 3e as the gate output C, that is, the system clock. Is done. The digital signal processor is operated by this system clock.

The “bit for controlling whether or not the instruction code is bit-inverted” in the claims refers to the control code A. Normally, control code A is "0"
Therefore, the gate output C having the same cycle as the 1/2 frequency-divided output B in FIG. 11 is output. However, when the control code A is "1", the double clock is output as the gate output C as it is. The instruction code (illustrated in the form of an assembler code, for example, the sixth line) of FIG. 3 shown in the upper part of FIG. 11 is obtained from the instruction ROM 2 on the eleventh and twelfth lines in FIG.
The instruction code on the seventh line in FIG. 3 becomes the ROM output directly input from the instruction ROM 2 on the thirteenth and fourteenth lines to the data selector 3a in FIG. The instruction code on the eighth line is 1 in FIG.
The ROM output directly input to the data selector 3a from the instruction ROMs 2 in the fifth and sixteenth rows is obtained. The instruction code in the ninth row in FIG.
In the RO on the 17th and 18th lines
ROM directly input from M2 to data selector 3a
Output.

In the instruction codes output from the instruction ROM 2 in the eleventh to eighteenth rows, only the bit portion of “Alu OP” corresponding to the eighth to tenth bits, which is input to the ROM data inverter 3b and inverted. Instruction code is stored in ROM
The inverted output is input to the data selector 3a. That is, the instruction codes on lines 11 and 12 [AA: ADD (A1,...) In assembler code format]
Is the inverted instruction code in the ROM data inverter 3b [SBA (A1,
..], And the instruction codes on lines 13 and 14 [SBA (A1,...) In assembler code format become inverted instruction codes [NOP in assembler code format] in ROM data inverter 3b.
The instruction codes (JNC0... In assembler code format) on the fifth and sixteenth lines are stored in the ROM data inverter 3
b, an inverted instruction code (NOP in assembler code format) is obtained, and the instruction code on lines 17 and 18 [MV in assembler code format]
I (RA,...) Are inverted instruction codes [N in assembler code format] in the ROM data inverter 3b.
OP].

Then, the 1/2 frequency divided output B input to the select input of the data selector 3a has a double clock of 1
The frequency is halved by the 分 frequency divider 3c, and is a one-time clock. The ROM output from the data selector 3a is output as a ROM data conversion output (instruction output) during the "H" period of the 1/2 frequency divided output B,
During the “L” period of the 1/2 frequency-divided output B, the data selector 3a
Outputs a ROM inverted output as a ROM data conversion output (instruction output). As a result,
As the ROM data conversion output (instruction output), the instruction code [AA: A
DD (A1,...), The instruction code [SBA (A1,...)] Is output on the twelfth line, and the instruction code [JNC0.
The fourth line outputs the instruction code [NOP], and the fifteenth line outputs the instruction code [MOV (R
A,...], An instruction code [NOP] is output on line 16, an instruction code [MVI (ROA,...)] Is output on line 17, and an instruction code [NOP] is output on line 18. Will be.

However, the system clock, which is the gate output C generated by the logical sum of the control code A and the 分 -divided output B in the AND gate 3e, is not used for the instructions on the 14th, 16th, and 18th lines. Since the code [NOP] is not output, it is considered that the assembler of FIG. 7 is substantially like the assembler of FIG.

When this is considered on the basis of the 1/2 frequency dividing output B, when the control code A is "1", the operation is performed at twice the speed. 1 of circumferential output B
Since it is executed in a cycle, it looks like one line. The seventh line, the eighth line, the ninth line, and the tenth line are each one line because the system clock as the gate output C has the same cycle as the 1/2 frequency-divided output B. In this case, the number of executions may be considered as six, seven, and eight lines substantially as two lines, and by replacing “3” in Expression (1) with “2”, 5 + [{(2 × 16) +4} × 16] = 581 (6), which is the same value as the equation (3) in the case of the first embodiment, and is about 30% smaller than the conventional method. I can do it. Moreover, since the actual number of clocks is reduced by about 30% compared to the first embodiment, the power consumption can be reduced by about 30%.

In the first and second embodiments, another embodiment in which the entire instruction code is bit-inverted is also conceivable.

(Embodiment 3) A digital signal processor according to Embodiment 3 of the present invention further improves the apparent operation speed.

FIG. 12A shows an instruction RO.
FIG. 12 shows the structure of a conversion code for calling the instruction code stored in M2 based on the assembler, and FIG. 12B shows the specific contents of each component of the conversion code. FIG. 12 (b) is the same as FIG. 2 (b).

The instruction code shown in FIG. 12A is divided into four sections, and a 2-bit quaternary counter for preparing 2 ² = 4 count values 0 to 3 is prepared for each section ( For the 2-bit quaternary counter, see the quaternary counter 21 in FIG. 15 described later).
The counts 0 to 3 indicate instructions to be executed when the count values of the quaternary counter reach 0, 1, 2, and 3, respectively. For example, when the count value is 0, the instruction of the count 0 is executed. The part of the count 0 is control related to the ALU9, and “multiplication” is assigned to the 39th bit.
“Alu OP” is assigned to the eighth bit, and 34 to 3
“Alu out” is assigned to the fifth bit, and
“Alu Ain” is assigned to the bit, and 30 to 31
“Alu Bin” is assigned to the bit. The part of the count 1 is the control related to the transfer relationship,
“DBUS dst” is assigned to the ninth bit, and
"DBUS src" is assigned to the 26th bit, and 23
“RAMA count” (“Ra co”) is assigned to the bit, and “ROMA count” (“Ro c”) is assigned to the 22nd bit.
o ”) is assigned. The part of the count 2 is control relating to transfer of immediate data (immediate value).
“DBUS dst” is assigned to the 19th to 21st bits, and “Immediate” of 8 bits is assigned to the 11th to 18th bits. The part of the count 3 is the control related to the jump instruction.
“ndition” is assigned, and 8-bit “Address” is assigned to the 0th to 7th bits.

When the conversion code of FIG. 12 is used, the source program in the assembler language of FIG. 3 is as shown in FIG. 13, and the operation which took a plurality of lines in FIG. 3 can be combined into one line. For example, the first and second lines in FIG. 3 are STT: CLR (A0) MVI (RAA, 0), but the first line is the ALU code, and the second line is the transfer code. Therefore, as shown in the first row of FIG. 13, STT: CLR (A0) | NOP | MVI (RAA,
0) | NOP and one line.

The MVI (ROA, 0) on the third line in FIG.
As shown in the second row of FIG. 13, | NOP | NOP | MVI (ROA, 0) | NOP | N
OP and MVI (CNT0, 0fh) M in the fourth row in FIG.
ULT is, as shown in the third row of FIG. 13, | MULT | NOP | MVI (CNT0, 0fh) | N
OP and the MVI (CNT1, 0fh) M in the fifth row of FIG.
ULT is, as shown in the fourth row of FIG. 13, | MULT | NOP | MVI (CNT1, 0fh) | N
It becomes OP. Then, AA: ADD (A1, A1,
A1, P) MULT INC (RO) is represented by AA: ADD (A1, A1, P) MULT | INC (R
O) | NOP | NOP, and the SBA in the seventh row of FIG.
(A1, A1, P) MULT INC (RO) and 8
The JNC0 AA in the row is grouped into one row as in the sixth row in FIG. 13, and SBA (A1, A1, P) MULT | INC (RO) |
NOP | JNC0 AA, and MOV (RA, A0) INC on the ninth row in FIG.
(RA) is expressed as | NOP | NOP | MOV (RA, A0) | INC (R
A) | NOP, and MVI (ROA, 0), 11 in the tenth row in FIG.
CLR (A0) on line 12 and JNC1 AA on line 12
Is obtained by combining three rows into one row as shown in the eighth row in FIG. 13, and | CLR (A0) | NOP | MVI (ROA, 0) | J
NC1 AA.

In this case, when the number of executions is counted by a conventional clock, the first to fourth rows are executed once each, and the fifth to sixth rows are executed by the first count register (0) 13. 16 from “0fh” to “00h”
The second count register (1) 14 changes the value from “0fh” to “0fh” by adding two rows from the seventh row to the eighth row to the 16 repetitions from the fifth row to the sixth row. 0
It will be repeated 16 times until it reaches 0h ".
Therefore, the total number of executions is 4 + [{(2 × 16) +2} × 16] = 548 (7), which is (837−548) ÷ 837 compared to the conventional method. = 0.345 (8) and can be executed in a small number of times, about 30% and 5 minutes. this is,
Compared to the case of the first embodiment, (581-548) ０．０５581 = 0.057 (9), and can be executed in about 0.6% less times.

However, since the instruction code is divided into four using a 2-bit quaternary counter,
Since the speed of the execution clock is four times as high as that of the conventional clock (see the quadruple clock in FIG. 16 to be described later), the actual number of clocks is 548 × 4 = 2192... ... (10), 2192/837 = 2.619 (11), and the power consumption is about 2.6 compared to the conventional method. The problem of doubling will newly arise.

(Embodiment 4) Therefore, the present embodiment is intended to reduce power consumption by providing a control code for controlling whether the count value of a quaternary counter is valid or not in an instruction code. Digital signal processor.

Control codes N0, N1, N2, and N3, which are bits for preventing generation of a clock in the case of "NOP" in the instruction code of FIG.
Is added to the conversion code as shown in FIG. 14 so as to reduce the number of executions with a quadruple clock. That is,
The control code N0 is set in the 40th bit, the control code N1 is set in the 41st bit, the control code N2 is set in the 42nd bit, and the control code N3 is set in the 43rd bit.

FIG. 15 is a block diagram showing a configuration of the ROM data converter 3 for reducing the number of executions, and FIG. 16 is a diagram showing its timing.

The output of the instruction ROM 2 is an instruction output and control codes N0, N1, N2,
N3, the instruction output is output to the next stage system controller 4 as it is, and the control code N
0 to N3 are output to the ROM data converter 3, respectively. The quadruple clock is connected to a quaternary counter 21 and an AND gate 28 which can have four values in two bits. Decoder 22
Outputs select signals A to D to the system controller 4 at the next stage in accordance with the count value of the quaternary counter 21. Select signals A, B, C, D and control code N
0, N1, N2 and N3 are AND gates 23 and 2 respectively.
4, 25, 26, and their outputs are input to an OR gate 27. The output of the OR gate 27 is input to the AND gate 28, and is ANDed with the quadruple clock,
The output of the D gate 28 is output as a system clock of the digital signal processor.

A quaternary counter 21 to which a quadruple clock is input
Outputs a count 0, and when only the select signal A from the decoder 22 is "H" and the control code N0 is "1", A
Since the ND gate 23 is turned on and the OR gate 27 is turned on, the AND gate 28 is turned on, and the quadruple clock is output as the system clock. A part of the instruction code on the fifth line in FIG. AA: ADD (A1, A1, P) MULT] is selected by the select signal A. When the quaternary counter 21 outputs the count 1 and only the select signal B from the decoder 22 is "H" and the control code N1 is "1", the AND gate 24 conducts and the OR gate 27 conducts.
When the D gate 28 is turned on, the quadruple clock is output as the system clock, and a part of the instruction code on line 5 in FIG. 13 [INC in assembler format]
(RO)] is selected by the select signal B. When the quaternary counter 21 outputs count 2 and only the select signal C from the decoder 22 is "H" and the control code N2 is "0", the AND gate 25 and the other three ANs are output.
Since all the D gates are non-conductive and the OR gate 27 is also non-conductive, the AND gate 28 is non-conductive and there is no output as the system clock of the quadrupled clock. However, a part of the instruction code on the fifth line in FIG. 13 [the first NO in assembler format]
P] is selected by the select signal C. When the quaternary counter 21 outputs the count 3 and only the select signal D from the decoder 22 is "H" and the control code N3 is "0", the AND gate 26 and the other three AND gates are all turned off. , AND gate 2
8 is in a non-conductive state, and the output as the system clock of the quadruple clock disappears. However, part of the instruction code on the fifth line in FIG. 13 (the second NOP in assembler format) is selected by the select signal D.

Next, the quaternary counter 21 again counts 0.
When only the select signal A from the decoder 22 is "H" and the control code N0 is "1", the AND gate 23 is turned on. A part of the instruction code on the sixth line in FIG. 13 [SBA (A1, A1, P) MUL in assembler format]
T] is selected by the select signal A. When the quaternary counter 21 outputs the count 1 and only the select signal B from the decoder 22 is "H" and the control code N1 is "1", the AND gate 24 becomes conductive.
8, the quadruple clock is output as the system clock, and a part of the instruction code (INC (RO) in assembler format) on the sixth line in FIG. Quaternary counter 21
Outputs a count 2, and when only the select signal C from the decoder 22 is "H" and the control code N2 is "0", A
Since the ND gate 25 and the other three AND gates are all non-conductive, the AND gate 28 is non-conductive, and there is no output as the system clock of the quadrupled clock. However, a part of the instruction code (NOP in assembler format) on the sixth line in FIG. The quaternary counter 21 outputs the count 3 and the select signal D from the decoder 22
When only the control code N3 is "1" and the control code N3 is "1", AND
Since the gate 26 is turned on, the AND gate 28 is turned on, and the quadruple clock is output as the system clock. A part of the instruction code on the sixth line in FIG. 13 [in the assembler format, JNC0 AA] is the select signal D. Selected by.

Next, the quaternary counter 21 again counts 0.
When only the select signal A from the decoder 22 is "H" and the control code N0 is "0", the AND gate 23 and the other three AND gates are all turned off. Becomes non-conductive,
The output as the system clock of the quadruple clock disappears. However, part of the instruction code on the seventh line in FIG. 13 (the first NOP in assembler format) is selected by the select signal A. When the quaternary counter 21 outputs the count 1 and only the select signal B from the decoder 22 is "H" and the control code N1 is "0", the output as the system clock of the quadrupled clock disappears as described above. However, a part (the second NOP in assembler format) of the instruction code on the seventh line in FIG. The quaternary counter 21 outputs the count 2 and the select signal C from the decoder 22
When only the control code N2 is "1" and the control code N2 is "1", AND
Since the gate 25 is turned on, a four-fold clock is output as a system clock from the AND gate 28, and a part of the instruction code [MOV (RA, A0) INC (RA) in assembler format] of the seventh line in FIG. 13 is selected. Selected by signal C. When the quaternary counter 21 outputs the count 3 and only the select signal D from the decoder 22 is "H" and the control code N3 is "0", the output as the system clock of the quadrupled clock disappears as described above. However, a part (third NOP in assembler format) (not shown) of the instruction code on the seventh line in FIG. 13 is selected by the select signal D.

The number of executions in the fourth embodiment is the same as that of the equation (7) in the third embodiment. However, when the actual number of clocks when a quadruple clock is used is obtained, Since unnecessary clocks are removed, 7 + [{(5 × 16) +4} × 16] = 1351... ...... (12), and 1351/837 = 1.614... (13) The number of clocks used is about 1.
It can be suppressed to about six times.

In the third and fourth embodiments, N is an arbitrary natural number of 1 or more, instead of the quaternary counter 21, and the ROM of the instruction ROM 2 is
An embodiment using an N-ary counter that counts at N times the clock of the address counter 1 is also conceivable.

In each of the first to fourth embodiments, the present invention is applied to a general integrated circuit including a microcomputer whose internal control is performed by an instruction code, instead of being configured as a digital signal processor. May be.

[0087]

According to the digital signal processor of the first aspect of the present invention, the instruction code is processed by bit inversion or the like to generate a plurality of codes from one instruction code and control a plurality of circuits. The operating speed of the entire digital signal processor can be substantially improved without increasing the operating speed of the digital signal processor.

According to the digital signal processor of the second aspect of the present invention, since a plurality of codes are formed from one instruction code by bit inversion, the means can be simplified.

According to the digital signal processor of the third aspect of the present invention, a control code for deciding whether or not to perform bit inversion is provided to perform bit inversion only on necessary portions, thereby increasing the operation speed. Accordingly, it is possible to prevent an unnecessary increase in power consumption.

According to the digital signal processor of the fourth aspect of the present invention, since an N-fold clock is generated by using the N-ary counter and controlled by this clock, the apparent speed can be increased by N times. .

According to the digital signal processor of the fifth aspect of the present invention, a control code for determining the validity of the count value of the N-ary count is provided, and only necessary parts are controlled by N times clock. Therefore, it is possible to prevent an unnecessary increase in power consumption caused by increasing the operation speed.

According to the integrated circuit of the sixth aspect of the present invention, the same effects as described above can be obtained in a microcomputer or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a digital signal processor according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a structure of a conversion code for calling an instruction code stored in an instruction ROM of a digital signal processor according to a conventional technique based on an assembler.

FIG. 3 is a diagram showing an example of a source program using an assembler language used for explaining the operation of the embodiment of the present invention and the conventional technique.

4 is an explanatory diagram of an instruction code corresponding to the assembler code on the first line of the source program in FIG. 3;

FIG. 5 is an explanatory diagram of instruction codes when the program of FIG. 3 is converted according to the conversion code of FIG. 2 by a conventional method.

6 is a code correspondence diagram in which the assembler code of FIG. 3 and the instruction code of FIG. 5 are compared in the conventional method.

FIG. 7 In the digital signal processor according to the first embodiment of the present invention, the bit inversion code of “ADD” in the sixth row in FIG. 3 has the meaning of “SBA”, and the other bit inversion codes are “NOP”. FIG. 14 is a diagram showing a source program in an assembler language when "."

FIG. 8 is a code correspondence diagram in which the assembler code of FIG. 7 is compared with the corresponding instruction code in the first embodiment.

FIG. 9 is an explanatory diagram of a structure of a conversion code for calling an instruction code stored in an instruction ROM based on an assembler for performing bit inversion in the first embodiment.

FIG. 10 is a block diagram showing a configuration of a ROM data converter for reducing the number of executions in a digital signal processor according to a second embodiment of the present invention.

FIG. 11 is a timing chart for explaining the operation of the second embodiment.

FIG. 12 is an explanatory diagram of a structure of a conversion code for calling an instruction code stored in an instruction ROM based on an assembler to reduce power consumption in the digital signal processor according to the third embodiment of the present invention. is there.

FIG. 13 is a diagram showing a source program obtained by converting the source program of FIG. 3 using the conversion code of FIG. 2 in the third embodiment.

FIG. 14 is a block diagram showing a digital signal processor according to a fourth embodiment of the present invention, in which an instruction code stored in an instruction ROM, in which a control code for preventing generation of a quadruple clock is added to a “NOP” portion, is transmitted to an assembler. FIG. 3 is an explanatory diagram of a structure of a conversion code for calling based on the above.

FIG. 15 is a block diagram showing a configuration of a ROM data converter for reducing the number of executions in the fourth embodiment.

FIG. 16 is a timing chart for explaining the operation of the fourth embodiment.

[Explanation of symbols]

 1 ROM address counter 2 Instruction ROM 3 ROM data converter 3a Data selector 3b ROM data inverter 3c 1/2 frequency divider 4 System controller 5 Temporary register 6 Table ROM 7 RAM 8 Multiplier 9 ALU (logical operation unit) 10 First save register (ACC0) 11 Second save register (ACC1) 12 Data bus 13 1 count register (0) 14 ... second count register (1) 15 ... RAM address counter 16 ... ROM address counter 21 ... quaternary counter 22 ... decoder A ... control code I ... instruction code N0 to N3 ... control code

Claims (6)

[Claims] 1. A digital signal processor in which internal control is performed by an instruction code, wherein the digital signal processor has a code for enabling control of a plurality of circuits with one code of an instruction ROM. 2. The digital signal processor according to claim 1, wherein one code is converted into a code for controlling a plurality of circuits by bit inverting a part or all of the instruction code. 3. The digital signal processor according to claim 2, further comprising a control code for controlling whether or not the instruction code is bit-inverted. 4. An N-ary counter which counts with a clock N times (N is a natural number of 1 or more) of the address counter separately from the address counter of the instruction ROM, and one code is generated based on the count value of the N-ary counter. 2. The digital signal processor according to claim 1, wherein the signal is converted into a code for controlling a plurality of circuits. 5. The digital signal processor according to claim 4, further comprising a control code for controlling whether or not a count value of an N-ary counter that counts at N times the clock of the address counter is valid. 6. The integrated circuit according to claim 1, further comprising a microcomputer for performing internal control by an instruction code similarly to the digital signal processor.