JP2706459B2 - Microprocessor with decimal multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

TECHNICAL FIELD The present invention relates to a microprocessor having a decimal multiplier suitable for controlling a device. 2. Description of the Related Art Recently, many microprocessors have a multiplication instruction, a general-purpose microprocessor has an integer multiplier, and a signal processor used for signal processing and device control has a floating-point multiplication. Vessel is mounted. Now, let us consider a case where a main part of the motor rotation speed control device as shown in FIG. 3 is realized by a microprocessor. When the speed error detection unit 1 outputs integer error data, the digital filter 2 After compensation in the frequency domain, the signal is converted into a DC voltage by the DA converter 3. By the way, as is well known, this kind of digital filter generally treats a decimal as a multiplier. On the other hand, what is input to the digital filter 2 is integer error detection data. As such a multiplier, a multiplier that handles only integers or a large-scale floating-point multiplier is used. Problems to be Solved by the Invention However, the conventional microprocessor multiplier described above has a problem that the multiplication of the integer multiplicand and the decimal multiplier cannot be directly performed. Therefore, a multiplier that handles only integers requires a large number of multipliers to speed up the execution, which increases the area of the IC and increases the cost. Means for Solving the Problems In order to solve the above-mentioned problems, a microprocessor having a decimal multiplier according to the present invention has a microprocessor having a decimal multiplier for multiplying integer multiplicand data and decimal multiplier data of 1 or less. ALU for performing arithmetic and logic operations on N-bit (N is an integer) first and second data supplied via a data bus, and N-bit multiplicand data supplied from the data bus. A covering number register, a multiplier register for storing M (M is an integer equal to or less than N) bits of multiplier data supplied from the data bus,
A multiplication control circuit that sends M addition execution instruction signals to U, and each time an addition execution instruction signal is sent, the discrimination bit position is shifted by one bit from a lower bit to an upper bit,
Bit discriminating means for outputting a value at the discriminating bit position of the multiplier data, switch means for supplying the covering number data or 0 value to the ALU as first data according to the output of the bit discriminating means, and shifting the output of the ALU to the right And an N-bit right shifter to be supplied to the ALU as second data, and N-bit output data of the ALU after M times of addition performed by the ALU as a multiplication result and transmitted to the data bus without passing through the right shifter. Output means. According to the present invention, a microprocessor having a multiplier capable of directly executing multiplication of integer multiplicand data and decimal multiplier data by the above-described configuration is obtained. Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a fractional multiplier of a microprocessor according to an embodiment of the present invention. On the transfer path of the multiplicand data supplied from the 16-bit data bus 10 to the multiplicand register 11 to the ALU (arithmetic logical operation unit) 20, a 16-bit switch group 32 opened and closed by the output of the bit AND circuit 31 is provided. The output data of the ALU 20 is returned to the input side of the ALU 20 via the output register 21, the 16-bit feedback bus 22, and the right shifter 33. Further, one input side of the bit AND circuit 31 is supplied with multiplier data from the data bus 10 via the multiplication register 12, and the other input side is provided with a multiplication control circuit via a decoder 34.
A bit position selection signal from the multiplication control circuit 35 is supplied to the ALU 20, and a bit position selection signal from the multiplication control circuit 35 is supplied to the ALU 20. The bit position selection signal is supplied from the multiplication control circuit 35 to the decoder 34 as numerical data from 0 to 15, and the decoder 34 performs a bit AND operation on the 16-bit data in which the bit position corresponding to the numerical data is set. Circuit 31
To send to. The bit AND circuit 31 performs an AND operation on the multiplier data and the data from the decoder 34, and outputs the result as 1
It is converted to bits and sent to the switch group 32. The switch group 32 is closed when the output of the bit AND circuit 31 is “1”, and is open when the output is “0”. When the switch group 32 is in the open state, zero is supplied to the multiplicand side of the ALU 20. The right shifter 33 shifts the input data in the decreasing direction of the value and supplies it to the input side of the ALU 20, and the input result is the addition result of the ALU 20. Now, the multiplicand data is hexadecimal [4E20], that is,
Decimal number is 20000, multiplier data is hexadecimal number [8000]
Assuming that the decimal point data is 1.0 in decimal, the multiplication control circuit 35 outputs a value from 0 to a bit discrimination unit 40 composed of a bit AND circuit 31 and a decoder 34.
Up to 15 numerical data are supplied and at the same time 1 for ALU20
When the intermittent addition execution command signal for six times is supplied, the data Rn of the output of the tecoder 34, the output Cn of the bit discriminator 40, the output data Dn of the output register 21, and the output data Sn of the right shifter 33 are as follows. Transition. Here, the output register 21 holds the previous value as its output data until the addition operation is completed. n Rn Cn Dn Sn (1) [0001]

[0] [0000] [0000] (2) [0002]

[0] [0000] [0000] (3) [0004]

[0] [0000] [0000] (4) [0008]

[0] [0000] [0000] (5) [0010]

[0] [0000] [0000] (6) [0020]

[0] [0000] [0000] (7) [0040]

[0] [0000] [0000] (8) [0080]

[0] [0000] [0000] (9) [0100]

[0] [0000] [0000] (10) [0200]

[0] [0000] [0000] (11) [0400]

[0] [0000] [0000] (12) [0800]

[0] [0000] [0000] (13) [1000]

[0] [0000] [0000] (14) [2000]

[0] [0000] [0000] (15) [4000]

[0] [0000] [0000] (16) [8000] [1] [4E20] [0000] The multiplication result is equal to the multiplicand [4E20] multiplied by the decimal number 1.0. Similarly, if the multiplicand data is hexadecimal [4E20] and the multiplier data is hexadecimal [5555] fixed-point data and decimal is 0.6666564, the multiplication control circuit 3
When numerical data from 0 to 15 is supplied to the 5-bit discriminating unit 40, and at the same time a pulse signal of 16 cycles is supplied to the ALU 20, the data Rn,
The output Cn of the bit determination unit 40, the output data Dn of the ALU 20, and the output data Sn of the right shifter 33 transition as follows. n Rn Cn Dn Sn (1) [0001] [1] [4E20] [0000] (2) [0002]

[0] [2710] [2710] (3) [0004] [1] [61A8] [1388] (4) [0008]

[0] [30D4] [30D4] (5) [0010] [1] [668A] [186A] (6) [0020]

[0] [3345] [3345] (7) [0040] [1] [67C2] [19A2] (8) [0080]

[0] [33E1] [33E1] (9) [0100] [1] [6810] [19F0] (10) [0200]

[0] [3408] [3408] (11) [0400] [1] [6824] [1A04] (12) [0800]

[0] [3412] [3412] (13) [1000] [1] [6829] [1A09] (14) [2000]

[0] [3414] [3414] (15) [4000] [1] [682A] [1A0A] (16) [8000]

[0] [3415] [3415] In this case, the multiplication result is [3415], which is 13333 in decimal, which is equal to a large number of [4E20] multiplied by the decimal number 0.6666564. After all, in the decimal multiplier shown in FIG. 1, the multiplication result A is calculated from the value D of the multiplicand data and the value M of the multiplier data as follows. ^{D = d15 · 2 15 + d14} · 2 14 + ... + d2 · 2 2 + d1 · 2 1 + d0 · 2 0 ...... (1) M = m15 · 2 0 + m14 · 2 -1 + ... + m2 · 2 -13 + m1 · 2 ^-14 + m0 · 2 ^-15 (2) where d15 and m15 are the values of the most significant bits of the multiplicand data D and the multiplier data M, respectively, and d0 and m0 are the least significant bits of the multiplicand data D and the multiplier data M, respectively. The value of a bit. The addition result a0 at the time when the first addition operation is completed is a0 = m0 · D (3) The addition result a1 at the time when the second addition operation is completed is a1 = m1 · D + a0 / 2 = m1 D + m0D / 2 (4) When the third addition operation is completed, the addition result a2 is as follows: a2 = m2D + a1 / 2 = m2D + m1D / 2 + m0D / 4 (5) ) Therefore, a = m15 · D + m14 · D / 2 1 + ... + m0 · D / 2 15 ...... (6) a = D · M in this way, the fractional multiplier of FIG. 1, and integer multiplicand data Multiplication with decimal multiplier data can be easily performed. Also, in the conventional integer multiplication, when a 16-bit data multiplication is executed, a 32-bit register or a memory area is required to store the result, but in the decimal multiplier of FIG. As long as the number does not exceed 1, no overflow occurs, so that the number of bits required to store the multiplication result is small. FIG. 2 shows another embodiment of the present invention.
In the decimal multiplier shown in FIG. 2, a shift register 36 is used as a bit discriminating means for discriminating a bit-by-bit value in order from the least significant bit of the multiplier data, and the shift register 36 is supplied from the multiplication control circuit 35 to the ALU 20. Addition command signal ADD
The right shift command signal composed of the same 16-cycle pulse train is supplied, and the switch group 32 is opened and closed by the shift carry from the shift register 36. In this embodiment, both the multiplicand data and the multiplier data are used.
Although the case of 16 bits has been described, both need not necessarily have the same number of bits. For example, if the multiplier data is 8 bits in FIG. 1, the multiplication control circuit 35 may generate an 8-cycle pulse, in which case the multiplication is completed more quickly. Further, for convenience of explanation, the multiplicand data and the multiplier data are distinguished from each other, but it is apparent from the equations (1) to (6) that there is no problem even if these data are exchanged. By the way, the ALU 20 of FIGS. 1 and 2 can use the one originally provided in the microprocessor, and includes the output register 21, the multiplicand register 11, and the multiplier register.
The same applies to 12. Therefore, referring to the embodiment of FIG. 1, a multiplication control block 30 composed of a bit AND circuit 31, a switch group 32, a right shifter 33, a decoder 34, and a multiplication control circuit 35 is added to the core of the microprocessor. Just need. 2, the switch group 32, the right shifter 33, the multiplication control circuit 35, the shift register 3
6 constitutes a multiplication control block 30 similar to that shown in FIG. As is apparent from the above description, the microprocessor having the decimal multiplier according to the present invention includes an ALU for performing addition and subtraction of N-bit data supplied through the data bus, and an NLU supplied from the data bus. A multiplicand register that stores integer multiplicand data in bits, a multiplier register that stores M-bit fractional multiplier data of 1 or less supplied from the data bus, and multiplication control that sends an MLU addition execution command signal to the ALU A circuit, bit discriminating means for discriminating a value at a discriminating bit position of multiplier data every time an addition execution command signal is sent out, and multiplicand data or a zero value as ALU first data according to an output of the bit discriminating means. Switch means for supplying, a right shifter for shifting the output of the ALU to the right and supplying it to the ALU as the second data, and N of the ALU after M additions have been performed in the ALU. Since output means for transmitting bit output data to the data bus as a result of multiplication without passing through the right shifter is provided, N-bit integer data and N or less can be obtained simply by adding a circuit having a very simple configuration. M
A microprocessor capable of executing multiplication of decimal data of bits can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a decimal multiplier showing one embodiment of the present invention, FIG. 2 is a block diagram of a decimal multiplier showing another embodiment of the present invention, and FIG. 3 requires a decimal multiplier. It is a block diagram of a control device. 10 Data bus, 20 ALU, 22 Return bus, 30
... Multiplication control block, 32 ... Switch group, 33 ... Right shifter, 35 ... Multiplication control circuit, 36 ... Shift register, 40 ...
... Bit discrimination unit.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yutaka Ota 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-59-172040 (JP, A) JP-A-59-229644 (JP, A) JP-A-61-163393 (JP, A) Jpn. Tadaaki Tarui and Keikichi Tamaru, "Electronic Circuit Course 10 Digital Computing Circuit", 5th Edition, 50-3-30 Asakura Shoten, P.S. 158-P. 161 Kai Hwang, translated by Yasushi Horikoshi [High-speed computing method of computer], 2nd printing, 57-8-1, Shogaku Kagakusha p. 130 to p. 135 Information Processing Society of Japan, "New Edition Information Processing Handbook", 1st edition, 3rd printing, Ohmsha, July 20, 1982, p. 802-p. 805 Hiroshi Hagiwara, "Introduction to Computers 2", 11th edition, March 10, 1978, Asakura Shoten, pp. 32-p. 35

Claims (1)

(57) [Claims] 1. A microprocessor having a decimal multiplier for multiplying an integer multiplicand data and a decimal multiplier data of 1 or less, comprising: a first N-bit (N is an integer) first signal supplied via a data bus; ALU for performing an arithmetic and logic operation on second data, a multiplicand register for storing N-bit multiplicand data supplied from the data bus, and M (M is an integer equal to or less than N) bits supplied from the data bus A multiplier register for storing multiplier data of
A multiplication control circuit for transmitting the addition execution command signal twice, and each time the addition execution command signal is transmitted, the discrimination bit position is shifted by one bit from the lower bit to the upper bit to thereby determine the multiplication data at the discrimination bit position. Bit discriminating means for outputting a value, switch means for supplying the multiplicand data or zero value as first data to the ALU according to the output of the bit discriminating means, and shifting the output of the ALU to the right to the ALU. An N-bit right shifter to be supplied as the second data and N-bit output data of the ALU after the M times of addition performed by the ALU are sent to the data bus as a multiplication result without passing through the right shifter. A microprocessor having a decimal multiplier comprising output means for performing the following.