JPS6210733A - Adding control system - Google Patents

Abstract

PURPOSE:To execute a simultaneous processing with a simple constitution and to execute the high speed of the processing by providing a selecting circuit which selects the output of both adders with the first and second converting circuits. CONSTITUTION:The output of adders 1 and 2 are inputted to a multiplexing circuit 3 which operates as a selecting circuit, and the connecting selecting signals S1 and S2 of the multiplexing circuit 3 are outputted from a prefixing converting part 4 which operates as the first converting circuit and an SBR converting part 5 which operates as the second converting circuit respectively. The prefixing converting part 4, when the actual addresses are all 0, selects the output of an adder 1, and when the actual address exists in another conditions, so as to select the adding result of the base value and the actual address, namely, the output of an adder 2, the multiplexor circuit 3 is controlled. In the same way as the SBR converting part 5, when the address is an SBR value, 0 is selected, when 1-19 bits of data (b) are all 0, the SBR value is selected, and when the data (b) are excluded, the data (b) are selected. Only either of the prefixing conversion and SBR conversion is exclusively executed. Thus, with a very simple circuit constitution, the adding precessing is executed at a high speed.

Description

[Detailed Description of the Invention] [Summary] This is an addition control method, which includes an adder that adds at least two pieces of data separately to a second input, and a selection circuit that selects the addition result. By performing the conversion and addition at the same time, it is possible to speed up the calculation process.

[Industrial application field]

The present invention relates to an arithmetic control method that performs conversion on an input, performs addition with a second input, and performs a second conversion on the addition result.

Addition circuits are widely used in fields such as information processing. On the other hand, the processing speed of information processing is required to be high, and it is necessary to perform addition processing at high speed. In particular, there is a need for an addition control method that can handle high-speed addition processing, such as when adding a transformation to an input, adding it to a second input, and then performing a second transformation on the result. .

[Conventional technology]

There is an addition process in which input data A, which is composed of a plurality of pieces of data, is converted depending on the state of the data, added to input data B, and a second conversion is performed on the addition result.

Conventionally, when performing addition processing as described above, a circuit shown in FIG. 2 has been used. That is, input data A composed of at least two pieces of data a and b is input to the conversion circuit 4.
The signal is input to the adder 6, subjected to necessary conversion, and then input to the adder 6. Input data B is further input to the adder 6. The adder 6 adds the output of the conversion circuit 4 and the input data B, and the second conversion circuit 5 performs the conversion, and the arithmetic processing ends.

The conventional method described above includes conversion by converter 4, adder 5
The addition by the converter 5 and the conversion by the converter 5 require sequential steps, and the processing takes time.

[Problem that the invention seeks to solve]

In the conventional method, conversion, addition, and conversion are performed sequentially, making it difficult to shorten the processing time.

The present invention was created in view of these points.
The purpose of this invention is to provide an addition control method that can perform simultaneous processing with a simple configuration and can speed up processing.

[Means for solving problems]

Adders are provided for adding data a of first input data A and second input data B, and adding data b of first input data A and second input data B, respectively. The configuration includes a selection circuit that selects the outputs of both adders using a second conversion circuit.

[Effect]

Both adders and the first. By operating the second conversion circuit simultaneously, the speed of addition processing is increased.

〔Example〕

FIG. 1 shows an embodiment of the present invention, and to make the explanation easier to understand, the explanation will be given using prefix conversion as an example.

When multiple CPUs (or virtual machines) share a main storage device, a fixed area of each CP[I (or virtual machine) is provided as a unique area. Therefore, the absolute address, which is the address on the main memory, is set to a different address for each CPU (or virtual machine).

Prefix conversion converts this real address into an absolute address.

In addition, the control program (or hypervisor) that controls these multiple CPUs (or virtual machines) includes a
A special area that is invisible to the control program (or hypervisor) is allocated and special address translation for the control program (or hypervisor) is called SBR translation.

This will be explained using FIG. Input data A is composed of data a and data b. For example, data a has a prefix value (
(hereinafter referred to as PRFX).

Data b is the real address stored in address register 8.

Input data B is the base value stored in the base register 9. Input data C is a system base register (SBR) value stored in register 10.

PRFX is 19 bits from bits 1 to 19 of prefix register 7. PRFX (data a) and the base value (data B) are input to an adder 1. The real address (data b) and base value (data B) are input to the adder 2.

The output of adder 1.2 is input to multiplex circuit 3, which operates as a selection circuit. The connection selection signals St and S2 of the multiplex circuit 3 are output from the prefix converter 4 operating as a first converter circuit and the SBR converter 5 operating as a second converter circuit, respectively.

The prefix converter 4 operates in response to a control signal S3 indicating the operation mode of each CPU (or virtual machine), and converts the SBR
The converter 5 operates in response to a control signal S4 indicating the operating mode of the control program (or hypervisor).

The prefix conversion unit 4 selects the base value (data B) when PRFX (data a) and real address (data B) are input and the PRFXO value is not zero and equal to bits 1 to 19 of the real address. The multiplexer circuit 3 is controlled so as to.

Furthermore, the prefix converter 4 selects the output of the adder 1 when the real address (bits 1 to 19 of data b) are all "0", and selects the output of the adder 1 when the real address is in a state other than the above. The multiplexer circuit 3 is controlled to select the result of addition of the value (data B) and the real address (data b), that is, the output of the adder 2.

Similarly, in the SBR conversion unit 5, when data b and data C are equal, that is, when the address is an SBR value, rOJ is selected, and when all 1 to 19 bits of data b are "0", data C, that is, SBR If a value is selected and data b is other than, data b is selected.

Note that only one of the prefix conversion and SBR conversion is executed exclusively.

Therefore, conventionally, processing was performed in three steps: first conversion, addition, and second conversion. The process is completed in two steps: second conversion and addition are performed simultaneously, and selection is made.

〔Effect of the invention〕

As described above, according to the present invention, addition processing can be performed at high speed with an extremely simple circuit configuration, and is extremely effective in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional addition control system.

Claims (1)

[Claims] A first transformation is performed on a first input (A) consisting of at least two pieces of data (a, b), and the transformed value and the second input (B) are
), an adder (1) that performs addition of the data (a) and the second input (B), and an adder (1) that performs the addition of the data (b) and the second input (B); an adder (2) that performs addition with the input (B) of the adder (1), (
2) A selection circuit (3) for selecting the output of step 2), and performing both additions and the first and second conversions at the same time.