JP2511262Y2 - Digital signal processor - Google Patents

Description

[Detailed description of the device]

The present invention relates to a digital signal processing device using a digital signal processor that executes high-speed multiply-accumulate operations according to a program.

[0001]

2. Description of the Related Art A memory for storing a program and data to be processed, an adder, and a multiplier are main components, and data delay and sum-of-products calculation according to a program stored in the memory are executed. The single-chip IC (digital signal processor, hereinafter referred to as "D") that can realize digital filters with various characteristics, reverberation adding circuit, etc.
"SP") has been conventionally known (for example, YM3608 manufactured by Yamaha Corporation).

[0002]

The DSP can realize various functions by changing the program. However, even if it is desired to change only a part of the characteristics of a certain specific function, the whole program needs to be reviewed, and many DSPs are required. Need the labor of.

In order to avoid this, a plurality of DSPs that realize different functions may be provided in parallel, and one of them may be selected and used as needed. However, in such a configuration, it is necessary. As many DSPs as necessary are required. Therefore, in order to realize many functions,
A large number of DSPs are required, which causes an increase in cost.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a digital signal processing apparatus which can realize many functions at low cost and can easily change the functions. To aim.

[0005]

To achieve the above object, the present invention provides an input terminal to which a signal to be processed is input, an output terminal to which a processed signal is output, and a delay and One of a plurality of digital signal processors performing a sum of products operation, at least one adder, a signal input to the input terminal, an output signal of the plurality of digital signal processors, and an output signal of the adder
At least two of a first selection circuit that selects one of them, and inputs the digital signal processor to the digital signal processor; a signal input to the input terminal; an output signal of the plurality of digital signal processing units; and an output signal of the adder. And a third selection circuit for selecting one of the output signals of the plurality of digital signal processors and the output signal of the adder and outputting the output signal to the output terminal. A selection circuit and a control means for supplying a selection control signal indicating a signal to be selected by the first, second and third selection circuits to each selection circuit are provided.

[0006]

The connection state of the plurality of digital signal processors and the adder is changed according to the selection control signal, and the content of signal processing in the process from the input terminal to the output terminal is changed.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a digital signal processing apparatus according to an embodiment of the present invention. This apparatus has input terminals 1 and 2, an output terminal 3, and first to sixth data selectors. 4 to 9, first to third digital signal processors (hereinafter referred to as "DSP") 10 to 12, first and second
Adders 13 and 14, a decoder 15, and a latch circuit 1
6 and 6. A signal to be processed is input to the input terminal 1, and the processed signal is output from the output terminal 3. Further, selection data for determining the function of this device is input to the input terminal 2. The decoder 15 decodes the selection data and uses the latch circuit 1 as a selection control signal.
Enter in 6. The output of the latch circuit 16 is connected to the control input terminals of the first to sixth data selectors 4 to 9, and the selection control signal SC is input to each control input terminal.

The first to third data selectors (first selection circuits) 4 to 6 have six data input terminals (input 0 to input 5), one data output terminal, and a latch circuit 16. It has connected control input terminals, and the six data input terminals are connected to the input terminal 1, the outputs of the DSPs 10-12 and the adders 13 and 14, respectively, and the data output terminals are connected to the inputs of the DSPs 10-11, respectively. It is connected. Therefore, the first to third data selectors 4 to 6 are connected to the input terminal 1
Signal ID input to the output signal P of the DSP 10-12
1 to P3 and one of the output signals A1 and A2 of the adders 13 and 14 are selected according to the selection control signal SC and are input to the DSPs 10 to 12, respectively.

The fourth and fifth data selectors (second selection circuits) 7 and 8 have six data input terminals (input 0 to input 5), two data output terminals, and a latch circuit 16. 6 data input terminals are connected to the input terminal 1, the outputs of the DSPs 10 to 12 and the outputs of the adders 13 and 14, respectively, and the data output of the fourth data selector 7. All terminals are the first adder 1
3 and the data output terminals of the fifth data selector 8 are both connected to the second adder 14.
Therefore, the fourth and fifth data selectors 7 and 8 have the signal ID input to the input terminal 1, the output signals P1 to P3 of the DSPs 10 to 12 and the output signals A1 of the adders 13 and 14, respectively.
Two of A2 are selected according to the selection control signal SC and are input to the adders 13 and 14, respectively.

Each of the first to third DSPs 10 to 12 has a memory for storing a program and data to be processed, an adder, and a multiplier as main components, and stores data according to the program stored in the memory. And the circuit configuration (hardware configuration) is the same. However, each has a different program and has a different function (for example, a function as a filter having different characteristics, a function as a reverberation adding circuit, or the like).

The first and second adders 13 and 14 add two input signals and output the added signals.

Sixth data selector (third selection circuit)
9 is five data input terminals (input 0 to input 4) and 1
The data output terminals and the control input terminal connected to the latch circuit 16 are provided, and the five data input terminals are connected to the outputs of the DSPs 10 to 12 and the outputs of the adders 13 and 14, respectively, and output the data. The terminal is connected to the output terminal 3. Therefore, the sixth data selector 9 is
One of the output signals P1 to P3 of .about.12 and the output signals A1 and A2 of the adders 13 and 14 is selected according to the selection control signal SC and output to the output terminal 3 as processed data OD.

The operation of the signal processing apparatus configured as above will be described below.

As the selection control signal SC, for example, first to first
Input 4, input 1 and input 1 are selected for the third data selectors 4 to 6, respectively, and inputs 0 and 5 and input 2 are selected for the fourth and fifth data selectors 7 and 8, respectively.
Select 3 and input 0 for the sixth data selector 9.
When a signal for selecting (hereinafter referred to as “signal SC1”) is stored in the latch circuit 16, the configuration of this device is
It becomes as shown in FIG. That is, according to the signal SC1, the input signal ID is input to the first adder 13 via the fourth data selector 7, and the output of the first adder 13 is output via the first data selector 4. First DSP 10
And the output of the first DSP 10 is input to the second and third DSP 1 through the second and third data selectors 5 and 6.
6th data selector 9
Is connected to the output terminal 3 via the output terminals of the second and third data selectors 5 and 6 and is input to the second adder 14 via the fifth data selector 8. 2A is equivalently input to the first adder 13 via the fourth data selector 7 in FIG.
The configuration of is realized.

As the selection control signal SC, for example, for the first to third data selectors 4 to 6, the input 4, the input 1 and the input 2 are selected, and the fourth and the fifth data selectors 7 and 8 are selected. Selects inputs 0, 3 and inputs 0, 1 respectively, and a signal for selecting input 1 for the sixth data selector (hereinafter referred to as "signal SC2").
2 is stored in the latch circuit 16, the configuration of this device is as shown in FIG. That is, according to the signal SC2, the input signal ID is input to the first adder 13 via the fourth data selector 7, and the output of the first adder 13 is output via the first data selector 4. First DSP 10
Is input to the second DSP 11 via the second data selector 5, and the output of the first DSP 10 is input to the second DSP 11.
The output of the DSP 11 is input to the third DSP 12 via the third data selector 6 and is also connected to the output terminal 3 via the sixth data selector 9 to generate the third D
The output of SP12 is the first data through the fourth data selector 7.
2 is input to the adder 13, so that the configuration of FIG. 2B is equivalently realized. The signal SC
In the case of 2, since the second adder 14 is not used,
Dummy data is inserted in a portion of the selection control signal corresponding to the fifth data selector 8 (a portion instructing selection of inputs 0 and 1 of the fifth data selector 8). On this occasion,
In order to clearly indicate that the data is not used, 0 input may be prepared as the input of the selector and used.

As described above, according to this apparatus, the connection state of the DSPs 10-12 and the adders 13 and 14 can be easily changed by changing the selection control signal SC. As a result, many functions can be realized by using a small number of DSPs, and the functions can be easily changed.

In the above embodiment, the adder 13,
Although 14 uses the one that adds two input signals, it is not limited to this, and one that adds three or more input signals may be used. In that case, as the data selector provided on the input side of the adder, one having the number of outputs corresponding to the number of inputs of the adder may be used.

[0019]

As described in detail above, according to the present invention, since the connection states of a plurality of digital signal processors and adders are changed according to the selection control signal, signals in the process from the input terminal to the output terminal are changed. The content of processing can be easily changed. As a result, many functions can be realized by using a few digital signal processors, and the functions can be easily changed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the digital signal processing device of FIG.

[Explanation of symbols]

 1 Input Terminal 3 Output Terminal 4-9 Data Selector 10-12 Digital Signal Processor 13,14 Adder 16 Latch Circuit

Claims (1)

(57) [Scope of utility model registration request] 1. An input terminal to which a signal to be processed is input, an output terminal to which a processed signal is output, a plurality of digital signal processors that execute signal delay and product-sum operations according to a program, and at least One adder, a signal input to the input terminal, one of the output signals of the plurality of digital signal processors and the output signal of the adder, and a first selection for inputting to the digital signal processor A second selection circuit for selecting at least two of a circuit, a signal input to the input terminal, an output signal of the plurality of digital signal processing units, and an output signal of the adder, and inputting to the adder. A third selection circuit that selects one of the output signals of the plurality of digital signal processors and the output signal of the adder and outputs the selected output signal to the output terminal; A digital signal processing device, comprising: a control unit that supplies a selection control signal indicating a signal to be selected by the first, second, and third selection circuits to each selection circuit.