JP2001092658A - Data processing circuit and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor for reducing the increase of the physical scale, and for preventing the deterioration in arithmetic performance as a digital signal processor at the time of loading the functions of a microprocessor and a digital signal processor on one LSI. SOLUTION: This data processor is provided with by-paths 107, 108, 109, 110, and 112 arranged on data paths in parallel with pipe line registers as the paths of data for selectively obtaining data passing through the by-paths or data transmitted to the pipe line registers and selectors 13, 14, 16, and 23 for selectively outputting the outputs of the by-paths and the outputs of the pipe line registers. Also, an address generating circuit 17 is arranged differently from an instruction executing circuit A3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus for performing a pipeline process, and more particularly to a signal processing technique by a processor and a control technique by a processor, and performs both high-speed signal processing and complicated control. The present invention relates to a technology applied to required communication terminals, multimedia devices, and the like.

[0002]

2. Description of the Related Art Hitherto, examples of a processor in which a digital signal processor is mounted on a single LSI together with a microprocessor are described in JP-A-9-22379 and Hitachi SuperH RISC.
engine SH-DSP programming manual and Nikkei Electronics No. 666, pages 147 to 161 (prior art 1). According to this, a digital signal processing circuit is added to the CPU core, an instruction fetch circuit and an address generation circuit are shared to suppress an increase in physical scale, and ALU operation, multiplication, and parallel execution of two loads or stores are performed. Digital signal processing is speeded up by enabling processing.

[0003] Examples of a data processing apparatus which makes a pipeline of a processor variable are described in JP-A-9-319578 and JP-A-11-15.
No. 658 (prior art 2). According to this, the instruction execution circuit is variable in the number of pipeline stages to n stages and m stages larger than n, and performs the pipeline processing of the instruction in any of the n stages or the m stages. The pipeline control circuit switches the number of pipeline stages of the instruction execution means. According to this configuration, in the m-stage pipeline processing, the upper limit of the operation clock can be improved, and high processing performance can be improved. Further, in applications where a low-speed clock is sufficient, it is possible to use an n-stage pipeline process in which a penalty due to branch interlock is small.

[0004]

However, in the prior art 1, the DSP data transfer instruction and the DSP operation instruction include IF (instruction fetch), ID (instruction decode), and E (instruction decode).
X (instruction execution), MA (memory access), WB / DS
P (Write back or DSP write back / DSP)
Is processed by the 5-stage pipeline, and the DSP operation instruction is WB
Since the digital signal processing is executed in the / DSP stage, digital signal processing may not be performed at high speed. For example, consider the case where the DSP operation and the parallel processing of the memory store are repeatedly performed. Here, it is assumed that the data to be stored in the memory is the result of the operation in the immediately preceding parallel processing. In this case, for example, in the case shown in FIG.
Even if the operation result (instruction 1) obtained in the stage is to be stored (instruction 2) in the next parallel processing MA stage, the operation result has not been obtained yet, so that a conflict occurs and a stall cycle occurs. There is a problem that processing efficiency is reduced.

Further, in the above-mentioned prior art 1, there is a problem that the arithmetic units of the microprocessor and the digital signal processor are not physically shared, which leads to an increase in the physical scale.

[0006] Since the operations of the pipelines of the microprocessor and the digital signal processor are essentially different from each other, in order to mount them on one LSI and to speed up the digital signal processing, the instructions as the microprocessor and the digital signal processor must be used. I thought that it was necessary to switch the operation of the pipeline with this instruction.

In the above-mentioned prior art 2, the number of pipeline stages is made variable. However, the upper limit of the clock frequency is improved, and it is preferable to use a high-speed clock or a low-speed clock depending on the application. The purpose of the present invention is to provide a data processing device having good processing performance and high cost performance, and is not realized by switching pipeline operations between a microprocessor and a digital signal processor.

In view of the above, the present invention has been made to solve the above-described various problems, and when the functions of a microprocessor and a digital signal processor are mounted on one LSI, an increase in physical scale is suppressed as much as possible, and An object of the present invention is to provide a data processing device that does not degrade the operation performance as a signal processor.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. First, a data processing circuit for performing pipeline processing, which is provided on a data path. One or more bypass means provided,
As a data path, there is provided a bypass unit which can obtain a case where the data passes through the bypass and a case where the data reaches the pipeline register, and performs a switching operation between a pipeline operation of the microprocessor and a pipeline operation of the digital signal processor. It is characterized in that it is possible.

According to the data processing circuit having the first configuration, the pipeline operation of the digital signal processor can be realized by providing the data path with the bypass means provided in parallel with the pipeline register. When the functions of the processor and the digital processor are mounted on one LSI, duplication of circuits can be prevented, and the circuit scale can be reduced. In addition, when operating as a digital signal processor for performing high-speed digital signal processing, arithmetic performance is not impaired.

Secondly, in the first configuration, the data processing circuit has a selection means for selecting and outputting an output from the bypass means and an output from the pipeline register. I do.

Third, in the first or second configuration, the pipeline register is switched between the pipeline operation of the microprocessor and the pipeline operation of the digital signal processor. It is characterized in that a given clock frequency is switched.

A fourth aspect is a data processing device, wherein the data processing circuit has the first, second, or third configuration, and an address generation circuit for generating address information for the data processing circuit. And an address generation circuit that generates an address when the operation is switched to the pipeline operation of the digital signal processor and enables simultaneous execution of operation of an operation instruction and address calculation.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, a data processing device A according to the present invention includes an instruction fetch circuit A1, an instruction decoding / pipeline control circuit A2, an instruction execution circuit A3, a data memory 25, an address generation circuit 17, have.

Here, as shown in FIG. 1, the instruction fetch circuit A1 has a program counter, an instruction memory, and an instruction register. The instruction fetch circuit A1 reads out the instruction memory based on an address indicated by the program counter, and reads the instruction memory. It is stored in a register.

The instruction decoding / pipeline control circuit A2 decodes the contents of the instruction register to generate a read address of a register file, and generates an operation unit control signal for controlling the operation unit.

The instruction execution circuit A3 includes a register file 1, a pipeline register 2, a pipeline register 3, a pipeline register 6, a pipeline register 7, a pipeline register 22, a selector 4,
Selector 8, selector 9, selector 12, selector 1
3, a selector 14, a selector 15, a selector 16, a selector 23, and a computing unit 5. The instruction execution circuit A3 functions as the data processing circuit.

A bypass 107 is provided between the output terminal of the register file 1 and the input terminal of the selector 13 in parallel with the pipeline register 2. A bypass 108 is provided in parallel with the pipeline register 3. A bypass 109 is provided between the output terminal of the arithmetic unit 5 and the input terminal of the selector 15 in parallel with the pipeline register 6 and the pipeline register 10. A bypass 110 is provided between the bus 104 and the input terminal of the selector 16 in parallel with the pipeline register 11, and a pipeline register 22 is connected between the output terminal of the selector 4 and the input terminal of the selector 23. In parallel, a bypass 112 is provided. The bypass 107, the bypass 108, the bypass 109, the bypass 110, and the bypass 112 function as the bypass unit, and the selector 4, the selector 13, the selector 14, and the selector 1
5, the selector 16 and the selector 23 function as the selection output means.

The data memory 25 is connected to the instruction execution circuit A3. That is, the address bus 10
3 and connected to the selector 23 via the write data bus 111, and further connected to the selectors 8 and 9 via the read data bus 104.

The address generation circuit 17 includes an address register 18, an address register 19, and a selector 20.
And an address calculation circuit 21. The output of the address generation circuit 17 is input to the selector 14.

Here, the conventional data processing apparatus B
Is configured as shown in FIG. 3, and includes an instruction fetch circuit B1.
And an instruction decoding / pipeline control circuit B2 and an instruction execution circuit B3. Comparing the instruction execution circuits, the instruction execution circuit A3 of this embodiment is different from the conventional instruction execution circuit B3 in that the selector 13 and the selector 1
4, a selector 15, a selector 16, a selector 23, and a bypass 107, a bypass 108, a bypass 109, a bypass 110, and a bypass 112. Further, the data processing device A of the present embodiment It differs from the configuration shown in FIG. 3 in that it is provided separately.

Each of the bypasses is provided in parallel with the pipeline register so that a case where the data passes through the bypass and a case where the data is input to the pipeline register are obtained. A selector is provided at the output destination so that the output of the pipeline register can be selectively output. That is, the bypass 10
It is not necessary when the selector is already provided in the conventional configuration as in 8, 110, but if not, the selector is provided.

The operation of the data processing apparatus A having the above configuration will be described. First, a case where the data processing apparatus A performs a three-stage pipeline operation as a digital signal processor will be described. This three-stage pipeline operation is performed in three stages of fetch (F), decode (D), and execute (E).

First, in the fetch (F), in the instruction fetch circuit A1, the instruction memory is read based on the address indicated by the program counter, and the read data is stored in the instruction register.

Next, in the decode (D), the instruction decoding / pipeline control circuit A2 decodes the data stored in the instruction register, and sets the maximum two read addresses of the register file 1 and the read address of the register file 1. A maximum of two write addresses and a control signal such as an arithmetic unit control signal are generated.

Next, in the execution (E), control signals such as the read address of the register file 1, the write address of the register file 1, and the operation unit control signal generated by the decode (D) are used for instruction decoding / pipeline control. Output simultaneously by the circuit A2, (1) reading up to two data from the register file 1, (2) operation by the arithmetic unit 5,
(3) reading from or writing to the data memory 25; (4) address calculation by the address calculation circuit 21; (5) storing of operation results in the register file 1; and (6) memory to the register file 1. The read data is stored, and (7) the address calculation results are stored in the address registers 18 and 19.

The above processes (1) to (7) are
Not all operations are performed in the execution stage, and only some of them may be performed. For example, the above (1),
There are also cases where only the processes of (2) and (5) are performed, cases where only the processes of (3) and (6) are performed, and cases where only the processes of (4) and (7) are performed. .

Here, in order to realize the operation as a digital signal processor, the processing is performed by the following path as a data path.

That is, the above (1) register file 1
In the process of reading two operands from the register file, (2) the operation by the arithmetic unit 5, and (5) storing the operation result in the register file 1, one of the operands read from the register file 1 Is input directly to the arithmetic unit 5 through the bypass 107 without passing through. Similarly, another operand read from the register file 1 is input to the arithmetic unit 5 through the bypass 108 and the selector 4. The operation result output from the arithmetic unit 5 is output to the bypass 1 without passing through the pipeline registers 6 and 10.
09 and the selector 15 are stored in the register file 1.

When reading from the data memory 25 and storing (6) the memory read data in the register file 1 in the above-mentioned "(3) Reading from the data memory 25 or writing into the data memory 25",
The data read from the data memory 25 is stored in the register file 1 via the bypass 110 and the selector 16 without passing through the data bus 104 and the pipeline register 11.

When writing to the data memory 25 in "(3) Reading from or writing to the data memory 25", the data read from the register file includes the bypass 108, the selector 4, the bypass 112, and the selector 23 to the write data bus 111.

The above (4) address calculation circuit 21
(7) Address registers 18 and 1
In the operation of the digital signal processor, the operation and the address calculation must be performed in the same cycle in the storage of the address calculation result in the memory 9. Therefore, the memory address is not specified by the register of the register file 1 without performing the specification. , Address registers 18 and 19, and the address calculation circuit 21 provided in the address generation circuit 17 without using the arithmetic unit 5 in the address calculation.
Use The address generated by the address generation circuit 17 is selected by the selector 14 and the address bus 10
3 is output. The address becomes a read address in reading from the data memory 25 in “(3) Reading from or writing to the data memory 25”, and “3. Reading from the data memory 25 or reading from the data memory 25”. In the case of writing to the data memory 25 in "writing to 25", the address becomes a write address.

Next, the operation timing and data flow as a digital signal processor will be exemplified. First, an example program is shown below.

Instruction 1: A0 = 0; That is, 0 is assigned to the address register A0. Here, the address register 18 corresponds to the address register A0.

Instruction 2: R0 = 0; Here, 0 is assigned to the register R0 (see FIG. 1) in the register file 1. This is performed, for example, from the instruction decoding / pipeline control circuit A2.

Instruction 3: R1 = [A0 ++]; Here, the contents in the memory (data memory 25) indicated by the address register A0 are transferred to the register R1 in the register file 1 (see FIG. 1). Further, the contents of the address register A0 (address register 18) are incremented.

Instruction 4: rpt7; The next one instruction (here, instruction 5) is repeatedly executed a specified number of times (here, seven times).

Instruction 5: R0 + = R1; R1 = [A0 +
+]; The contents of the register R1 in the register file are added to the contents of the register R0 in the register file 1. This addition is performed by the arithmetic unit 5. Then, the result of the addition is assigned to the register R0 via the bypass 109, the selector 15, and the bus 105. The contents in the memory (data memory 25) indicated by the address register A0 are transferred to the register R1. Further, the contents of the address register A0 are incremented.

Instruction 6: R0 + = R1; register R
The contents of the register R1 are added to the contents of 0. This addition is performed by the arithmetic unit 5. Then, the result of this addition is substituted into the register R0.

Here, before entering the execution stage in the first execution of the instruction 5, the contents of the registers R0, R1, and the address register A0 are as follows. That is, the content of the register R0 is 0 substituted in the instruction 2. The content of register R1 is equal to the content of address 0 of the memory (data memory 25) loaded by instruction 3. The content of the address register A0 is 1 because 0 is substituted in the instruction 1 and then incremented in the instruction 3.

FIG. 2 shows a pipeline operation after the execution stage in the first processing of the instruction 5 described above. The timing of the execution stage in the first processing of the instruction 5 is the timing 1 in FIG. In this execution stage, as described above, (1) reading of two data from the register file 1, (2) operation by the arithmetic unit 5, (3) reading from or writing to the data memory 25, (4) address calculation by the address calculation circuit 21, (5) storage of operation results in the register file 1, (6) storage of memory read data in the register file 1, (7) address calculation to the address registers 18 and 19 The result is stored. Each process will be described in more detail below.

That is, (1) the register file 1
In reading the two data from the register, the contents of the registers R0 and R1 are read from the register file 1.
In the execution stage in the first processing of the instruction 1 and the timing 1 in FIG. 2, the content of R0 is 0,
The content of R1 is equal to the content of address 0 in the memory (data memory 25).

In the operation (2), the content of the register R0 is input to the arithmetic unit 5 through the bypass 107 and the selector 13. The contents of the register R1 are input to the arithmetic unit 5 through the bypass 108 and the selector 4. In the arithmetic unit 5, the input data is added. At timing 1 in FIG. 2, the output of the arithmetic unit 5 is the sum of 0 and the contents of the address 0 of the memory (data memory 25), that is, the memory (data memory 25).
Is equal to the contents of the address 0.

In the above (3) reading from the data memory 25 or reading from the data memory 25 in writing to the data memory 25, the contents of the address register A0 are selected by the selector 20 and the selector 14, and the contents of the address register A0 are selected. It is put on 103. At the timing 1 in FIG. 2, the content of the address register A0 is 1, and the content of the memory (data memory 25) indicated by the address register A0 is read and placed on the read data bus 104.

In the above (4) address calculation by the address calculation circuit 21, the contents of the address register A0 are selected by the selector 20 and input to the address calculation circuit 21. The address calculation circuit 21 adds 1 to the input and outputs the result to the address registers 18 and 19.

Also, in the above (5) storing the operation result in the register file 1, the output of the arithmetic unit 5 is stored in the register R0 of the register file 1 through the bypass 109 and the selector 15. In FIG. 2, the timing at which this processing is performed is when the timing 1 shifts to the timing 2.

In (6) storing the memory read data in the register file 1, the read data on the read data bus 104 is stored in the register R 1 through the bypass 110 and the selector 16. In FIG. 2, the timing at which this processing is performed is when the timing 1 shifts to the timing 2.

Further, (7) the address register 18,
In storing the address calculation result in the address register 19, the output of the address calculation circuit 21 is stored in the address register A0. In FIG. 2, the timing at which this processing is performed is when the timing 1 shifts to the timing 2.

The execution stage in the second and subsequent processing of instruction 5 occurs after timing 2 in FIG. 2, and processing per one word of memory data is performed every clock cycle.

Next, as described above, the data processing apparatus A of this embodiment has a configuration in which a bypass and a selector are added to the configuration of a conventional microprocessor that performs a five-stage pipeline operation. Obviously, a pipeline operation can be realized. The five-stage pipeline operation of the data processing device A according to the present embodiment will be described below.

In the instruction fetch (IF), in the instruction fetch circuit A1, the instruction memory is read based on the address indicated by the program counter, and the read data is stored in the instruction register.

Next, in the instruction decoding (ID), the instruction decoding / pipeline control circuit A2 decodes the instruction register to generate two read addresses of the register file. The register file 1 is read based on the read address and stored in the pipeline registers 2 and 3. The instruction decoding / pipeline control circuit A2 decodes the instruction register to generate a control signal such as an arithmetic unit control signal. In addition, this control signal is
After being delayed by a necessary cycle in the pipeline control circuit A2, it is input to the instruction execution circuit A3 to control the arithmetic unit 5 and the like.

Next, the operation in the case of the instruction execution (EX) will be described. In the following, three cases of an operation instruction, a load instruction, and a store instruction will be described separately. First, in the case of an operation instruction, the data in the pipeline register 2 is input to the arithmetic unit 5 through the selector 13, and the data in the pipeline register 3 is input to the arithmetic unit 5 through the selector 4. 5 is stored in the pipeline register 6.

In the case of a load instruction, the data of the pipeline register 2 is stored in the pipeline register 7 through the selector 13. The value of the pipeline register 7 becomes a memory read address.

In the case of a store instruction, data in pipeline register 2 is stored in pipeline register 7 through selector 13, and data in pipeline register 3 is stored in pipeline register 22 through selector 4. Is done. This pipeline register 7
Becomes the memory write address, and the value of the pipeline register 22 becomes the memory write data.

When post-increment or the like of a register used as a pointer is performed in a load instruction or a store instruction, data of the pipeline register 2 is further input to the arithmetic unit 5 through the selector 13 to perform an operation such as an increment. And store it in the pipeline register 6.

Next, the operation in the case of memory access (MA) will be described. In the following, three cases of an operation instruction, a load instruction, and a store instruction will be described separately. First,
In the case of an operation instruction, the data of the pipeline register 6 is stored in the pipeline register 10 through the selector 8.

In the case of a load instruction, the data of the pipeline register 7 is output to the address bus 103 through the selector 14. And the address bus 103
, The read data is output to the read data bus 104, and stored in the pipeline register 11 through the selector 9.

In the case of a store instruction, the data of the pipeline register 7 is output to the address bus 103 through the selector 14, and the data of the pipeline register 22 is output to the write data bus 111 through the selector 23.
Output to Based on the address on the address bus 103 and the data on the write data bus 111, writing to the data memory 25 is performed.

When post-increment or the like of a register used as a pointer is performed in a load instruction or a store instruction, data of the pipeline register 6 is further stored in the pipeline register 10 through the selector 8.

Next, the operation in the case of write back (WB) will be described. In the following, operation instructions, load instructions,
The case of a store instruction will be described. First, in the case of an operation instruction, data of the pipeline register 10 is written into the register file 1 through the selector 15. In the case of a load instruction, the pipeline register 11
Of the register file 1 through the selector 16
Write to.

In the case of performing a post-increment or the like of a register used as a pointer in a load instruction or a store instruction, data of the pipeline register 10 is further written into the register file 1 through the selector 15.

By switching between the three-stage pipeline operation and the five-stage pipeline operation, the pipeline operation of the microprocessor of the RISC architecture and the pipeline operation of the digital signal processor can be switched and operated. . Note that it is preferable that the clock frequency given to the pipeline register be switched between when switching to the pipeline operation of the microprocessor and when switching to the pipeline operation of the digital signal processor. That is, the clock frequency when switching to the pipeline operation of the microprocessor is set higher than the clock frequency when switching to the pipeline operation of the digital signal processor.

As described above, according to the data processing apparatus A of this embodiment, in particular, according to the instruction execution circuit A3, by providing bypass means in the data path of the microprocessor,
A pipeline operation of a digital signal processor can be realized, and when the functions of a microprocessor and a digital processor are mounted on one LSI, duplication of circuits can be prevented and the circuit size can be reduced. . Further, in the conventional case (conventional technology 1), if the operation result is to be stored in the memory immediately after the DSP operation, it is possible to avoid a problem that a contention occurs, a stall cycle occurs, and processing efficiency is reduced. Therefore, when the digital signal processor operates as a digital signal processor to perform high-speed digital signal processing, arithmetic performance is not impaired.

[0065]

According to the data processing circuit and the data processing apparatus having the same according to the present invention, the pipeline operation of the digital signal processor can be performed by providing the data path with bypass means provided in parallel with the pipeline register. In addition, when the functions of the microprocessor and the digital processor are mounted on one LSI, duplication of circuits can be prevented, and the circuit size can be reduced. In addition, when operating as a digital signal processor for performing high-speed digital signal processing, arithmetic performance is not impaired.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data processing device based on an embodiment of the present invention.

FIG. 2 is a time chart showing an operation of a data processing device according to a conventional embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional data processing device.

FIG. 4 is an explanatory diagram illustrating a stall cycle in the case of a conventional configuration.

[Explanation of symbols]

A Data processing device A1 Instruction fetch circuit A2 Instruction decoding / pipeline control circuit A3 Instruction execution circuit 1 Register file 2, 3, 6, 7, 10, 11, 22 Pipeline register 4, 8, 9, 12, 13, 14 , 15, 16, 20, 2,
Reference Signs List 3 selector 5 arithmetic unit 17 address generating circuit 18, 19 address register 21 address calculating circuit 25 data memory 107, 108, 109, 110, 112 bypass

Claims (4)

[Claims] 1. A data processing circuit having a pipeline register and performing pipeline processing, comprising one or a plurality of bypass means provided on a data path, the data processing circuit passing through the bypass as a data path. Data having a bypass means capable of obtaining a case in which the operation is performed and a case in which the operation reaches the pipeline register, and enabling a switching operation between a pipeline operation of a microprocessor and a pipeline operation of a digital signal processor. Processing circuit. 2. The data processing circuit according to claim 1, wherein said data processing circuit has a selecting means for selecting and outputting an output from said bypass means and an output of said pipeline register. 3. The clock frequency given to a pipeline register is switched between when switching to pipeline operation of a microprocessor and when switching to pipeline operation of a digital signal processor. 3. The data processing circuit according to 2. 4. A data processing device, comprising: the data processing circuit according to claim 1 or 2; and an address generation circuit for generating address information for the data processing circuit, wherein A data processing device, comprising: an address generation circuit that generates an address when switching to a pipeline operation of a signal processor and enables simultaneous execution of operation of an operation instruction and address calculation.