JP2004302856A - Integrated circuit device and data configuring device for device thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase use efficiency of a reconfigurable circuit. <P>SOLUTION: Two mul commands and one add command corresponding to a program is loaded, and a sub command, div command, and add command corresponding to another program are loaded in a vacant region. A plurality of functional circuits are loaded in one ALU array. When the program is loaded, the use state of ALU is monitored and recorded. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an integrated circuit technology, and particularly to a reconfigurable circuit, and an integrated circuit device and a data conversion device that can use the same.
[0002]
[Prior art]
Recently, wireless communications such as mobile phones, GPS, and VICS have become widespread, and the types of wireless devices have been increasing. If all of these radios or their functions are implemented by hardware, the cost and the mounting area increase. Therefore, there is a concept of a "software radio" in which a circuit having general-purpose capability is mounted as hardware, and various functions are realized by switching software to be loaded on the circuit.
[0003]
As a circuit for realizing the software defined radio, there are an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor). Patent Document 1 proposes a method for reusing a circuit configuration by dynamically reconfiguring an FPGA. A type of circuit that can be dynamically changed is also referred to as a reconfigurable circuit.
[0004]
[Patent Document 1]
Japanese Patent Application Laid-Open No. H10-256383 (Full text, Fig. 1-4)
[0005]
[Problems to be solved by the invention]
Various logic can be realized by using a look-up table (LUT) for storing a truth table of a logic circuit based on an FPGA. However, in general, a unit of a logic element is small, and a desired function is realized. Requires many LUTs and wiring resources. As a result, as compared with a normal LSI, the mounting area is generally large and the cost is high. Also, the program time for rewriting the circuit is long to some extent, and is often not suitable for real-time function switching.
[0006]
SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has as its object to provide a reconfigurable circuit advantageous in terms of cost, rewriting speed, circuit use efficiency, power consumption, and the like, an integrated circuit device using the same, and data setting. It is to provide a device.
[0007]
[Means for Solving the Problems]
One embodiment of the present invention relates to an integrated circuit device, which is used to set an array of logic circuits each of which can selectively execute a plurality of arithmetic logic functions and a connection relationship between the functions of each logic circuit and the logic circuits in the array. And a setting unit that reads the setting data from the storage unit and loads the setting data into the array, wherein the setting data is an area that becomes unused when the first functional circuit is loaded into the array. To load the second functional circuit.
[0008]
The setting unit may be configured by dedicated hardware, for example, in addition to a combination of programs of a CPU (central processing unit) included in the device. The array is configured by arranging, for example, 8 × 8 logic circuits. As a result of loading a plurality of functions into an array, ie, the smallest unit of a functional configuration, the effective utilization of the array is increased.
[0009]
The setting data may be described so that the second functional circuit is arranged in a row near the input stage in an unused area. Alternatively, it may be described that the second functional circuit is packed and arranged in a column close to the logic circuit in which the first functional circuit is loaded. In either case, placing such a rule to place the second functional circuit makes it easier to accommodate that circuit in the array. Further, there is still room for mounting a third functional circuit.
[0010]
Another embodiment of the present invention also relates to an integrated circuit device, each having an array of m rows and n columns of a logic circuit capable of selectively performing a plurality of arithmetic logic functions, wherein each of the m rows and the n columns includes a first row to a first column. Loading and arranging a functional circuit, and loading and arranging a second functional circuit from i-th row and j-th column (1 ≦ i ≦ m, 1 ≦ j ≦ n) in an area which is unused in the array as a result; The second functional circuit is loaded and arranged so that one of the aforementioned i and j is minimized.
[0011]
Another embodiment of the present invention also relates to an integrated circuit device, each having an array of m rows and n columns of a logic circuit capable of selectively performing a plurality of arithmetic logic functions, wherein each of the m rows and the n columns includes a first row to a first column. A function circuit is loaded and arranged, and a second function circuit is loaded and arranged using a row and a column with a small row number as much as possible in an area unused in the array. It is.
[0012]
In these configurations, the second functional circuit may be optimally arranged using a through node as appropriate. The term “optimized placement” refers to a case where placement is only possible, a case where the total number of logic circuits used at the time of placement is minimized, and a case where there is room to place a third functional circuit. An arrangement that is useful in a sense. "Through node" refers to NOP (No Operation), that is, a node that does nothing. In practice, a wiring that simply connects an input and an output is selected inside a logic circuit, or the logic circuit is subjected to an identity mapping operation, that is, multiplication. If the circuit is set to a circuit that multiplies 1 as an adder or adds 0 as an adder, this logic circuit becomes a through node.
[0013]
Still another embodiment of the present invention relates to a data setting device. This device may be, for example, an external device that provides setting data to the above-described integrated circuit device, and may include a compiler that converts a program written in C language or another high-level language into setting data. The setting data corresponds to, for example, a data flow graph.
[0014]
The apparatus includes a control unit that generates setting data for loading a desired function into an integrated circuit device that includes an array of logic circuits each capable of selectively executing a plurality of arithmetic logic functions, and loading the setting data. And a monitoring unit that monitors an area used in the array when the operation is completed. The control unit and possibly the monitoring unit comprise a compiler or a combination thereof with a CPU or any other hardware or software. If the control unit receives the result of monitoring by the monitoring unit and generates setting data for loading another function in an unused area in the array, the use efficiency of the array is improved.
[0015]
The integrated circuit device and the data setting device described above may be a single device. In this case, for example, the former setting unit and the latter control unit can be configured by a single CPU and a single program. A part of the former and a part of the latter may be configured as a single device.
[0016]
In any of the above cases, the array of logic circuits is an array in which a plurality of rows of logic circuits arranged in the horizontal direction are combined in the vertical direction, and there is no connection for connection between the logic circuits in the horizontal direction. May be provided with a connection for connection between the output of the logic circuit row of (1) and the input of the logic circuit row of the next stage.
[0017]
In addition, any combination of the above-described components, and the expression of the present invention expressed as a method, an apparatus, a system, or a computer program are also effective as embodiments of the present invention.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
The embodiment relates to a reconfigurable circuit having an ALU (Arithmetic Logic Unit) array as a basic element. In this type of circuit, one ALU constitutes one logical unit, and this logical unit can selectively execute a plurality of arithmetic operations. Therefore, the circuit configuration is simple, and a data flow graph described later can be directly displayed. Configuration time is saved because mapping is possible. Mapping refers to loading an instruction set of a program to be executed in the reconfigurable circuit and a connection data set required in the reconfigurable circuit to realize the program into an ALU array (hereinafter simply referred to as “array”). Setting. Hereinafter, the configuration is defined.
[0019]
1. Array: ALUs are arranged in an m × n matrix.
2. Reconfigurable circuit: A plurality of arrays are built-in, but one array will be noted in the following description (hereinafter, this array is also referred to as an “array of interest”).
[0020]
An ALU is a "logical unit", but usually one ALU implements one function. Thus, the array is a “functional unit”. The size of the array, that is, the setting of the above-mentioned values of m and n is made by empirical rules based on the assumption of the function to be realized. If the array is too small, one function cannot be realized. On the other hand, if the array is too large, when one function is loaded, unused ALUs increase and utilization efficiency is poor.
[0021]
From such a viewpoint, a feature of the embodiment is that a plurality of functions are implemented in an array which is a functional unit. That is, first, the first functional circuit is loaded, and if there is an unused area, the second functional circuit is loaded to effectively use the array. Of course, it is effective to load the third and lower functional circuits in the remaining area.
[0022]
FIG. 1 shows a configuration of an integrated circuit device 10 and a data setting device 24 according to the embodiment. The data setting device 24 creates data for setting the circuit configuration of the integrated circuit device 10 and supplies the data to the integrated circuit device 10.
[0023]
The integrated circuit device 10 includes a reconfigurable circuit 12, a setting data storage unit 16 for storing setting data 17 for reconfiguring the reconfigurable circuit 12, and a setting for loading the setting data 17 into the reconfigurable circuit 12. Unit 14. "Reconstruction" refers to making a circuit for realizing a desired function. In practice, the loading of the setting data 17 corresponds to this.
[0024]
The data setting device 24 includes a control unit 18, a compiling unit 20, a program storage unit 22, and a monitoring unit 23 that monitors the use status of the ALU in the target array.
The monitoring unit 23 monitors the setting data 17 at any of several possible timings, such as when the setting data 17 is transmitted from the control unit 18 or when the setting data 17 is set by the setting unit 14. As a result, the ALU used in the target array is always grasped, and the unused ALU is identified and transmitted to the control unit 18. The control unit 18 determines whether the second functional circuit can be loaded into the array of interest based on the usage status of the ALU, and generates the setting data 17 to load the array if possible. If it is impossible, the setting data 17 is changed so that the second functional circuit is mapped to another array.
[0025]
The program storage unit 22 of the data setting device 24 holds various programs 19 to be executed by the integrated circuit device 10. The compiling unit 20 compiles the program 19 stored in the program storage unit 22, converts the program 19 into a data flow graph 21, and stores the data flow graph 21 in the program storage unit 22. As will be described later, the data flow graph 21 shows the flow of calculation of input variables and constants in a graph structure.
[0026]
The control unit 18 converts the data flow graph 21 into setting data 17 for mapping to the circuit configuration of the reconfigurable circuit 12, and supplies the setting data 17 to the setting unit 14 of the integrated circuit device 10. At this time, information on the unused ALU is acquired from the monitoring unit 23, and the setting data 17 is described so that a plurality of functional circuits are loaded into the array of interest as much as possible. The setting data 17 is stored in the setting data storage unit 16.
[0027]
The setting unit 14 reconfigures the reconfigurable circuit 12 by reading the setting data 17 from the setting data storage unit 16 and loading the setting data 17 into the reconfigurable circuit 12. The reconfigured reconfigurable circuit 12 performs processing based on the loaded setting data 17.
[0028]
FIG. 2 shows the configuration of the target array 12a. The target array 12a includes a data input unit 40 for loading the setting data 17 and an area 42 in which the rows of the ALU are arranged. The connection switch 44 and the connection 30 provided in each row provide the data of the ALU of the preceding row. The output and the input of the following ALU can be arbitrarily connected by setting. Although the connection connection 30 is selected by the connection switch 44, hereinafter, it is abbreviated as "setting by the connection connection 30". Each ALU includes, for example, an adder, a subtractor, a multiplier, and the like.
[0029]
As shown in the figure, Y ALUs are arranged in the horizontal direction and X ALUs are arranged in the vertical direction. Input variables and constants are input to ALU11, ALU12,... , A predetermined calculation is performed according to the setting. The output of the operation result is input to ALU21, ALU22,..., ALU2Y in the second row according to the connection set in the connection connection 30 in the first row. The connection connection 30 in the first row is configured such that an arbitrary connection relationship between the output of the ALU group in the first row and the input of the ALU group in the second row can be realized, and a specific connection is set by setting. Becomes effective. Hereinafter, the configuration is the same up to the connection connection 30 in the (X-1) th row, and the ALU group in the Xth row, which is the last row, outputs the final result of the operation. Each ALU has a through path (not shown) for directly outputting an input in order to execute a mov operation described later, and by selecting this, the ALU becomes a through node.
[0030]
The setting data 17 for mapping the data flow graph 21 to the array of interest 12a includes information for selecting an operation of each ALU, information for selecting a connection connection between ALU rows, and variables input to the ALU group in the first row. Contains the value of the constant.
[0031]
Now, consider the following program to be executed.
int main (int a, int b) ｛
int x = 2 * a;
int x = 5 * b;
return (x + y);
｝
FIG. 3 shows a data flow graph corresponding to the above program. In the figure, constants, variables and operators are circled, mul indicates multiplication, and add indicates addition. If this is directly mapped to the reconfigurable circuit 12, the state shown in FIG. 4 is obtained. The above is the basis of the embodiment.
[0032]
Hereinafter, a method of loading two or more functional circuits will be described. Now, as shown in FIG. 5, the ALU included in the array of 2 rows and 4 columns is represented by coordinates (i, j). However, i = 1,2 and j = 1,2,3,4. 6 and 7 respectively show coordinates of the setting in FIG. Here, for example, two muls and one add are respectively set to (1, 1) (1, 2) (2, 1), and both outputs of (1, 1) and (1, 2) are (2, 1). It is connected to the input of 1).
[0033]
The monitoring unit 23 checks the ALU for which an instruction has already been set, that is, the used ALU, and records the result in its own internal memory (not shown). FIG. 8 shows the processing for that. Here, the array has Z rows and W columns, and the internal variables i and j are used as row and column counters, respectively. As shown in the figure, first, an initial value "1" is set in counters i and j (S10), i and Z are compared (S12), and if i is equal to or less than Z (Y in S12), a row to be checked still remains. The process proceeds to S14. In S14, j and W are compared, and if j is equal to or less than W (Y in S14), the process proceeds to S16 because there is still a row.
[0034]
In S16, it is checked whether the ALU of (i, j) is unset, that is, whether it is vacant. If it is vacant (Y of S16), "the vacant number of the i-th row is W-j + 1 and the used number is j-1" Is output (S22), i is incremented and j is returned to "1" (S24), and the process returns to S12 to investigate the next line. If the (i, j) ALU has been used in S16, the process proceeds to S18, j is incremented, and the process returns to S14.
[0035]
If j has already exceeded the value of W in S14 (N in S14), there is no free space in that row, so that "the number of free rows in the i row is zero and the number of used rows is W" is output (S20), and S24 is executed. Proceed to.
[0036]
If i has already exceeded Z in S12 (N in S12), the process is terminated because all rows have been examined. With the above processing, the monitoring unit 23 can record the number of empty lines in each row. Since the number of vacancies is known, the monitoring unit 23 can consequently know whether the (i, j) ALU is vacant or used for any i, j.
[0037]
A second program, that is, a second functional circuit is set in this array. This program is as follows.
int main (int c, int d) ｛
int x = 3-c;
int y = d / 8;
return (x + y);
｝
FIG. 9 shows a data flow graph of this program, and FIG. 10 shows a setting in the case where only this program is temporarily loaded into an array in a coordinate display. However, since the first program has already been loaded, an instruction is set to a vacant ALU when loading the second program.
[0038]
FIG. 11 shows a process in which the control unit 18 determines whether the second program can be loaded. Here, N is the number of lines required for setting the second program. First, the counter i is set to "1" (S30), and i and N are compared (S32). If i is less than or equal to N, the setting is not completed, so the process proceeds to S34, and it is determined whether or not all the instructions necessary for realizing the second program can be accommodated in the vacant ALU in the i-th row. This is determined based on the number of free ALUs. If it can be accommodated (Y in S34), i is incremented by reflecting it in the setting data 17 (S36), the number of free spaces is reduced by the number of ALUs newly set in the row (S38), and the process returns to S32.
[0039]
In S34, when it is impossible to store the instruction in the i-th row, that is, when the number of instructions to be stored exceeds the number of available spaces (N in S34), error processing (S40) is executed to execute the processing. Finish. The error processing (S40) includes loading of the second program into an array other than this array. As another process, there is a process of FIG. 14 described later. On the other hand, in step S32, if the value of i has already exceeded N, it means that the setting of all the instructions has been completed, and the process is similarly ended.
[0040]
12 and 13 show a state in which the second program is set in relation to each command and the coordinate display of the ALU. The sub uses the vacant ALU like (1, 3). FIG. 13 shows the state of the array in a state where the first and second programs are mounted.
[0041]
FIG. 14 shows an example of the above-described error processing. First, an outline of the process will be given, and an actual example will be given later.
As shown in FIG. 14, first, "1" is set to counters i, j, and k (S50). Here, k is the k-th instruction constituting a program to be newly loaded, and it is assumed that the program includes all L instructions.
[0042]
When k is equal to or less than L (S52), i is equal to or less than Z (S54), and j is equal to or less than W (S56), the control unit 18 checks whether the ALU of (i, j) is empty (S58). If free, it is checked whether the k-th instruction can be set in the ALU (S60). As will be described later, even if the ALU is empty, the ALU may not be usable depending on the number of input nodes and the number of output nodes required for this instruction. If the result of the inspection indicates that it can be used (Y in S60), the value is reflected in the setting data 17, k is incremented (S62), j is incremented (S64), and the process returns to S52. If it is determined in S60 that the ALU cannot be used because of the k-th instruction (N in S60), the process skips S62 and proceeds to S64. If (i, j) is found not to be empty in S58, S60 and S62 are skipped and the process proceeds to S64.
[0043]
If j already exceeds W in S56, the inspection of that row has been completed (N of S56), so that j is returned to “1” to inspect the next row, and i is incremented (S66). It returns to S54.
[0044]
If i has already exceeded Z in S54, since the setting of this program has not been completed, error processing (S68) is executed and the processing ends. On the other hand, if k has already exceeded L in S52, the setting of this program has been completed, and the process ends normally. The error processing in S68 includes loading this program into another array. The above is the outline of the processing.
[0045]
15 and subsequent figures, the processes of FIGS. 11 and 14 are collectively shown by actual examples. Here, when the first data flow graph, the second data flow graph,... Corresponding to a plurality of programs are set, the data flow graph is appropriately modified according to the empty area of the array. Set the data flow graph according to the following procedure.
[0046]
(1) Set the first data flow graph.
(2) Information about an unset ALU is acquired from the setting information of the first data flow graph, and if the second data flow graph can be set in the unset ALU, the setting is performed as it is (FIG. 11).
(3) If the second data flow graph does not fit in the unset ALU, the second data flow graph is modified and set (in the case of FIG. 14).
(4) If the second data flow graph does not fit in any way, the setting process is performed on the remaining data flow graphs (error processing in FIG. 14).
(5) The data flow graph that could not be set finally is set in another ALU array (the same error processing).
[0047]
FIGS. 15, 16, and 17 schematically show three data flow graphs to be set. Here, the number indicates the number of the node, and a predetermined logical operation is assigned to each node. The array is 8 × 8.
[0048]
First, since the array is not set in the initial state, the first data flow graph can be set as it is. FIG. 18 shows this state. FIG. 19 shows the vacant state of the ALU at this time.
[0049]
Next, a second data flow graph is set. It can be seen from the empty state in FIG. 19 and the required number of ALUs in FIG. 16 that the second data flow graph can be set as it is. FIG. 20 shows a state where the second data flow graph has been set in the array. FIG. 21 shows the ALU idle state at this time.
[0050]
Finally, a third data flow graph is set. By comparing the required number of ALUs found from FIG. 17 with the empty state found from FIG. 19, it can be seen that the third data flow graph cannot be set in the array in the connected state as it is. It is checked whether setting can be made by changing the connection state of the third data flow graph. The rules for setting nodes in the array are as follows.
[0051]
(1) Set the line as high as possible (the line where i is small).
(2) Set the column as far to the left as possible (the column where j is small).
(3) There is a problem such as a shortage of vacant ALUs, and when deforming the data flow graph, through nodes are added as appropriate.
[0052]
In order to make the position of the unused ALU shown in FIG. 19 easy to understand, the coordinate display described above is used. When inspected from the top row, (8, 1) can be set only to nodes having 0 input nodes and 1 output nodes. FIG. 22 shows the number of input nodes and the number of output nodes of each node constituting the third data flow graph. From FIG. 22, the node 24 is set to (8, 1). FIG. 23 shows the setting state at this time for the upper three rows.
[0053]
Next, the output node of the set node 24 is checked. The node 24 has a node 28 as an output node, but since the node 28 has two input nodes, it cannot be set to (8, 2). Therefore, it is set further down. Here, since it is left-aligned, the node 28 is temporarily set to (6, 3). However, even in this case, since two input nodes of the node 28 cannot be set, (4, 4) which is further down and satisfies the left alignment is set. Since the nodes 24 and 28 are connected, they are connected by setting through nodes ("N" in the figure) at (6, 3) and (8, 2). FIG. 24 shows the setting state at this time.
[0054]
Subsequently, a node 25 which is an input node of the node 28 is set. Since the node 25 may be set in the upper row of the node 28, it is set to (7, 3). Thus, the setting of the input node of the node 28 is completed. FIG. 25 shows the setting state at this time.
[0055]
Next, the output node of the node 28 is only the node 31. As described above, the node 31 is set, and the unset node 29 among the input nodes of the node 31 is set to (5, 4). Further, the unset node 26 among the input nodes of the node 29 is set to (8, 4). FIG. 26 shows the setting state at this time.
[0056]
Subsequently, the output node 33 of the node 31 is set. Since the number of input nodes of the node 33 is 2, the setting is made at (1, 6), and the setting of the input node is set as described above. However, the setting fails because there is no ALU that can be set for the input node 27 of the node 30. Therefore, the settings after the node 33 are cleared. FIG. 27 shows the setting state before clearing.
[0057]
In order to set the node 27, a through node is inserted at (1, 6), and the setting position of the node 33 is lowered by one line to create a space. The node 33 sets (1, 7). With the above procedure, the setting of the third data flow graph is completed as shown in FIG.
[0058]
The present invention has been described based on the embodiments. It should be understood by those skilled in the art that the embodiments are exemplifications, and that various modifications can be made to the combination of each component and each processing process, and that such modifications are also within the scope of the present invention. . The following is an example.
[0059]
A timer (not shown) may be provided in the data setting device 24 in FIG. 1 and the like, and the function of the control unit 18 to load the reconfigurable circuit 12 according to the timer output may be switched. In that case, a plurality of functions can be realized by sequentially switching. This method is effective when the integrated circuit device 10 performs various functions in a time sharing manner.
[0060]
The integrated circuit device 10 of the embodiment can be applied to, for example, a software defined radio. In this case, the FM radio, the car navigation function, the television receiving function, the voice call function, and the like may be loaded into the reconfigurable circuit 12 as appropriate.
[0061]
【The invention's effect】
According to the present invention, it is possible to provide an integrated circuit device improved in utilization efficiency and a data setting device for setting data in the device. Also, when implementing the same function, the circuit scale and power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an integrated circuit device and a data setting device according to an embodiment.
FIG. 2 is a configuration diagram of an ALU array portion in the reconfigurable circuit of FIG. 1;
FIG. 3 is a diagram showing a data flow graph representing a process of a certain program.
FIG. 4 is a configuration diagram of an ALU array mapped according to the data flow graph of FIG. 3;
FIG. 5 is a diagram showing coordinates of a 2 × 4 ALU array.
FIG. 6 is a diagram showing a correspondence between an instruction set and an ALU.
FIG. 7 is a diagram showing the correspondence between instruction sets and ALUs.
FIG. 8 is a flowchart illustrating a procedure in which a monitoring unit checks an ALU for an empty state;
FIG. 9 is a diagram showing a data flow graph of a second program to be loaded into the ALU array.
FIG. 10 is a diagram showing a correspondence between an instruction set of the second program and an ALU when the first program is not considered;
FIG. 11 is a flowchart illustrating a procedure for determining whether a second program can be loaded into a certain ALU array.
FIG. 12 is a diagram illustrating a correspondence between an instruction set of the second program and an ALU when the first program is considered.
FIG. 13 is a diagram showing a state where the first and second programs are loaded into the ALU array.
14 is a flowchart showing a procedure for determining whether or not loading is possible when loading a second or lower program into the ALU array, and particularly showing an example of error processing in FIG. 11;
FIG. 15 is a diagram showing ALUs to be used in the first data flow graph by numbering;
FIG. 16 is a diagram showing ALUs to be used in the second data flow graph by numbering;
FIG. 17 is a diagram showing ALUs to be used in the third data flow graph by numbering;
FIG. 18 is a diagram showing a state in which a first data flow graph is loaded into an 8 × 8 ALU array.
FIG. 19 is a diagram illustrating the use state of the ALU at the time of FIG. 18;
FIG. 20 is a diagram showing a state in which a second data flow graph is loaded into an 8 × 8 ALU array.
FIG. 21 is a diagram illustrating the use state of the ALU at the time of FIG. 20;
FIG. 22 is a diagram showing the number of input and output nodes of the ALU required for the third data flow graph.
FIG. 23 is a diagram showing a state where a node “24” of the third data flow graph is set.
FIG. 24 is a diagram showing a state where a node “28” of the third data flow graph is set.
FIG. 25 is a diagram showing a state where a node “25” of the third data flow graph is set.
FIG. 26 is a diagram showing a state where nodes “26”, “29”, and “31” of the third data flow graph are set.
FIG. 27 is a diagram showing a state in which the node “27” of the third data flow graph cannot be set, and the setting is temporarily failed.
28 is a diagram showing a state in which the setting of the third data flow graph is completed after the failure in FIG. 28 is resolved.
[Explanation of symbols]
Reference Signs List 10 integrated circuit device, 12 reconfigurable circuit, 12a ALU array, 14 setting unit, 18 control unit, 20 compiling unit, 21 data flow graph, 23 monitoring unit, 24 data setting device.

Claims (9)

An array of logic circuits, each of which can selectively perform a plurality of arithmetic logic functions;
A storage unit that stores setting data for setting a function of each logic circuit in the array and a connection relationship between the logic circuits,
A setting unit that reads the setting data from the storage unit and loads the setting data into the array;
Wherein the setting data is described so as to load a second functional circuit into an area which is not used when the first functional circuit is loaded onto the array. 2. The apparatus according to claim 1, wherein the setting data is described so as to arrange the second functional circuit in a row near an input stage in the unused area. Circuit device. 3. The device according to claim 1, wherein the setting data is obtained by packing the second function circuit in a column close to a logic circuit in which the first function circuit is loaded in the unused area. 4. An integrated circuit device that is described to be placed. Each has an array of m rows and n columns of logic circuits capable of selectively executing a plurality of arithmetic logic functions, and loads and arranges the first functional circuit from one row and one column of the array, and as a result, In the unused area of the array, the second functional circuit is loaded and arranged from the i-th row and the j-th column (1 ≦ i ≦ m, 1 ≦ j ≦ n), and the second functional circuit is arranged so that the value of i is minimized. An integrated circuit device, wherein the second functional circuit is loaded and arranged. Each has an array of m rows and n columns of logic circuits capable of selectively executing a plurality of arithmetic logic functions, and loads and arranges the first functional circuit from one row and one column of the array, and as a result, In the unused area of the array, the second functional circuit is loaded and arranged from the i-th row and the j-th column (1 ≦ i ≦ m, 1 ≦ j ≦ n), and the second functional circuit is arranged so that the value of j is minimized. An integrated circuit device, wherein the second functional circuit is loaded and arranged. Each has an array of m rows and n columns of logic circuits capable of selectively executing a plurality of arithmetic logic functions, and loads and arranges the first functional circuit from one row and one column of the array, and as a result, An integrated circuit device wherein a second functional circuit is loaded and arranged using a row having a small row number and a column having a small column number as much as possible in an unused area of the array. 7. The integrated circuit device according to claim 4, wherein the second functional circuit is optimally arranged by using a through node as appropriate. A control unit for generating setting data for loading a desired function into an integrated circuit device including an array of logic circuits each capable of selectively executing a plurality of arithmetic logic functions;
When the configuration data is loaded, a monitoring unit that monitors an area used in the array,
A data setting device comprising: 9. The apparatus according to claim 8, wherein the control unit receives a result of monitoring by the monitoring unit and generates setting data for loading another function into an unused area in the array. Data setting device.

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