JP2715493B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device, in which a data storage unit has first to third planes, The present invention relates to a semiconductor memory device used for a purpose of performing a data operation of an arbitrary one address of two planes and writing an operation result to an arbitrary one address of a third plane.

[Conventional technology]

Conventionally, this type of semiconductor memory device has a configuration as shown in FIG. 6, which includes an address input buffer 9, an address selector 10, a control circuit 8, a column decoder 2, a row decoder 4,
Sense amplifier 3, first plane 1-1, second plane 1-2,
A memory cell array divided into three sets of third planes 1-3,
The semiconductor memory device includes a selection circuit 5 and a data input / output buffer 7.
An operation of calculating data of an arbitrary one address of the plane and data of an arbitrary one address of the second plane and writing the operation result to an arbitrary address of the third plane has been performed.

The control circuit 8 controls the row address strobe signal ▲
▼, a column address strobe signal ▲ ▼, a write control signal WE, a read control signal ▲ ▼ as input signals, an address input buffer control signal a for controlling the input of the address data Ai, and an address selector control for controlling the address selector 10. A signal b, a row decoder control signal c for controlling the row decoder 4 to select only one word line from the memory cell array by address data, and an arbitrary switch 1 in the selection circuit 5 for controlling the column decoder 2. A column decoder control signal d for turning on one of them, a sense amplifier control signal e for controlling the sense amplifier 3 for determining memory cell contents, and a data input / output buffer control signal f for controlling data input / output as output signals. I have.

Next, an operation is performed between the data stored at any one address of the first plane and the data stored at any one address of the second plane, and the operation result is written to any one address of the third plane. The operation in this case will be described with reference to the timing chart of FIG.

First, in the first memory cycle, arbitrary one address data (hereinafter, referred to as address data 01) supplied to the address data input terminal Ai of the first plane is fetched, and the cell data (hereinafter, referred to as 001) selected by 01 is taken into the first memory cycle. The data is taken out of the plane 1-1, passed through the internal data input / output bus h and the data input / output buffer 7, placed on the external system bus i, and transmitted to the arithmetic circuit 6. That is, a read cycle operation is performed.

Subsequently, in the same manner, in the second memory cycle, any one address data of the second plane (hereinafter, address data)
02), and the selected cell data (hereinafter referred to as data 002) is placed on an external system bus and transmitted to the arithmetic circuit. That is, a read cycle operation is performed. Subsequently, in the same manner, in the third memory cycle, arbitrary one address data (hereinafter, referred to as address data 03) of the third plane is fetched, and data (hereinafter, data 003) obtained by calculating data 001 and data 002 by the arithmetic circuit is obtained. Is written to the address specified by the address data 03 of the semiconductor memory device. That is, a write cycle operation is performed.

Summarizing the above, the first read cycle requires two memory cycles and one write cycle for a total of three memory cycles.
An arithmetic circuit performs an operation on data stored at any one address of the plane and data stored at any one address of the second plane, and performs an operation of writing the operation result to any one address of the third plane. .

[Problems to be solved by the invention]

In the above-described conventional semiconductor memory device, unless an arithmetic circuit is provided externally, the operation of the data of the first plane and the data of the second plane and the operation of writing the result to the third plane cannot be performed. for,
Since three memory cycles are required and the system bus is monopolized during that time, there is a disadvantage in that the speed of a system using such a semiconductor memory device is impaired.

[Means for solving the problem]

A semiconductor memory device according to the present invention includes a data storage unit including a first plane, a second plane, and a third plane, which are sets of a plurality of memory cells, and an internal unit that inputs and outputs data for each plane of the data storage unit. A data input / output bus,
A semiconductor memory device including an arithmetic circuit connected to the internal data input / output bus, wherein the control circuit generates a set of control signals for controlling the operation of the semiconductor memory device;
Means for generating an internal address latch signal of three cycles in one memory cycle in response to an operation mode setting signal supplied from the outside; and a means for generating a first cycle, an intermediate cycle and a last cycle of the three cycles. Means for controlling supply of data of the first plane to the arithmetic circuit, supply of data of the second plane to the arithmetic circuit, and storage of arithmetic result data of the arithmetic circuit in the third plane. It is provided.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of a first embodiment of the present invention.

In this embodiment, a first plane 101-1, a second plane 101-2, and a third plane 101, which are sets of a plurality of memory cells, are used.
-3, a data storage unit (memory cell), an internal data input / output bus 1h for inputting / outputting data for each plane of the data storage unit, and an arithmetic circuit 106 (addition) connected to the internal data input / output bus 1h. And a control circuit 108 for generating a set of control signals (1a to 1g) for controlling the operation of the semiconductor memory device. Means for generating an internal address latch signal of three cycles in one memory cycle upon receipt thereof;
Supply of data for one address stored in the first plane 101-1 to the arithmetic circuit 1g within the respective periods of the intermediate cycle and the last cycle, the second plane 101-2
Of data for one address stored in the arithmetic circuit 1g and the third plane of the operation result data of the arithmetic circuit 1g
Means for controlling storage in the selected one address 101-3.

FIG. 3 is a circuit diagram showing an example of an internal address latch signal ▲ ▼ generating circuit, which generates a 3-cycle pulse signal from the operation mode setting signal MODE, and constitutes a part of the control circuit 108.

 Next, the operation of this embodiment will be described.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

If the operation mode setting signal MODE at the time t1 is at a high level, the control circuit 108 determines that the operation is to be performed, and generates an internal address latch signal ▲ ▼ falling three times continuously in one memory cycle inside the control circuit. I do.

The control circuit changes the address data 01 of the first plane at the falling edge of the first signal and outputs the address data 01 of the second time.
Address data 02 of second plane at falling edge of signal
Is controlled to take in the address data 03 of the third plane at the third falling edge of the signal.

The data 001 stored in the first plane selected by the address data 01 and the data 002 stored in the second plane selected by the address data 02 are transmitted to the arithmetic circuit via the internal data bus and added. Is done. The data 003 resulting from the addition is written to the memory cell array of the third plane specified by the address data 03 via the internal data bus.

The type of the arithmetic circuit is not limited to the adder circuit, but may be any of a subtractor circuit, a multiplying circuit, and the like.

FIG. 4 is a block diagram of a second embodiment of the present invention, and FIG. 5 is a timing chart for explaining the operation of the second embodiment.

In this embodiment, the operation mode setting signal MODEi (i = 1,
2,...), And thus a plurality of types of arithmetic circuits 206 are also provided, and there is an advantage that an arithmetic method can be arbitrarily selected and designated from among the multiple arithmetic methods.

〔The invention's effect〕

As described above, according to the present invention, an arithmetic circuit is provided in a semiconductor memory device, and means for generating an internal address latch signal of three cycles in one memory cycle based on an arithmetic mode setting signal is added to a control circuit. In one memory cycle, data of any one address of the first plane and data of any one address of the second plane can be operated by the arithmetic circuit, and the operation result can be written to any one address of the third plane. Since the internal data input / output bus is used for such data processing, monopolization of the external system bus can be prevented, and the system can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention, and FIG. 3 is a first embodiment of the present invention. FIG. 4 is a block diagram of a second embodiment of the present invention, FIG. 5 is a timing chart for explaining the operation of the second embodiment of the present invention, FIG. FIG. 6 is a conventional block diagram, and FIG. 7 is a timing chart for explaining the operation of the conventional example. 1-1, 101-1, 201-1 ... first plane, 1-2, 101-
2, 201-2: second plane, 1-3, 101-3, 201-3 ...
… The third plane, 2,102,202 …… the column decoder, 3,10
3,203 sense amplifier, 4,104,204 row decoder,
5,105,205 …… Selection circuit, 6,106,206 …… Operation circuit, 7,10
7,207 Data input / output buffer, 8,108,208 Control circuit 9,109,209 Address input buffer 10,110,210
... Address selectors, 11-1 to 11-5.
12-1 to 12-5: Inverter, 13-1 to 13-4: NA
ND gates, a, 1a, 2a: Address input buffer control signal (line), b, 1b, 2b: Address selector control signal (line), c, 1c, 2c: Row decoder control signal (line), d , 1
d, 2d ... column decoder control signal (line), e, 1e, 2e ...
Sense amplifier control signal (line), f, 1f, 2f ... data input / output buffer control signal (line), g, 1g, 2g ... arithmetic circuit control signal (line), h, 1h, 2h ... internal data input Output bus, i, 1i,
2i: System bus, Ai: Address data input terminal,
▲ ▼ …… Internal address latch signal, ▲ ▼…
... column address strobe signal, MODE, MODEi ... operation mode setting signal, ▲ ▼ ... read control signal, ▲
▼ …… Row address strobe signal, ▲ ▼ ……
Write control signal.

Claims (1)

(57) [Claims] 1. A data storage unit comprising a first plane, a second plane, and a third plane, which are a set of a plurality of memory cells, and an internal data input / output for inputting / outputting data for each plane of the data storage unit. A semiconductor memory device including a bus and an arithmetic circuit connected to the internal data input / output bus, wherein the control circuit generates a set of control signals for controlling the operation of the semiconductor memory device; 3 within one memory cycle
Means for generating a cycle internal address latch signal;
Supplying the data of the first plane to the arithmetic circuit, supplying the data of the second plane to the arithmetic circuit, and supplying the data of the second plane to the arithmetic circuit within respective periods of a first cycle, an intermediate cycle, and a final cycle of the three cycles. Means for controlling storage of operation result data of the operation circuit in the third plane.