JPH0750856B2 - Delay circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly to a digital delay circuit that can obtain data delayed by a fixed number of bits.

[Conventional technology]

Generally, in a digital television or the like, a line-by-line process is performed, so that a digital delay line for one line (910 bits) is used.

For example, in the process of separating a luminance signal and a chrominance signal from a composite color signal, separation by a comb filter is well known.

FIG. 3 is a block diagram of an example of a conventional delay circuit.

Referring to FIG. 3, this conventional delay circuit includes a delay line 31 for one line (for example, 910 bits), an adder 32,
This is a configuration including a subtractor 33.

The digital composite color signal supplied from the input terminal 34 is the output signal from the delay line 31 (that is, the signal one line before).
The luminance signal component is separated by the addition by the adder 32. Further, the subtractor 33 subtracts the output signal from the delay line 31 to separate the color signal components. The separated signals are output from the output terminals 35 and 36, respectively.

FIG. 4 is a block diagram of the delay line shown in FIG. 3, and the delay line 31 has a 910-bit shift transistor configuration.

That is, cascaded registers R ₁ to R _910, when writing the input data to the register R ₁ is a control that ahead of time transferred to the register R ₂ the data stored in the register R ₁ until it registers Data is stored between R _{1 and} R ₉₁₀ , and the first stored data is read from the register R ₉₁₀ .

[Problems to be solved by the invention]

Since the conventional delay circuit described above uses the shift register as the digital delay line, the number of elements required for the data storage capacity increases, which makes it difficult to store a large amount of data, and also increases the mounting area and power consumption. There is a problem.

An object of the present invention is to provide a delay circuit in which the number of required elements for the data storage capacity is small and the mounting area and power consumption can be reduced.

[Means for solving problems]

The delay circuit of the present invention has m (m ≧ 1 integer) rows and n (n
A dual-port memory cell array composed of m × n dual-port memory cells arranged in (≧ 1 integer) columns, an input buffer for amplifying write data to be written in the dual-port memory cells, and the write data. A row write selection circuit and a column write selection circuit for selecting the dual port memory cell of the desired address for writing to the dual port memory cell of the desired address of the dual port memory cell array; A row read selection circuit and a column read selection circuit for selecting the dual port memory cell at the desired address for reading stored data from the dual port memory cell, an external reset signal, an external write clock, and an external read clock. Each of the row write selection circuit and the column write selection circuit. Circuit, a row control circuit for selecting the row read selection circuit, and a clock control circuit for outputting each of the write clock and the read clock for controlling the column read selection circuit, a sense amplifier for amplifying the stored data, and an output of this amplifier In a delay circuit including an output buffer for outputting the row write selection circuit, the column write selection circuit, the row read selection circuit, and the column read selection circuit. The difference between the write address value selected by the circuit and the column write selection circuit and the read address value selected by the row read selection circuit and the column read selection circuit is set to a desired value (1 ≦ P). ≦ m × n−
Setting means for setting in 1), first dual port memory cell selecting means for selecting the dual port memory cells corresponding to the write address value in a fixed address order in synchronization with the write clock, The first dual port memory cell selecting means selects the dual port memory cell corresponding to the write address value in the predetermined address order, and at the same time, corresponds to the read address value in synchronization with the read clock. Second dual port memory cell selecting means for selecting a dual port memory cell in the predetermined address order.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, which is a block diagram of a delay circuit according to an exemplary embodiment of the present invention, a delay circuit according to an exemplary embodiment of the present invention includes an external reset signal RST, an external write clock WCK, and an external read clock RCK. Reset signal RST ', write clock WCK' and external read clock RC are input as internal signals.
A clock control circuit 1 for outputting each of K ', an input buffer 2 for amplifying write data, and a dual port memory cell Mij (1≤i≤m, 1≤j for writing the write data).
(An integer of ≤n), and a dual port memory cell array 7 having m in the row direction and n in the column direction and a dual port memory Mij of the dual port memory cell array 7 for writing the write data. Column read selection circuit 3 and row write selection circuit 4, and column read selection for selecting the dual port memory cell Mij at the desired address in order to read stored data from the dual port memory cell Mij at the desired address. Each of the circuit 5 and the row read selection circuit 6, a sense amplifier 8 for amplifying stored data, and an output buffer 9 for outputting the output of the amplifier 8 to the outside are configured.

The configuration and operation of the delay circuit of this embodiment will be described in detail below.

That is, the column write selection circuit 3 is a switch for connecting the input buffer 2 and the write digit line for writing the write data from the input buffer 2 into the memory cells in a fixed order in synchronization with the write clock WCK '. Generates a transistor activation signal. Since it is composed of a ring counter, when it reaches the end of the column, it returns to the beginning and repeats the same operation.

The row write selection circuit 4 selects the write word line in a fixed order in synchronization with the drive clock. A control signal from the column write selection circuit 3 is used as a drive clock, and this control signal is such that a pulse is generated once when the column write selection circuit 3 returns from the last column to the first column. Is configured. Since row write selection circuit 4 is also composed of a ring counter, when it reaches the end of the row, it returns to the first row and repeats the same operation. As a result, the memory cells arranged two-dimensionally can be written bit by bit from the first row and column to the last row and column.

The column read selection circuit 5 generates an activation signal for a switch transistor connecting the read digit line and the sense amplifier in order to read the read data of the memory cell in a fixed order in synchronization with the read clock RCK '. Since it is composed of a ring count, it returns to the beginning when the end of the column is reached and the same operation is repeated as in the case of writing.

The row read selection circuit 6 selects a read word line in the same fixed order as writing in synchronization with the drive clock. A control signal from the column read selection circuit 5 is used as a drive clock,
This control signal is configured to generate a pulse once when the column read selection circuit 5 returns from the last column to the first column. Since row read selection circuit 6 is also constituted by a ring counter, when the end of the row is reached, the operation returns to the first row and the same operation is repeated. As a result, the memory cells arranged two-dimensionally can be read bit by bit from the first row and column to the last row and column.

A reset signal RST ′ for setting the number of delay bits is input to each of the column write selection circuit 3, the row write selection circuit 4, the column read selection circuit 5, and the row read selection circuit 6. The reset signal RST ′ has a desired difference between the write address value and the read address value selected by the column write selection circuit 3, the row write selection circuit 4, the column read selection circuit 5, and the row read selection circuit 6. Used to reset each select circuit (3-6). That is, when the delay circuit is used as a 910-bit digital delay line, the address selected by the write selection circuit (3 and 4) and the address selected by the read selection circuit (5 and 6) are relative to each other. Reset to separate the 910 address.

For example, the reset signal RST 'resets the column write selection circuit 3 and the row write selection circuit 4 to the address 911, and the column read selection circuit 5 and the row read selection circuit 6 to the address 1, respectively. 'And read clock RCK'
The address is incremented by 1 in synchronization with. Therefore,
The first written data at the address 911 is read in the 911th read cycle and can be used as a 910-bit digital delay line.

The dual-port memory cell array 7 includes m × n dual-port memory cells Mij (1 ≦ 1 ≦ m, 1 ≦ j) arranged in m (m ≧ 1 integer) rows and n (n ≧ 1 integer) columns. ≤
n) and this dual port memory cell Mi
j has a write port and a read port separately and can write and read at different addresses at the same time.

When this dual-port memory cell Mij is used as a 910-bit digital delay line, the number of memory cells in the dual-port memory cell array 7 must be 911 or more.

Next, the configuration of the memory cell Mij and the write / read operation will be described.

The memory cell Mij has a read word XRi for transmitting stored information to the read digit line RDj, ▲ ▼ forming a pair with MISFETs Q ₃ and Q ₆ whose gates and drains are cross-coupled to each other.
Controlled by MISFETs Q ₁ and Q ₄ and a pair of write digit lines WDj and MISFETs Q ₂ and Q ₅ controlled by a write word line XWi for fetching write data of ▲ ▼ into a memory cell Mij.
It is composed by. Although not shown, an element for compensating leakage due to high resistance may be attached between the contact in the memory cell and the power supply terminal in order to statically retain the stored information.

The write data is amplified by the input buffer 2 and then the write data bus
WDB, output to ▲ ▼.

When the jth column is selected by the column write selection circuit 3,
The output YWj becomes high level, the MISFETs Q ₉ and Q ₁₀ of the write switch transistor become conductive, and one of the write digit lines WDj or ▲ ▼ becomes low level and the other becomes high level according to the write data.

Next, when the i-th row is selected by the row write selection circuit 4, the write word line XWi becomes high level and the memory cell Mij
MISFETs Q ₂ and Q ₅ become conductive, the write data is taken in, and the writing is completed. In addition, the following digit lines WDj, ▲
MISFETs Q ₁₃ and Q ₁₄ connected to ▼ are load elements for speeding up recovery of the digit line after writing.

In reading the stored data, when the i-th row is selected by the row read selection circuit 6, the read word line XRi becomes high level and the MISFETs Q ₁ and Q ₄ become conductive. That is, the stored data is transmitted to the paired read digit lines RDj, ▲ ▼.

Next, when the jth column is selected by the column read selection circuit 5, the output YRj becomes high level, the MISFETs Q ₁₁ and Q ₁₂ become conductive, and the read data of the read digit line RDj, ▲ ▼ forming a pair is read. Output to data bus RDB, ▲ ▼. The read data is amplified by the sense amplifier 8 and output buffer 9
Will be output.

MISFET connected to read digit line RDj, ▲ ▼
Q ₇ and Q ₈ are load elements for preventing the digit line from being completely discharged to the ground potential.

In this way, by using separate buses for writing and reading, writing and reading can be performed simultaneously on different memory cells. That is, when writing and reading the memory cells in the same column and different rows, since the write digit line pair and the read digit line pair are different, the write data and the read data have no influence on the read and the write, respectively. Can be done simultaneously without giving. Further, writing and reading of memory cells in the same row and different columns can be performed simultaneously without any influence on reading and writing because the write digit line pairs are different. The same applies when the rows and columns are different.

Therefore, when used as a digital delay line, if the predetermined number of delay bits P is set to 1 ≦ P ≦ m × n−1, the memory cells for writing and reading do not overlap, and an arbitrary number between them can be set as a predetermined value. .

When the write and read memory cells overlap, the stored information is destroyed and the write data is read as it is.

FIG. 2 is a block diagram of the column write selection circuit 3 shown in FIG.

Referring to FIG. 2, the column write selection circuit 3 has a flip-flop 21 ₁ having a function corresponding to a delayed type flip-flop (hereinafter referred to as DF · F), and a clock signal applied to the clock input terminal CK. Detects the logic level of the signal input to the data input terminal D at the rising edge of
It has a function of outputting a signal in phase to the output terminal Q, and the output signal is held until the next rising edge of the clock.

When a high level is applied to the preset terminal PR, a high level is generated at the output terminal Q regardless of the states of the input signals at the data input terminal D and the clock input terminal CK. Also, clear terminal CL
When a high level is applied to R, a low level is output to the output terminal Q regardless of the states of the input signals of the data input terminal D and the clock input terminal CK.

Further, the column write selection circuit 3 shown in FIG. 2 has DFF (21 _{1 to} 21 _n ) connected by the number n of columns, and the clock input terminal CK is commonly provided with the write clock WCK '. Is typing.
Also, the data input terminal D is connected to the previous D-F-F.
The output signal of the output terminal Q of is added in phase. First
The output signal from the output terminal Q of the _nth DF · F21 _n is applied to the data input terminal D of the DF · F21 ₁ of the nth. The output signal from the output terminal Q corresponds to the output YWj.

The reset signal RST 'is input to each DF / F21 _{1 to} 21 _n , and in the circuit shown in FIG. 2, the DF / F21 ₁ corresponding to the first column is connected to the preset terminal PR. , Other DF
・ F is input to the clear terminal CLR. Therefore, immediately after the reset, only the output YW ₁ is at the high level and the other outputs are at the low level. That is, the first column is selected.

In this way, by supplying the reset signal RST ′ to the preset terminal PR of the DF / F corresponding to the column to be reset, immediately after the reset signal RST ′ is applied,
The write column number can be a predetermined value.

The high level output YW ₁ of the _first column is applied to the data input terminal D of the _second DF · F21 ₂ by advancing the write clock WCK ′ bit by bit after reset. Therefore, at the next rising edge of the write clock WCK ', the DF-F21 ₂ corresponding to the second column outputs the high-level output YW ₂ . In this way, the output YWj of the jth column can be shifted to a high level, and the output of the output terminal Q of DF · F21 _n corresponding to the nth column is the first D−. F
・ Since it is added to the data input terminal D of F21 ₁ , it operates as a ring counter.

The inverted signal obtained by inverting the high level output YW _n from the output terminal Q of DF · F21 _n corresponding to the nth column is used as the drive signal of the row write selection circuit 4 described above.

The configurations of the row write selection circuit 4, the column read selection circuit 5, and the row read selection circuit 6 are basically the same as the configuration of the column write selection circuit 3, and the operation of these ring counters is also the column write. The operation is the same as that of the built-in selection circuit 3.

In other words, the row write selection circuit 4 has D connected by the number m of rows.
-F · F has a ring counter, the column read selection circuit 5 has a ring counter made up of D-F · F connected n in number of columns, and the row read selection circuit 6 has a row counter. It has a ring counter composed of D-F / F connected by the number m, and resets to the preset terminal PR of which D-F-F in the D-F-F row which constitutes each selection circuit. Signal RS
It can be operated as a delay line having a predetermined number of bits by selecting whether to supply T '.

In the above-described embodiment, the write clock WCK 'and the read clock RCK' are separately used. However, this is because if one clock is stopped externally or internally for a certain time after reset, the selection circuit driven by that clock is used. Also has the advantage that the number of delay bits can be changed in real time because it also stops for a certain period of time, but if the number of delay bits can be fixed, it is clear that the write clock and read clock can be made common and operate with the same clock. In this case, there is an advantage that the number of terminals can be reduced.

〔The invention's effect〕

As described above, the delay circuit of the present invention uses dual-port memory cells arranged two-dimensionally as storage elements, and controls so that the order of writing and reading becomes constant,
Moreover, the write data is read with a delay of a predetermined value by configuring the address difference between writing and reading to be a preset value by the reset signal and then performing writing and reading simultaneously in synchronization with the external clock. Since it can be used as a digital delay line using a memory cell instead of the shift register, there is an effect that the number of constituent elements can be reduced and the packaging area can be reduced by high integration to reduce power consumption. .

[Brief description of drawings]

1 is a block diagram of a delay circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a column write selection circuit shown in FIG. 1, and FIG. 3 is a block diagram of an example of a conventional delay circuit. Four
The figure is a block diagram of the delay line shown in FIG. 1 ... Clock control circuit, 2 ... Input buffer, 3 ... Column write selection circuit, 4 ... Row write selection circuit, 5 ... Column read selection circuit, 6 ... Row read selection circuit, 7 ... Dual Port cell array, 8 ... Sense amplifier, 9 ... Output buffer, 21 _{1 to} 21 _n ...... DFF, 31
... delay line, Mij ... dual-port memory cell, RCK,
RCK ′ …… Read clock, RDj, ▲ ▼ …… Read digit line, RST, RST ′ …… Reset signal, WCK, WCK ′ ……
Write clock, WDj, ▲ ▼ …… Write digit line, XRi …… Read word line, XWi …… Write word line.

Claims (1)

[Claims] 1. A dual port memory cell array composed of m × n dual port memory cells arranged in m (m ≧ 1 integer) rows and n (n ≧ 1 integer) columns. And an input buffer for amplifying write data to be written into the dual port memory cell, and a line selection for selecting the dual port memory cell at the desired address to write the write data to the dual port memory cell at the desired address in the dual port memory cell array. A row select circuit and a column read circuit for selecting the dual port memory cell at the desired address in order to read stored data from the dual port memory cell at the desired address. Each of the selection circuit, the external reset signal, the external write clock, and the external read clock, respectively. A clock control circuit for receiving the reset signal and the write clock and the read clock for controlling the row write selection circuit, the column write selection circuit, the row read selection circuit and the column read selection circuit, respectively. In a delay circuit including a sense amplifier for amplifying the stored data and an output buffer for outputting the output of the amplifier to the outside, the row write selection circuit, the column write selection circuit, the row read selection circuit, and the column read Each of the selection circuits is selected by the row write selection circuit and the column write selection circuit by the reset signal and selected by the row read selection circuit and the column read selection circuit, respectively. The difference from the read address value is the desired value P (1 ≦ P ≦ m × n−1)
Setting means, first dual port memory cell selecting means for selecting the dual port memory cells corresponding to the write address value in a fixed address order in synchronization with the write clock, and the first dual port memory cell selecting means. The dual port memory cell selecting means selects the dual port memory cell corresponding to the write address value in the predetermined address order, and at the same time, the dual port corresponding to the read address value is synchronized with the read clock. And a second dual port memory cell selecting means for selecting memory cells in the predetermined address order.