JPH06259955A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To change the number of bits per word by reading out/writing in by one word or plural words, responding to a clock signal. CONSTITUTION:This memory includes a mode signal input circuit 50 receiving through a terminal 107 a mode signal MD to variably designate the number of bits per word. For instance, the first mode making 8 bits 1 word, and the second mode making 16 bits 1 word, are set. A signal AD becomes a high level at the time of the first mode, and becomes a low level at the time of the second mode. The circuit 50 detects the level of a mode signal MD, writes in a mode signal IMD in it, and supplies it to a control circuit 30 and a read-out control circuit 40. When the signal IMD becomes high/low levels and designates the first/second modes, the circuits 30 and 40 write in or read out data by 8/16 bits. As a result, when the number of bits per word is designated, the number of bits can be changed by a mode changeover.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out (FIFO) memory, and particularly to an F-memory suitable for image processing of plain paper copiers, facsimile machines and the like.
Regarding IFO memory.

[0002]

2. Description of the Related Art Plain paper copier (hereinafter abbreviated to P
A FIFO memory is often used as a memory for serially digitally processing data for one line such as that found in a PC (personal computer), a facsimile machine (hereinafter abbreviated as FAX), and the like.

Generally, this kind of FIFO memory has a clock terminal for inputting a clock signal and a reset terminal for inputting a reset signal, and inputs a reset signal in synchronization with the clock signal to initialize an internal address (0 ) Initialize the address. Thereafter, the internal address is sequentially incremented (or decremented) in synchronization with the clock signal to perform the data write operation and data read operation. By having a clock terminal, a reset terminal, and other control signal terminals for writing and reading, and having dedicated terminals for data input and data output, writing and reading can be performed asynchronously.

FIG. 10 shows an example of a conventional FIFO memory of this type. This FIFO memory has a memory cell array 1 having a predetermined number of addresses for writing and storing and reading a word having the same number of bits as the number of bits of one word of the write data DTw, and a clock for writing. The write control circuit 2 that sequentially writes the write data DTw word by word in the memory cell array 1 according to the signal CKw and the reset signal RSTw, and the data stored in the memory cell array 1 according to the read clock signal CKr and the reset signal RSTr. The read control circuit 3 sequentially reads data in the order in which one word is written.

The depth direction of the FIFO memory, that is, the number of words is determined by the paper size and resolution of PPC or FAX. For example, in the case of A3 size vertical writing (297 mm) and a resolution of 400 dpi (16 dots / mm), a capacity of about 5K in the depth direction is required. Also, the number of bits (bit width) is determined by the gradation and processing application. For example, in the case of 256 gradations, 2 ⁸ requires a bit width of 8 bits.

In general, such a FIFO memory is used when comparing data between mutual lines in order to improve image quality, when aligning data of R, G, and B data in color, and at the same time. It is used when performing various data processing and calculations accompanying functionalization. That is, the data of each line is stored in each FIFO memory, delay data and the like are created, arithmetic processing is performed between the output data, and finally image data is created and output.

In recent years, due to the tendency toward higher image quality, higher functionality, and colorization in PPCs and FAXes, there is a wide variety of functional requirements for the FIFO memory.

For example, in a device using a large number of FIFO memories for one model or a device requiring high gradation,
There is an increasing demand for products with the same capacity in the depth direction and wider bit width.

[0009]

However, in the above-described conventional FIFO memory, the number of bits of each word in the memory cell array 1 is the same as the number of bits of the write / read word. For this reason, in response to the above-mentioned requirements, semiconductor manufacturers develop FIFO memories having a bit number corresponding to them, while OEMs and users can select from among these FIFO memories depending on the required specifications of the device using the FIFO memory. It is configured to select the most suitable one. That is, on the side of developing a FIFO memory, there is a problem that the number of development products is wide and the number of development man-hours (design man-hours, evaluation man-hours, mass-manufacturing man-hours, etc.) is increased.
On the side using the IFO memory, if a certain FIFO memory is selected, it is difficult to use it for developing functions in a multi-function device, and it is difficult to expand it to other models with different target usages. Since the memory must be purchased, the number of man-hours required for component evaluation, management, etc. increases, and there is a problem that they become complicated.

Therefore, an object of the present invention is to provide a FIFO memory capable of changing the number of bits per word.

[0011]

A FIFO memory according to the present invention is provided with a memory cell array having a plurality of memory cells, means for specifying a first mode or a second mode in response to a mode signal, and a clock signal. Means for selecting a memory cell by a first predetermined number each time in the first mode and a memory cell by a second predetermined number different from the first predetermined number in the second mode. And a means for performing data access to the memory cell.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings.

A FIFO according to an embodiment of the present invention shown in FIG.
The memory 10 is configured as a semiconductor integrated circuit and has a memory cell array 20, a write control circuit 30, and a read control circuit 40 as in the conventional example. However, this FI
The FO memory further has a mode signal input circuit 50 which receives a mode signal MD for variably designating the number of bits per word via a terminal 107. In this embodiment, the first mode in which 8 bits are 1 word and the second mode in which 16 bits are 1 word are set. The signal AD takes a high level in the first mode and takes a low level in the second mode. The mode signal input circuit 50 detects the level of the mode signal MD and internally supplies the mode signal IMD to the write and read control circuits 30 and 40. As will be described later in detail, when the mode signal AD, that is, the internal mode signal IMD is at the high level and the first mode is designated, the write control circuit 30 writes data to the memory cell array 20 by 8 bits and the read control circuit 40. Reads out data in units of 8 bits. When the signal MD goes low and the second mode is designated, 16-bit data writing and reading is executed.

8-bit data write / read and 1
Since it supports writing / reading 6-bit data,
Data input terminal 101 to which write data WDT is supplied
Is 16 and similarly, the data output terminal 104 for outputting the read data DRT is also 16. Write clock signal WCLK and write reset signal WRS
T is supplied to the terminals 102 and 103, respectively. Read clock signal RCLK and read reset signal RRS
T is supplied to the terminals 105 and 106, respectively.

Referring to FIG. 2, the memory cell array 20.
Are ⁿ word lines WO-W ^n-1 , 128 pairs of bit lines (80, 80B)-(B127, B17B), and memory cells M arranged at respective intersections of these word and bit lines.
Has C. In this embodiment, each memory cell MC is of a static type.

A write control circuit 30 is further shown in FIG. That is, the circuit 30 has a row pointer 303 and is connected to the word line WO-W ^n-1 . One word line W is selected when one of the output signals WSO-WS ^n-1 of the pointer 303 becomes active level. In this embodiment, 128 memory cells MC are connected to the selected word line W. These memory cells M
C is divided into 16 groups of 8 each, and 16 column switches DW0 to DW15 are provided corresponding to each group. As shown, each column switch DW is N
It consists of channel transistors. Further, the even-numbered column switches DW0, ..., DW14 are connected to the eight pairs of digit lines (D0, D0B)-(D7, D7B), and the odd-numbered column switches DW1 ,. Line (D8, D8B)-(D15, D15B)
It is connected to the. The column switches DW0-DW15 have corresponding selection signals DS0- from the column pointer 302.
It is turned on by DS15. Digit line (D
0, D0B)-(D15, D15B) is connected to a data write circuit 304, and the circuit 304 is connected to write data input terminals 101-0 to 101-15.

The column pointer 302 and the row pointer 303 control the level of each output signal DS0-DS15, WS0-WSn ^-1 under the control of the timing controller 301. The timing controller 301 uses the write clock WCLK and the write reset signal WRS.
T, and further the pointer 30 based on the mode signal 1MD
Control the timing of 2,303.

Referring to FIG. 3, the column pointer 306
Is composed of 16 stages of shift registers 302-0 to 302-15. Since each shift register has the same configuration, only the first-stage shift register 302-0 is shown. This shift register is a master-slave type, and the master flip-flop MST has a first clock terminal N1, a second clock terminal N2, and a P-channel and an N-channel MO, respectively.
It is composed of two transfer gates composed of S transistors and two inverters, and is connected as shown in the figure. The slave flip-flop SLV has the same configuration. However, the clock ends of the slave flip-flop SLV are shown as N3 and N4. The shift register 302-0 further has a NAND gate 3020 and an inverter 321 and generates a column selection signal DS0. Then, as shown in the figure, the clock ends N2, N of the even-numbered shift registers 302-0, ...
1, N4 and N3 are respectively the first clock line CK
1, an inverted clock line CK1, a second clock line CK2, and an inverted clock line CK2B thereof, respectively, while an odd-numbered shift register 302-
1, ..., 302-15 clock ends N1, N2, N3
N4 is connected to CK1B, CK1, CK1, CK1B, respectively.

Five inverters 301 forming a part of the timing controller 301 are connected to these clock lines.
0-3014 and two transfer gates 305
3, 3054 causes a clock synchronized with the write clock signal WCLK to appear. Transfer gate 305
3, 3054 is a mode signal IMD and its inverted signal I
Opening and closing are controlled by MDB, and signals IMD and IMDB
The level is determined by the inverters 51 and 52 based on the mode signal MD. That is, when the signal MD is at a high level, the gate 3053 is turned on (open) and 3054 is turned off (closed), so that a signal synchronous with the write clock signal WCLK appears on the clock line CK1 and an opposite phase signal is output on the clock line. Appears in CK2. On the other hand, when the mode signal MD is low level, the transfer gate 305
Since 4 is turned on, both the clock lines CK1 and CK2 are signals in phase with the write clock WCLK.

The output of the inverter 301b is connected to the input of the first-stage shift register 302-0, and the NOR gate 3 receives the write reset signal WRST and the output DC0 of the final-stage shift register 302-15 at its input.
The output of 015 is supplied.

The row pointer 303 has n stages of shift registers 303-0 to 303- (n-1). Each shift register has the same structure as the shift register of the column pointer 302. Then, as shown in the figure, the clock terminals N2 and N3 of each shift register 303-0 to 303- (n-1) are connected to the first row clock line RC1 and N1 and N4.
Are connected to their inversion lines RC1B, respectively.
These lines are connected to these clock signals CK1 and their inverted signals 1/10, NA connected as shown in the figure.
Supplied under the control of ND gate 3017 and inverter 3019. The output of each shift register is the corresponding A
The AND signal inputted to the ND 3030 and the clock CK1 becomes the corresponding word line selection signal WS.

To the input of the first stage shift register 303-0, the reset signal WRST and the final stage shift register 3 are supplied by the NOR gate 3051 and the inverter 3052.
An OR signal is supplied to the output of 03- (n-1).

Referring to FIG. 4, the data write circuit 30.
4 is an input buffer 3040-0 to 3040-1 connected to the data input terminals 101-0 to 101-15, respectively.
5 and the outputs thereof are connected to the data amplifiers 3043-0 to 3043-15 via the N-channel MOS transistors 3041-0 to 3041-15, respectively. The output of the data amplifier 3043 is connected to the corresponding digit line pair (D, DB). Outputs of the input buffers 3040-0 to 3040-7 are further passed through N-channel MOS transistors 3042-0 to 3042-7, respectively, and data amplifiers 3043-8 to 3043- are provided.
15 are connected to each. Transistor 3041
The gates of −0 to 3041-7 have shift registers 30
The data switching signal DSW0 from 48 is commonly supplied. The gates of the transistors 3042-0 to 3042-7 are commonly connected to an AND gate 3045 which takes the logical product of the mode signal IMD and the data switching signal DSW1 from the shift register 3049, and the transistors 3041-8 to 3041-8.
The gates of 3041-15 are commonly connected to an AND gate 3044 which receives the signal DSW1 and the inversion mode signal IMDB.

The shift registers 3048 and 3049 have the same structure as the shift register 302-0 and the like, and their clock terminals N1 to N4 are clock lines CK1 and CK1 as shown in the figure.
It is connected to CK1B, CK2, and CK2B. The input of the shift register 3048 is the write reset signal WRST.
And an OR gate 3 for receiving the output of the shift register 3049
It is connected to 060.

The read control circuit 40 (FIG. 1) is also constructed similarly to the write control circuit 30 described above. However, in FIG. 4, the data amplifiers 3043-0 to 3043-1
5, the input side is the digit line D side, and an output buffer is used instead of the input buffers 3040-0 to 3040-1. The row pointer in the read control circuit 40 is arranged on the right side of the memory cell array 20 in FIG. 2, and the data read circuit including the column switch is located under the array 20.

The data writing operation will be described in detail below, but the data reading operation is the same except that the data writing is replaced with the data reading.

When the mode signal MD is at the high level and the first
When the mode (data writing in 8-bit units) is designated, data writing is executed according to the timing chart shown in FIG. That is, since the signal MD is at the high level, a signal having the same phase as the write clock signal WCLK appears on the clock line CK1 and an opposite phase signal to the clock line CK2. In order to write data from the first address, the reset signal WRST is generated in synchronization with the clock signal WCLK. As a result, the row pointer 30
3 sets the selection signal WS0, and the column pointer 302 sets the selection signal DS0 to the active level. Thus, the word line W0 is selected, the column switch DN0 is turned on, and the 8-bit first group is selected from the memory cells connected to the word line W0.

The data switching signal DSW0 from the shift register 3048 (FIG. 4) also becomes active high level.
The transistors 3041-0 to 3041-7 are thus turned on, and the input buffers 3040-0 to 3040-7 and the data amplifiers 3043 to 3043-7 are respectively connected. Thus, the data input terminals 101-0 to 10-10
The 8-bit input data to 1-7 is written to the 8-bit memory cell MC at the first address.

Every time the write clock signal WCLK becomes high level, the data "1" in the shift register 302-0.
Are sequentially shifted to the registers of the next stage, and as a result, the column switch selection signals DS1 to DS15 sequentially become active high level (FIG. 5). That is, the column switches DW1-DW15 are sequentially selected. On the other hand, the clock to each shift register in the row pointer 303 is not supplied because the NAND gate 3017 is closed,
Therefore, the shift register 303-0 remains holding the data "1". The AND gate 3030-0 causes the selection signal WS0 of the word line W0 to become active high level in synchronization with the clock WCLK (FIG. 5). For the shift registers 3048 and 3049 (FIG. 4), 304
Since the output of 9 is fed back through the OR gate 3060, the data switching signals DSW0 and DSW1 are clocked by the clock W.
The active high level alternates in synchronization with CLK (FIG. 6). That is, the transistors 3041-0 to 30
41-7 and 3042-0 to 3042-7 are alternately turned on. Thus, the data input terminals 3040-0 to 3
The 8-bit data supplied to 040-7 is written in sequence after the second address.

When the selection signal DS15 from the shift register 302-15 becomes active high level and its carry output DC0 becomes high level, the gate 3015,
The selection signal DS0 is returned to the high level again by being fed back to the shift register 302-0 via 3016. At this time, N
Since the AND gate 3017 opens, the shift register 30
The data "1" in 3-0 is the shift register 30 of the next stage.
3-1. As a result, the selection signal WS-1 of the word line W1 becomes active high level via the AND gate 3030-1.

Thus, when the mode signal MD is at the high level and the first mode is designated, 8-bit data is written in the order of addresses.

The mode signal MD changes to the low level to change to the second mode (that is, data writing in 16-bit units).
Is designated, the operation is performed according to the timing shown in FIG.
That is, the transfer gate 3054 is on, 305
Since 3 is turned off, signals in phase with the write clock WCLK both appear on the clock lines CK1 and CK2. As is clear from the connection relationship between the clock ends N1 to N4 of the shift registers 302-0 to 302-15 and the clock writes CK1 to CK2B, the OR gate (301
The output of the slave flip-flop S via the shift register 302-0 and further via the master flip-flop MST of the shift register 302-1.
It is transmitted to the input of LV. Therefore, the column selection signals DS0 and DS1 simultaneously become active levels, and the column switches DW0 and DW1 are both selected (FIG. 6).

Clock terminals N1-N4 of shift registers 3048 and 3049 (FIG. 4) and clock line CK1
Since the connection relationship with -CK2B is also the same, the data switching signals DSW0 and DSW1 also become active high level at the same time (FIG. 6). However, the AND gate 3045 is closed because the signal IMD is at the low level, and therefore the transistors 3042-0 to 3042-7 are off. On the other hand, the AND gate 3044 opens,
The transistors 3041-8 to 3041-15 are turned on. Therefore, the data input terminals 101-0 to 101-
The 16-bit data supplied to 15 is written in 16 memory cells MC.

Each time the write clock signal WCLK becomes high level, the next two column switches DW are selected and 16-bit data is written.

Thus, when the first mode is designated by the mode signal MD, 8-bit data writing and reading are executed in the order of addresses, and when the second mode is designated, 16-bit data writing and reading are performed. It is executed in address order.

The row pointer 303 and the column pointer 302 can be configured like the column pointer 302 and the row pointer 303 of FIG. 3, respectively. In this case, each time the write clock WCLK becomes high level, the words W0-Wn _-1 are selected in that order, and the column switch DW0 is continuously selected until one cycle is completed. Further, it is apparent from the above configuration that not only the combination of 8 bits and 16 bits but also the combination of 4 bits, 8 bits, 16 bits and 32 bits can be similarly realized.

As is apparent from FIG. 3, the mode signal MD
Changes from high level to low level and vice versa are always accepted. That is, there may occur a case where data is written in the memory cell array 20 in units of 8 bits but is read in units of 16 bits, and vice versa. Therefore, it is desirable that the mode switching is always executed from the start address.

FIG. 7 shows a structure for that purpose. For this purpose, the mode signal input circuit 50 may be slightly modified.
That is, the present input circuit further has a D-type flip-flop 53, and the output of the inverter 52 is provided at the data input D thereof, and the write reset signal WRST is provided during the clock input.
Are input, and the internal mode signal IMD and its inverted signal I are output from its output Q and its inverted output QB, respectively.
The MDB has been removed. Therefore, the mode signal M
The level of D is taken in only when the reset signal WRST becomes active high level, and the internal mode signal IM
The level of D is controlled. Thus, the mode change is configured to be performed only on reset.

In FIG. 4, when the 8-bit mode is designated, the levels of the data input terminals 101-8 to 101-15 are undefined, and therefore the input buffer 3040-
The outputs of 8 to 3040-15 are also indefinite, and noise generated thereby may cause malfunction. Therefore, each of the input buffers 3040-8 to 3040-15 is preferably configured as shown in FIG. That is,
Each of the data input terminals 101-8 to 101-15 is connected to one input of the AND gate 3046 of the corresponding input buffer, and the other mode input has the inverted mode signal IMD.
B is supplied. The output of the AND gate 3046 is supplied to the corresponding transistor 3041 via the inverters 3047 and 3048. Therefore, when the 8-bit mode is designated, the output of the AND gate 3046 is held at the low level, and the input buffers 3040-8 to 3040-30.
Each output of 40-15 is also held at the low level.

Some data output terminals 104 (FIG. 1) are also used in the 8-bit mode. The data bus is connected even though it is not used. Therefore, as shown in FIG. 9, the output buffer is constituted by the tri-state buffer 1040, and the inversion mode signal IM
When DB is at low level (that is, the first mode is designated), its output is set to high impedance.

[0041]

As described above, according to the present invention, it is possible to change the number of bits for data writing and data reading by mode switching, and the optimum FIFO for PPC, FAX and the like.
O memory is provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a memory cell array and a write control circuit of FIG.

FIG. 3 is a circuit diagram showing part of the row pointer, column pointer and timing controller of FIG.

FIG. 4 is a circuit diagram showing the data write circuit of FIG.

FIG. 5 is a timing chart showing the operation in the first mode.

FIG. 6 is a timing chart showing the operation in the second mode.

7 is a circuit diagram of an improved input circuit of the mode signal input circuit of FIG.

FIG. 8 is a circuit diagram of an improved input buffer that is part of the input buffer of FIG.

9 is a circuit diagram showing an improved output buffer included in the read control circuit of FIG.

FIG. 10 is a block diagram showing a conventional example.

Claims (9)

[Claims] 1. A first-in-first-out type semiconductor memory, wherein a memory section having a plurality of words each having a plurality of bits, and write data to the first memory section in response to a write clock signal. Write one word at a time in the mode and write control circuit for writing a plurality of words at the second mode, and write data from the memory unit to 1 in the first mode in response to a read clock.
A semiconductor memory comprising: a read control circuit for reading a plurality of words in the second mode. 2. The write control circuit further selects a first word of the memory section in response to a write reset signal, and the read control circuit further selects the first word in response to a read reset signal, The write control circuit is enabled to change between the first and second modes in response to the write reset signal, and the read control circuit is responsive to the read reset signal between the first and second modes. 2. The semiconductor memory according to claim 1, wherein the change of is permitted. 3. The write control circuit has a plurality of data input terminals and a plurality of input buffers respectively connected to these data input terminals, and the read control circuit has a plurality of data output terminals and these data output terminals. A plurality of output buffers connected to each other, and a part of the input buffer generates an output fixed to a predetermined logic level regardless of the level of the corresponding data input terminal in the first mode. 2. The semiconductor memory according to claim 1, wherein a part of the output buffer is inactivated in the first mode to bring a corresponding data output terminal into a high impedance state. 4. A memory cell array having a plurality of memory cells, means for designating a first mode or a second mode in response to a mode signal, and a write clock when the first mode is designated. A first number of memory cells is selected each time the data is supplied, and a second number of memory cells different from the first number is selected each time the write clock is supplied when the second mode is designated. First selecting means for selecting; a third number of memory cells are selected each time a read clock is supplied when the first mode is designated, and the third mode is selected when the second mode is designated. Second selecting means for selecting a fourth number of memory cells different from the third number each time a read clock is supplied; and means for writing data to the memory cells selected by the first selecting means And the second choice Means for reading data from a memory cell selected by the means. 5. The first and third numbers are the same,
5. The semiconductor memory according to claim 4, wherein the second and fourth numbers are the same. 6. A plurality of first lines, a plurality of second lines intersecting each of these first lines, a plurality of memory cells arranged at intersections of these first and second lines, and a mode. Designating means for designating the first mode or the second mode in response to a signal; and the first line in the first mode with the second line selected in response to a clock signal. Selecting means for selecting a predetermined number of second predetermined numbers different from the first predetermined number in the second mode,
And a semiconductor memory including access means for performing data access to a memory cell arranged at an intersection of selected first and second lines. 7. The first line is a bit line and the second line
7. The semiconductor memory according to claim 6, wherein the line is a word line. 8. The access means includes a plurality of column switches, each of which is connected to a corresponding line of the plurality of first lines, and the selection means includes a column pointer and a row pointer. Each time the clock signal is supplied, one column switch is turned on in the first mode and at least two column switches are turned on in the second mode, and the row pointer is turned on until all the column switches are turned on. 8. The semiconductor memory according to claim 7, wherein one of the second lines is continuously selected. 9. The column pointer includes a shift register circuit having a plurality of outputs respectively connected to the plurality of column switches, and the row pointer has a plurality of outputs respectively connected to the plurality of second lines. 9. The semiconductor memory according to claim 8, including a shift register circuit having the same.