JPS6077514A - Delay time adjusting circuit - Google Patents

Abstract

PURPOSE:To attain miniaturization by counting a time difference between a 1st reference signal and a 2nd reference signal as input signals and outputting the 2nd reference signal delayed by the count value so as to use the signal for the write/read mode changeover of an RAM. CONSTITUTION:The time difference between a 1st reference signal 3 and a 2nd reference signal 4 is counted at a counter 201 of a delay time adjusting circuit by using a clock 2. The repetitive period of an address signal is set at an address counter 202 based on the count value 10 from the counter 201. A designation address 11 outputted from the counter 202 and the clock 2 are fed to a random access memory RAM101, and read RD and write WR operations are conducted respectively at the 1st half and the 2nd half of the address 11. Then the circuit constitution is simplified without the provision of a mode switching signal generator or the like of complicated constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay time adjustment circuit, and more particularly to a delay time adjustment circuit that automatically delays an input data string to a target timing.

A conventional delay time adjustment circuit will be explained with reference to the drawings. FIG. 1 is a block diagram showing an example of a conventional delay time adjustment circuit, and FIG. 2 is a time chart showing the sequence of signals in each part of FIG. In FIG. 1, the delay time adjustment circuit is connected to a random access memory (hereinafter referred to as 几AM) in which writing of input signal 1 and reading of output signal 9 are controlled.
) 101, a write address counter (hereinafter referred to as WAC) 103 initialized by the first reference signal 3, and a second
A read address counter (hereinafter referred to as RAC) 104 which is initialized by reference signal 4 of
Write address 5 or RACIQ4 from AC103
Selector (hereinafter referred to as 5EL) for selecting bladder ejection address 6 from
) 102, and a mode switching generator (hereinafter referred to as MDG) 105 which generates a mode switching signal 8 for writing/reading RAMl0I in response to a clock 2.

In this delay time adjustment circuit, WAC103 and RAM1
It is equipped with two address counters of 0I, and uses clock 2 to switch between AMIOI, input and read address designation. As shown in FIG. 2, address 7 output from the 5EL 102 has two addresses (for example, write address Wo and read address Rn-2, etc.) in one bit.

When clock 2 is used as mode switching signal 8, address 7
The changing point of clock 2 coincides with the changing point of clock 2. Here R
To avoid malfunction of AM101, mode switching signal 8
, change the on/off ratio of clock 2 using It is necessary to make sure that they do not match.

Therefore, in the delay time adjustment circuit of this example, WAC103°RA
f9ELIQ2 is required to select the output address of M101, and as a result, it shapes the clock signal and selects the output address of RAM10.
Since it is necessary to add an MDG 105 for switching the I mode, there is a drawback that the circuit configuration becomes complicated.

An object of the present invention is to count the time difference between the first and second reference signals, delay the input signal input to the RAM according to the first reference signal by the number of sets, and output the signal according to the second reference signal. It is an object of the present invention to provide a delay time adjustment circuit which eliminates the above-mentioned drawbacks and has a simplified circuit configuration by using a clock for switching between RAM write and read modes.

According to the present invention, a counter that counts the time difference between the first reference signal and the second reference signal, and a repetition period of the address signal that periodically changes depending on the count of the counter are set. A delay time adjustment circuit is obtained which is characterized by comprising an address counter and a random access memory which is addressed by the output of the address counter and whose readout is controlled by the same clock as that of the address counter.

Next, the present invention will be explained with reference to FIGS. 3 and 4.

FIG. 3 is a block diagram showing one embodiment of the delay time adjustment circuit of the present invention, and FIG. 4 is a time chart showing the sequence of signals in each part of FIG.

In FIG. 3, the delay time adjustment circuit adjusts the time difference between the first reference signal 3 and the second reference signal 4 by N1 using the clock 2.
Counter (hereinafter referred to as CNT) 201 and CNT 20
An address counter (hereinafter referred to as AI) C) 202 in which the edge return period of the sear address signal is set according to the count value 10 of 1;
It includes a RAM 101 whose write/read is controlled by a specified address 11 outputted from a DC 202 and a clock 2.

Next, the operation of this embodiment will be explained using FIGS. 3 and 4. CNT2O1 has the first reference signal 3 and the second
The time difference between the second reference signal 4 and the reference signal 4 is counted, and it is recognized that the second reference signal 4 lags the first reference signal 3 by a counted amount of 10 (here, D bits). This D bit I
Using the repetition period of the address signal that changes periodically in the ADc 202, the K is set so that the read and write operations are performed in the first half and the second half of the specified address 11, respectively.
Control RAMIOI. As a result, the first reference signal 3
Input signal 1 ('F, 1
,2. ~”) is the specified address 11 (“0, 1, 2.-”
) and after D focus, RAM according to the second reference signal 4.
Output signal 12 (@F', 1, 2 .
~”).

Therefore, the input data string is automatically delayed until the target timing and output.

As is clear from the above description, according to the delay time adjustment circuit of the present invention, the address of the RAM is specified using the result of counting the time difference between the first and second reference signals as the cycle of the address counter, and the clock is Since it is used to switch the write/read mode of the RAM and controls to perform reading and writing in the first half and second half of the address, respectively, the circuit configuration can be simplified and the circuit scale can be reduced.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an example of a conventional delay time adjustment circuit, FIG. 2 is a time chart showing the sequence of (i) in each part of FIG. A block diagram showing an embodiment of the delay time adjustment circuit of FIG.
5 is a time chart showing the sequence of signals in each part of the figure. In the figure, 1...input signal, 2- clock, 3
...first reference signal, 4 ...second reference signal,
5・■Including address, 6・・・・Reading address,
7...Address, 8...Mode switching signal, 9
．． 12・Output signal, 1o・・Counter, 11・・・・
・Specified address, 101 Random access memory address counter (RAC), 105 ・Mode switching signal generator (MDG), 201 ・Counter (C
N T ), 202... Address counter (AD
C). ,,;: ′,,, Agent Patent attorney Susumu Uchihara j−,”:”':', '
""? jFigure 2-G"-Bottom-"1 1

Claims (1)

[Claims] a counter that counts the time difference between a first reference signal and a second reference signal; an address counter in which a repetition period of an address signal that changes periodically according to the count of the counter is set; and the address 1. A delay time adjustment circuit comprising: a random access memory whose address is specified by the output of a counter, and whose write/read is controlled by the same clock as that of the address counter.