JPS62125589A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain application as a digital delay line having optional delay length by providing a delay circuit between a data input part and a write data bus and setting the delay amount of the delay circuit at a proper level. CONSTITUTION:A control circuit 1 inputs a applied reset signal RST, writing clock WCK and reading clock RCK and outputs internal control signals RST', WCK' and RCK' respectively. The signal RST' is inputted to address pointers 3-6 respectively and the writing and reading actions are initialized in different fixed addresses by the signal RST' respectively. In other words, input data Din is written on a dual port cell array 7 after a delay set to a delay circuit 10 in a writing mode. In this case, the delay length of the circuit 10 is set so that coincidence is secured between the address which is used when the valid write and inputted first after resetting is written on the array 7 via the data 10 and the address where the read data is set. Thus it is possible to form a circuit that has the variable delay length in response to the resetting interval.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit using dual-port memory cells as a digital delay line, and particularly relates to a semiconductor integrated circuit using dual-port memory cells as a digital delay line. The present invention relates to a semiconductor integrated circuit used as a delay line whose delay length can be made variable.

[Conventional technology]

In digital television and the like, a delay tr=line of one line (910 pits) is used to perform line-by-line processing. When creating such a delay line using an integrated circuit, a two-dimensionally arranged data gate memory cell array is used as a memory element, and the memory (writing/reading) order is controlled to be constant, and a reset signal is The configuration is such that the write address is initialized to a number that precedes the read address by a predetermined value (for example, 910 bits), and if write/read is performed in synchronization with the external clock after reset, the read address will be numbered 910 cycles after initialization. Since data that matches the first write address and is always delayed by 910 bits in synchronization with the clock can be read from C, it can be used as a digital delay line with a delay length of 910 bits.

[Problem that the invention seeks to solve]

However, in this configuration, the number of delays is fixed depending on the initialization address for writing and reading by reset, so that an arbitrary delay length or narrowing is inconvenient if it is desired to use a delay length other than 910 bits.

[Failure to solve the problem]

The semiconductor integrated circuit of the present invention includes a dual-port memory cell array arranged two-dimensionally, and in order to perform writing to the memory cell array, the memory cells are stored at a constant Il'!
a write row and column selection circuit configured to select a memory cell in the same order as in the write order; a read row and column selection circuit configured to select memory cells in the same order as in the write order for reading from the memory cell; and an external write clock. means for writing data into the memory cell in synchronization with an external read clock; means for reading data from the memory cell in synchronization with an external read clock; In a semiconductor integrated circuit equipped with means for initializing, the writing means includes a delay circuit driven in synchronization with an external write clock between the data input section and the write data bus, and the magnitude of the delay varies from the beginning after reset. It is characterized in that the input valid write data is set to a size just enough to be written to the read address initialized by the reset signal.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. The control circuit 1 receives a reset signal R that is not applied externally.
8T, write clock WCK.

Input the read clock RCK (WCK and RCK may be common), and input the internal control signal hole S'r', WCK.
Output 'RCK'. The input buffers 2, 2, and 2 are each composed of a ring counter. The read address pointer for column selection and the read address pointer for row selection are configured by counters. 7 is a dual port cell array arranged two-dimensionally in one row and one column. 8 is a sense amplifier for amplifying read data, and 9 is an output buffer for outputting its output as output data Dout. The delay circuit 10 connects the input buffer 2 and the write data bus, and outputs the signal ";A".
Driven by ICK/. Reset signal R8 from outside
By adding T, for example, the write address is initialized to write reset address 11, and the read address is initialized to read reset address 12, respectively.

The delay length of the tellay circuit 10 is set to a length corresponding to the number of cycles (ie, address difference) required for the write reset address 11 to catch up with the read reset address 12.

A write address pointer 3 for column selection generates an activation signal for a switch element connecting the output of a delay circuit 10, that is, a write data path bus and a bit line in the cell array 7. Write address pointer 3 for column selection
Since it is composed of a ring counter, when the output position of the activation signal reaches the end of the column, it returns to the beginning and repeats the same operation.

A write address pointer 4 for row selection selects write row lines in the cell array 7 in a fixed order in synchronization with a drive clock. As this drive clock, an internally generated pulse signal generated when the selected position by the write address pointer 3 for column selection returns from the last column to the first column is used. Since the row selection write address pointer 4 is also constructed as a ring counter, when the selection position reaches the end of the row, it returns to the beginning and repeats the same operation. This allows the two-dimensionally arranged dual port cell array 7 to be synchronized with the write clock WCK from the first row and column (top left of the cell array 7) to the last row and column (the right side of the cell array 7 in FIG. You can repeat writing up to (lower) endlessly.

The read address pointer 5.6 is also configured in the same way as in the write case. The column is the signal RCK as the driving clock.
/, an internally generated pulse signal generated from the read address pointer 5 for row/column selection is used. In order to read the read data from the dual port cell array 7 in a fixed order in synchronization with the signal RCK/, the output of the column selection read address pointer 5 is connected to the bit line in the cell array and the read data bus (snap or sense amplifier). It is used as an activation signal for the switch element connected to the input section of 8). The output of the read address pointer 6 for row selection is connected to the read row iK in the memory cell.

Each write address pointer 3, 4 and read address pointer 5 is set so that writing and reading have the same selection order.
, 6 are constructed. The delay circuit 10 is composed of a shift register whose input and output are separated. Also, the signal WCK' is prevented from running out of power as its driving clock.

A signal RS 'L' is input to address pointers 3 to 6, and this signal initializes (resets) write/read to different fixed addresses.At this time, the read reset address is different from the write reset address. C,
It is set at a position preceding by an address corresponding to the delay length of the delay circuit 10. In other words, when writing,
Because of the delay circuit 10, the input data Din is not written to the memory cell immediately, but is written to the memory cell after a delay set in the delay circuit 10. At this time, since the delay circuit 10 and the write address pointer 3 for column selection are driven by the same signal WCK', the write address also moves when the data is delayed in the delay circuit 10. Therefore, after a reset (that is, the write address/read address is initialized to a predetermined address), valid write data input for the first time reaches the write data bus via the delay circuit 10, and the address at which it is written to the memory cell is determined. , just reset (initialize) the read
The write/read reset address or the delay length of the delay circuit 1o is adjusted so that the addresses match.

Next, the operation of the semiconductor memory configured as described above will be explained using the timing diagram of FIG. 3. In order to make the explanation easier to understand, it is assumed that the clocks WCK and RCK are driven by the same clock CK (internally CK). The read reset address is 0, and the write reset address is -2 (-2 means an address two addresses back from address 0). Also light/
Since the difference in read reset addresses is 2, it is assumed that the number of delays of the delay circuit IO also corresponds to 2.

In FIG. 3, reset is performed when the reset signal R8T is at H level. Seventeen addresses of memory cells are selected during one cycle of the common clock signal CK, and the internal address is incremented at the rising edge of the same clock. Based on the above assumption, the write address is reset to address 12 and the read address is reset to address 0 by signal R8T.

Also, among the input data Din, the first valid write data DO after reset is input. The write address and read address are incremented in synchronization with the clock CK, and new data (DI, D2, . . . ) is applied to the input data Din in accordance with the new write address.

The difference between the write address and read address is 2 dollars (2 cycles), and the delay number of the delay circuit is adjusted accordingly to 2 bits (2 cycles). Two cycles later, the data DO is delivered to the output of the write data bus, that is, the delay circuit 1o, and written to the write address at that time, that is, address 0. Therefore, input data D1 is written to address 1, data D2 is written to address 2, and so on.
After all, the write data after reset is essentially memory cell 0.
This means that it is written to address 0.

On the other hand, since the read address is reset to address O from the beginning, the data written at address O in synchronization with the clock, that is, the data written after the previous reset, is read sequentially from the beginning. I will put it out. In other words, the data written after the reset in FIG. 3 will be read out sequentially from the beginning after the next reset. Therefore, by applying the reset signal RS'[' at cycle intervals within a range where the memory capacity is less than 1, a delay circuit having a variable delay length depending on the reset interval can be constructed.

In the above explanation, the difference between the write reset address and the read reset address is set to 2, but this value is not limited to 2 and can take any other number. In this case, it is necessary to change the delay length of the delay circuit 10 depending on the value. If this value is too large, it will take time for the write data from the terminal Din to actually be written into the memory cell, so generally 1 or 2 is blank.

〔Effect of the invention〕

As explained above, the present invention allows the digital delay line to be used as a digital delay line having a delay length corresponding to the reset interval by arbitrarily selecting the reset interval.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing diagram showing the operation of the figure. 1... Control circuit, 2... Input buffer, 3... Write address pointer for column selection, 4... Write address pointer for row selection, 5... Read address pointer for column selection, 6... Read address pointer for row selection, 7... Dual port cell array, 8...
・-・Se/Su/P, 9・・・・・・Output buffer, 1
0...Delay circuit, 11...Write reset address, 12...Read reset address, R8T...Reset signal, WCK...
...-Write clock, RCK...Read clock, CK...Common clock for write and read, R8T";WCK',RCK'...
...Internal control signal, Do. Dl...Light data. Agent Patent Attorney Susumu Uchihara 1 D, ″-f1 / Figure

Claims (1)

[Claims] A dual-port memory cell array arranged in a two-dimensional manner, a write row and column selection circuit configured to select memory cells in a fixed order for writing to the memory cell array, and a write row and column selection circuit configured to select memory cells in a fixed order for writing to the memory cell array; a read row and column selection circuit configured to select memory cells in the same order as for writing; means for writing data to the memory cells in synchronization with an external write clock; In a semiconductor integrated circuit comprising means for reading data from a memory cell, and means for initializing a write address and a read address in the writing means and reading means to mutually different predetermined values using an external reset signal, the writing means comprises: A delay circuit that is driven in synchronization with an external write clock is included between the data input section and the write data bus, and the magnitude of the delay is determined by the time at which valid write data input for the first time after reset is read from the address initialized by the reset signal. A semiconductor integrated circuit characterized by being set to a size just large enough to be written on.