JPH04343539A - Elastic storage circuit - Google Patents

Abstract

PURPOSE:To remove the inflow of a charging/discharging current into an unnecessary writing bit line and to reduce current consumption by inputting input data only to the writing bit line connected to an address cell selected in accordance with an address output from a writing address counter by means of a control circuit in the case of writing the input data. CONSTITUTION:When data have been written in a storing cell C11, both of a WAC row address line 4a and a WAC column address line 5a are turned to a 'H' level and connected to a writing bit line 101 by using only the writing transmission gate 26 of the cell C11 to attain the writing of input data D1. In such state, other row address lines 4b to 4d and column address lines 5b to 5d are turned to 'L' level states, the input data D1 are inputted only to a writing bit line 101a by a writing bit line control circuit 100 and inhibited from being inputted to another writing bit line 101b. Since the data D1 are inputted only to the bit line 101 parallel with a selected address line 4, the inflow of a charging/discharging current can be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and in particular to FIFO (First In First Out) devices.
t) This relates to the configuration of a data writing system of an elastic store circuit, which is a type of memory.

0002

[Prior Art] An elastic store circuit is an FI circuit that absorbs signal phase fluctuations and has a function suitable for time multiplexing.
It is a type of FO memory, and writing and reading can be performed using independent clocks.

FIG. 5 shows, for example, the journal of the Institute of Electronics and Communication Engineers;'
80/9 Vo1. J63-C NO. 9, pp.
FIG. 5 is a block diagram for explaining a conventional elastic store circuit described in Nos. 578 to 585. The transmitted input data DI is written into one store cell in a store cell matrix 2 of m rows and n columns by operating a write address counter (WAC) 1 using a write clock WCK. Here, WR (inverted) is a write reset signal, and when this signal is taken in, the write address is initialized. The written data is written using the write clock WCK.
The read address counter (RAC) 3 is operated with a special read clock RCK, and reading is performed in synchronization with RCK. Signal RR (inverted) is a read reset signal and initializes the read address. In this manner, the elastic store circuit is a type of FIFO memory in which the WAC1 and RAC3 are independent and write and read operations can be performed independently. Here, WI (inversion) and RI (inversion) are signals for inhibiting writing and reading, respectively, and when these signals fall, writing or reading of data at this time is not performed. Further, the signal CS (inverted) is a chip select signal that turns this LSI into an active state. Vcc and Vss are power and ground terminals, respectively.
13 is a gate.

FIG. 6 is a more detailed block diagram of the elastic store circuit. The store cells Cij are arranged in a matrix of m rows and n columns, but in the figure, for simplicity, they are arranged in a matrix of 4 rows and 4 columns.
An example for columns is shown below. WAC1 and RAC3 are arranged around the store cell matrix 2, and these address counters are divided into two types: row counters 1a and 3a that select each row of store cells C11 to C44, and column counters 1b and 3b that select each column. Consists of a ring counter. Although not shown, the carry output of the row counter 1a is AND
Column counter 1b enable (EN
) terminal. As a result, the column counter 1b increments by one step while the row counter 1a completes one cycle. Here, each ring counter is composed of a set D-flip-flop (S-D-F/F) 9 and a reset D-flip-flop (R-D-F/F) 10. Address selection for store cells C11 to C44 is performed by ANDing two types of address lines, row and column. Input data DI input in series is thus sequentially stored in the selected store cells C11 to C44, and then the same address selection as during writing is performed to store the data in the store cells C11 to C44 in synchronization with the read clock RCK. The stored data is sequentially read out to obtain serialized data. In addition, 4a to 4d are WAC row address lines, 5
a to 5d are WAC column address lines, 6a to 6d are RA
C column address lines, 7a to 7d are write bit lines, 8
A to 8d are read bit lines, 11 is a D-F/F, 12 is an inverter, and DQ is a data output terminal.

A detailed diagram of the store cell is shown in FIG. The store cell of the unit receives the output of the latch 20 section consisting of two inverters, which is an information storage section, and the NAND gate 21 of the WAC row address line 4 and WAC column address line 5, and writes to the latch 20, which is a storage section. A transmission gate 26 consisting of a P-channel transistor 22 and an N-channel transistor 23 controls the connection of the bit line 7, and receives the output of the RAC column address line 6 to control the connection between the latch 20, which is a storage section, and the read bit line 8. The transmission gate 27 includes a P-channel transistor 24 and an N-channel transistor 25, and an inverter 28.

The operation of the conventional elastic store circuit will be explained based on FIGS. 6 and 7. First, the write operation will be explained. Consider the case where data is written to the store cell C11. At this time, WAC row address line 4
a and the WAC column address line 5a are selected and both are at the "H" level, the transmission gate 26 for writing in the store cell C11 is opened, the latch 20 of the storage section is connected to the write bit line 7a, and the input data is D.I.
is written into latch 20 through write bit line 7a. In the next cycle, WAC row address line 4a becomes non-selected, and the write operation of store cell C11 ends. At the same time, the WAC row address line 4b becomes selected,
A write operation for the store cell C21 is started. At this time,
Input data DI is input not only to write bit line 7a but also to write bit lines 7b to 7d.

In case of read operation, RAC column 3b
In response to the output, the RAC column address line 6 rises, the read transmission gate 27 opens,
Data for one column of store cells connected to the selected RAC column address line 6 is read onto the read bit lines 8a to 8b and latched into the DF/F 11. This data is controlled by the output of the RAC row 3a and is serially read out to the data output terminal DO in synchronization with the clock.

[0008]

The conventional elastic store circuit is constructed as described above, and all write bit lines are charged and discharged during a write operation. As shown in Figure 7, since the drains of the P-channel transistor and N-channel transistor of the store cell are connected to the write bit line, a very large junction capacitance is attached in addition to the wiring capacitance, which causes consumption. There was a problem in that the electricity used was wasted.

The present invention has been made to solve the above-mentioned problems, and aims to eliminate unnecessary power consumption and provide an elastic store circuit with low power consumption.

0010

[Means for Solving the Problems] The present invention provides input data D
A write bit line control circuit 100 is provided for inputting input data DI only to the write bit line 101 connected to the store cell Cij selected according to the address output of the write address counter 1 when writing I. .

[0011]

[Operation] In the present invention, when a store cell Cij is selected according to the address output of the write address counter 1 when input data DI is written, the store cell Cij is selected according to the address output of the write address counter 1.
write bit line control circuit 10 so that input data DI is input only to write bit line 101 connected to
Controlled by 0. It is not input to other write bit lines.

0012

【Example】

Example 1. Hereinafter, one embodiment of the present invention will be described based on the drawings. In FIG. 1, the same reference numerals as in the conventional example indicate the same components, and a shaded portion 100 is a write bit line control circuit newly provided in the conventional example.
The configuration is such that the input data DI during writing is controlled by the output of the WAC row address line 4. That is, the selected WAC row address line 4 controls input data DI so that it enters only the write bit line 101 connected to the selected store cells C11 to C44.

The operation will be explained in detail below. For example, assume that data is written to store cell C11. In this case, the WAC row address line 4a goes to "H" level and at the same time the WAC column address line 5a goes to "H" level, and only the write transmission gate 26 of store cell C11 is opened and connected to the write bit line 101, and the input data is DI is written. At this time, other WA
C row address lines 4b-4d and WAC column address lines 5b-5d are at "L" level. In one embodiment of the present invention, the input data DI is controlled by the write bit line control circuit 100 so that it is input only to the write bit line 101a and not to the other write bit lines 101b.

An example of such a write bit line control circuit is shown in FIG. In this embodiment, input data D
I is connected to the write bit line 101 through a NAND circuit 30 with the WAC row address line 4. Therefore, input data DI is input only to the write bit line (101a in the above example) running parallel to the selected WAC row address line (4a in the above example). On the other hand, other WAC row address lines (4b to 4d in the above example) are “
Because of the NAND circuit 30,
No data is input to the write bit lines (101b to 101d in the above example) and they remain at the "H" level and do not change.

As described above, in the present invention, input data DI is input only to the write bit line 101 running parallel to the selected WAC row address line 4.
The charging and discharging current of write bit line 101 is significantly reduced. For example, in a configuration in which store cells are arranged in a matrix of m rows and n columns, the charging and discharging current of the write bit line 101 is reduced to 1/m compared to the conventional example.

Example 2. In this first embodiment, when moving to the next cycle, the selected WAC row address line 4 becomes "L" level, and at the same time, the write bit line 10
The potential of 1 becomes "H" level. In this case, depending on the wiring delay relationship between the WAC row address line 4 and the write bit line 101, the potential of the write bit line 101 becomes "H" first.
level, and then the WAC row address line 4 becomes “L” level.
” level, and an erroneous write may occur. In order to prevent this from happening, the write bit line control circuit is configured as shown in FIG. 3. In this embodiment, the output of the NAND circuit 30 A delay element 104 is provided after the
The configuration is such that the change of the write bit line 101 to the "H" level is delayed in response to the change of the WAC row address line 4 to the "L" level.

Example 3. Furthermore, another embodiment is shown in FIG. In FIG. 4, the write bit line control circuit is connected to an inverter 34.
and a transmission gate 33 consisting of transistors 31 and 32. During writing, only the write bit line 101 running parallel to the selected WAC row address line 4 is connected to the input data DI. In the next cycle, the WAC row address line 4 becomes "L" level, and the write bit line 101 is disconnected from the input data DI and becomes a floating state. Eventually, the potential of the write bit line 101 settles to the "L" level due to junction leakage at the drains of the transistors 22 and 23 of the transmission gate 26 of the store cell, but for a while after being disconnected, the potential of the write bit line 101 remains low. Since the level remains unchanged, no erroneous writing occurs.

[0018]

As described above, according to the present invention, input data is input only to the write bit line connected to the selected store cell and not to the others, so that the write bit line is unnecessary during writing. There is no charging/discharging current, and the effect is that the consumed power is not wasted.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an elastic store circuit according to an embodiment of the present invention.

FIG. 2 is a logic diagram of a write bit line control circuit according to the first embodiment of the present invention.

FIG. 3 is a logic diagram of a write bit line control circuit according to a second embodiment of the present invention.

FIG. 4 is a logic diagram of a write bit line control circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing the configuration of an elastic store circuit according to a conventional embodiment.

FIG. 6 is a diagram showing in more detail the configuration of the elastic store circuit according to the conventional embodiment shown in FIG. 5;

FIG. 7 is a diagram showing in detail the configuration of the elastic store circuit according to the conventional embodiment shown in FIG. 6, particularly the store cell portion.

[Explanation of symbols]

1a Write row address counter 1b Write column address counter 2 Store cell matrix 3a Read row address counter 3b Read column address counter 4a to 4d
WAC row address lines 5a to 5d WAC column address lines 6a to 6d
RAC column address lines 7a-7d Write bit lines 8a-8d Read bit line 9 S-D-F/F 10 R-D-F/F 11 D-F/F 20 Latch 21 NAND gate 22 P-channel transistor 23 N-channel Transistor 24 P-channel transistor 25 N-channel transistor 100 Write bit line control circuits 101a to 101d Write bit line 104 Delay elements C11 to C44 Store cell

Claims (1)

[Claims] 1. A plurality of store cells arranged in a matrix as a data storage section, a plurality of write word lines and a plurality of write bit lines for writing data to the store cells, and a plurality of write word lines and a plurality of write bit lines for writing data to the store cells. It consists of multiple read word lines and multiple read bit lines for reading data, and a write address counter is operated in the write block to serially write data to the store cell, and reading is independent of the write clock. In an elastic store circuit configured to read data serially from the store cell by operating a read address counter with a read clock, when writing data, the data is stored in the store cell selected according to the address output of the write address counter when writing data. An elastic store circuit comprising a write bit line control circuit for inputting data only to the connected write bit line.