RU2152072C1 - Dynamic priority device - Google Patents

Abstract

FIELD: computer engineering and automatic control, in particular, interrupt generators, data flow controllers, generators of data bank addresses in logical processors. SUBSTANCE: device has request register, priority unit, two groups of OR gates, group of AND gates, two OR gates, n l-bit priority registers, n groups of bit AND gates. Goal of invention is achieved by introduced AND gate, OR gate, (n+1) priority registers, (n+2) logical units, each of which has two groups of AND gates, group of AND gates, group of OR gates, three gates, two AND gates, delay gate 32. EFFECT: increased field of application, simplified design. 6 dwg

Description

 The invention relates to computer technology, automatic control and can be used in devices for interrupting programs, controlling data flows and forming the executive address of banks in logical processors.

 A variable priority device is known (USSR author's certificate N 1383353, class 4 G 06 F 9/46, bull. N 11, 1988), containing a trigger, the single and zero inputs of which are the device mode inputs, the request register, the bit inputs of which are a group of request inputs of a device, the first group of AND elements, the first inputs of which are combined and connected to a single output of a trigger, the second input of each i-th (i = 1,2, ..., n, where n is the number of request inputs) of an AND element the first group is connected respectively with the i - th (i = 1,2, ..., n) bit output of the register interrogation, the second group of AND elements, the first inputs of which are combined and connected to the zero output of the trigger, the second input of each i - th (i = 1,2, ..., n) element And the second group is connected respectively cj - th (j = n , n-1, ..., 1) by the bit output of the request register, the first group of OR elements, the inputs of which are connected respectively to the outputs of the same elements AND of the first and second groups, and the outputs are with the inputs of the first OR element, the priority code register, whose inputs are the control inputs of the device mode setting, and the outputs are connected to the same decoder inputs, the third group of AND elements, the inverse inputs of which are connected respectively to the outputs of the decoder, the fourth group of AND elements, the first inputs of which are connected to the inverse inputs of the same elements AND of the third group, the second inputs of the elements AND of the fourth group are combined and connected to the output of the first OR element, the output of the first AND element of the fifth group is connected to the direct input of the second AND element of the third group, the output of the ith (i = 2,3, ..., (n-1)) element of the And fifth element is connected to the direct input (i + 1) element And the third group, out one of the nth element AND of the fifth group is connected to the direct input of the first element AND of the third group, the outputs of the same elements AND of the fourth and third groups, respectively, are connected to the inputs of the same elements OR of the second group, the outputs of which are respectively connected to the first inputs of the elements AND of the sixth group and direct inputs elements And the fifth group, the inverse inputs of the elements And the fifth group and the second inputs of the elements And the sixth group, respectively, are combined and connected to the outputs of the corresponding elements of the same OR OR the first group , And outputs elements of the sixth group are connected respectively to the inputs of the encoder, the outputs of which are a group of information outputs of the device.

 Signs of an analogue common with the claimed technical solution are the request register, encoder, first group of elements I.

- число разрядов кода маски, N - число входных запросов, при которой каждый запрос (абонент) может иметь только два уровня приоритета и рост аппаратурных затрат при реализации данного устройства.The reasons that impede the achievement of the required technical result are the low resolution when managing requests η = 2 • C $\genfrac{}{}{0ex}{}{\text{i}}{\text{N}}$ / 2 where

- the number of bits of the mask code, N - the number of input requests at which each request (subscriber) can have only two priority levels and an increase in hardware costs when implementing this device.

 A device of variable priority (USSR author's certificate N 1444766, class. 4 G 06 F 9/46, bull. N 46, 1988) containing a request register, two groups of AND elements, an OR-NOT element, a group of decoders, a group of registers , a group of OR elements, a trigger, a first OR element, an AND element, and a group of m blocks for generating the maximum code (m is the number of requests), moreover, the group of code inputs of the device is connected to the group of information inputs of the group registers, the group of inputs of the code of the subscriber number of the device is connected to groups group decoder inputs, and The information inputs of the request register are request devices, the output of each group decoder is connected to the write permission input of the group register of the same name, the inputs of the And elements of the first group are the indicator outputs of the device, the outputs of the request register are connected to the inputs of the first OR element, the output of which is the signal output of the device, characterized in that in order to expand the scope by providing the ability to service subscribers with absolute and relative device priorities yours contains trigger groups, the OR-NOT element, the second, third fourth elements OR-NOT, and the request and response inputs of the device are connected to the OR-NOT element, the response inputs of the device are connected to the inputs of the second OR element, each response input of the device is connected to a reset input group trigger of the same name and with the same input reset request register, each output of which is connected to the start input of the unit of the same name generating the maximum group code, the group of outputs of each group register is connected to the first group and information inputs of the unit of the same name forming the maximum code of the jth group, the output of the group of outputs of each of which (j = 1,2, ..., m) is connected to the corresponding input of the jth element OR NOT of the group, the output of which is connected to j - m the input of the second group of information inputs of each unit for generating the maximum code of the group, the indicator output of each unit for generating the maximum code of the group is connected to the first input of the same element And the second group, the output of each element And the second group is connected to the installation input in "1" by one group trigger, the clock input of each of the group triggers is connected to the output of the same element of the group OR, the inputs of each element of the group are connected to the outputs of all the group triggers, excluding the output of the group trigger of the same name, the output of the OR element is NOT connected to the second inputs of all elements of the second group , the output of each group trigger is connected to the first input of the element of the same name AND the first group, the outputs of the elements of the first group are connected to the inputs of the third OR element, the output of which is connected to the reset reset input , the device startup input is connected to the corresponding input of the second OR element, the output of which is connected to the first input of the AND element, the second input of which is the first input of the device mode setting, the output of the AND element is connected to the first input of the fourth OR element, the second input of which is the second input of the mode setting devices, the output of the fourth element OR is connected to the second inputs of all elements AND of the first group, the information inputs of the triggers of the group are connected to the logical zero input of the device, the information input igger connected to the input of the logical unit of the device.

 Signs of an analogue common with the claimed technical solution are a request register, a group of priority code registers, a trigger, elements AND groups.

 The reasons that impede the achievement of the required technical result are hardware redundancy, depending on the growth of the information capacity of the device.

элемента ИЛИ второй группы соединен с i - ым входом второго блока приоритета, группа выходов которого подключена к группе входов шифратора, к группе входов сброса регистра запросов и к группе входов первого элемента ИЛИ, выход которого соединен с входом установки в "О" триггера, вход установки в "1" которого подключен к выходу второго элемента ИЛИ, первый и второй входы которого являются входом сигнала ответа и входом "Пуск" устройства соответственно, при этом третьи входы каждого блока элементов И группы подключены к выходу соответствующего регистра приоритета, входы регистра приоритета являются группой входов кода приоритета устройства.Of the known technical solutions, the closest in technical essence to the claimed object is a variable priority device with address encryption (USSR author's certificate N 1234837, class. 4 G 06 F 9/46, bulletin N 20, 1986), containing the request register, the inputs of which are the request inputs of the device, a trigger, an encoder, the outputs of which are a group of information outputs of the device, n priority registers (n is the number of request sources), a group of decoders, a group of blocks of AND elements, two groups of OR elements, two priority blocks itet, two OR elements, m groups of AND elements (m is the number of priority codes), the first block of each block of elements AND groups connected to the output of the corresponding priority register, the second inputs of all blocks of elements AND groups connected to the output of the trigger, the group of outputs of each element block And the group is connected to the group of inputs of the corresponding group decoder, the output of the ith

of the OR element of the second group is connected to the i-th input of the second priority block, the output group of which is connected to the group of inputs of the encoder, to the group of inputs of the reset of the request register and to the group of inputs of the first OR element, the output of which is connected to the installation input in the "O" trigger, input setting to "1" which is connected to the output of the second OR element, the first and second inputs of which are the input of the response signal and the "Start" input of the device, respectively, while the third inputs of each block of elements AND groups are connected to the output of the corresponding priority register, priority register inputs are a group of device priority code inputs.

In the known device, the sequence of servicing n requests is specified both by the sequence number (i = 1,2, ..., n) of the request and by assigning each of n requests with the corresponding code combination of m (m≤n) values. It is not ruled out that a number of requests can be endowed with the same priority code values recorded in registers. The determination of the highest priority request at time t in a known device is implemented by the following algorithm:
1. Unit requests highlight the corresponding priority code values.

2. The allocated code combinations are decoded by decoders, that is, they are converted respectively into code combinations for one combination With _m ¹ , ie in the combination of a unitary code, the position "1" in the combination of which displays the decimal equivalent (M = 1,2, ..., m) of the decoded combination of the priority code. The structure of the decoder corresponds to the code formation law of the priority code used. The use of other classes of codes to set the priority, i.e., to use this priority device for other computers, will require the use of other decoders, i.e. another priority device.

 3. The combination of the outputs of the decoders of the same name with logical elements OR in m disjunctive channels of binary equivalents of the code values of the priority codes ensures the appearance of a single signal in the corresponding m channels. The channel number corresponds to the combination number occupied among m combinations.

 4. To determine the most priority combination among the decoded combinations of the priority code, a circuit-determined algorithm of the priority block is intended, ie there is no possibility of changing the priority.

 5. A single signal from the output of the priority block polls the outputs of the same name for all n decoders by means of AND elements (m groups, each with n elements), ie queries are determined that have at time t the highest priority value (maximum or minimum) of the code combination; there can be several such queries, as already indicated.

 6. Using a priority block with a circuit-set priority for the importance of sequence numbers, the highest priority request is selected with subsequent encoding of its address.

 7. By transferring to "0" the state of the discharge trigger, the discharge number of which corresponds to the number of the allocated request, request register and control trigger, the transition to servicing the next priority request is carried out.

 The disadvantages of the prototype are the limited scope, since the structure of the device is designed for only a certain class of priority code, the lack of control of the interrupt threshold, i.e. the connection of the circuit and software levels of computer interruption, and significant hardware costs due to the redundancy and complexity of the procedure for determining the highest priority code combination (items 2, 3, 4, 5 of the above steps of the algorithm and the corresponding circuit elements: n decoders, m AND elements, priority block , mxn elements And).

 The problem to which the invention is directed, is to expand the functionality and reduce hardware costs due to parallel-discharge comparison of priority codes.

 The technical result achieved by the implementation of the invention is to expand the functionality achieved by increasing the order of information content of the device and providing a masking mode for requests, in addition, more than ten times lower hardware costs and a more uniform structure is provided.

 The technical result that can be obtained by carrying out the invention is achieved by the fact that a variable priority device containing a request register containing a group of request inputs, which are a group of request inputs of the device, and two mode setting inputs, a priority block containing two mode setting inputs connected to the inputs of the job request register mode, and n control inputs, which are the same inputs of the device, two groups of OR elements and a group of AND elements, the outputs of the priority block are connected with the inputs of the encoder, the outputs of which are the information outputs of the device, with the inputs of the reset of the request register and with the inputs of the first OR element, the output of which is connected to the zero input of the trigger, the second OR element, the first and second inputs of which are inputs of the “Answer” and “Start” signals "devices, respectively, n 1-bit priority registers (n is the number of request sources), the inputs of which are inputs of setting priority codes for device request sources, n groups of bit elements AND l elements in each group e, the first inputs of which are grouped together and connected to the corresponding outputs of the request register, the second inputs of all bit elements AND groups are connected to a single output of the trigger, the outputs of the priority registers are bitwise connected to the third inputs of the bit elements AND of the corresponding groups, the first element And, the first input which is connected to the output of the second OR element, the second input of the first AND element is connected to the output of the third OR element, the inputs of which are connected respectively to the request input and the query register, and the output of the first AND element is connected to a single input of the trigger, n logic blocks, the information inputs of which, respectively, to the bits and groups are connected to the outputs of the bit elements AND groups, and each logical block contains, in each bit, except the first, the second AND elements, the first inputs of which are the corresponding (2,3, ... l) -information inputs of the logic block, the third elements of And, the first inputs of which are bitwise combined with the second inputs of the second elements of And, the fourth elements of OR, the first inputs whose odes in each category are connected to the outputs of the second AND elements, and the second inputs are connected to the outputs of the third AND elements, the output of each fourth element OR of the i-th category (where i = 1,2, ..., l-1) is connected to the combined the inputs of the second and third elements AND the subsequent discharge, the output of the fourth element OR of the l discharge is the information output of the logical block, the first bit of each logical block contains the fifth OR element, the first input of the fifth OR element is the first information input of this logical block, the output of the fifth of the OR element is connected to the combined second input of the second AND element and the first input of the third AND element of the second bit of this logic block, the inputs of the first OR element of the first group are connected to the first information inputs of n logical blocks, the zero output of the first OR element of the first group is connected to the combined second inputs of the fifth OR elements of n logical blocks, the inputs of the jth (j = 2,3, ... l) OR element of the first group are connected to the outputs of the second elements of the AND (j-1) th category of n logical blocks, and the zero output of the said element OR is connected to the combined second inputs of the third AND elements of the (j- 1) th category of n logic blocks, the first inputs of the first group of AND elements are respectively connected to the unit outputs of the OR elements of the first group, and the second inputs are combined and connected to the output of the sixth OR element, the inputs which are connected to the information outputs of the logical blocks, the first inputs of the second group of AND elements are connected to the information outputs of the corresponding logical blocks, the second inputs of the mentioned AND elements are combined, and the outputs, respectively о are connected to the information inputs of the priority block, the device also contains a second group of OR elements, the (n + 1) and (n + 2) th identical logic blocks, the information inputs of the (n + 1) th logical block are respectively connected to the outputs elements of the first group of the (n + 2) -th logical block, the information inputs of which are respectively connected to the outputs of the (n + 1) -th priority register, the inputs of which are the inputs of the code for the highest priority of the device, the inputs of the first element of the second group are connected to the first information inputs dams of the (n + 1) th and (n + 2) th logical blocks, the zero output of the first OR element of the second group is connected to the combined second inputs of the fifth elements OR of the (n + 1) th and (n + 2) th logical blocks, the inputs of the jth (j = 2,3, ..., l) element of the OR of the second group are connected to the outputs of the second elements of the And (j-1) -th discharge of the (n + 1) -th and (n + 2) -th logical blocks, and the zero output of the said OR element is connected to the combined second inputs of the third elements of the AND (j-1) -th category of the (n + 1) -th and (n + 2) -th logical blocks, the first inputs of the fourth and fifth elements And combined and connected to information the ion output of the (n + 1) th logical block, the second inputs are also combined, the second input of the fourth AND element being inverse, and connected to the information output of the (n + 2) th logical block, the inputs of the seventh OR element are connected to the outputs of the fourth and of the fifth AND element, and the output is connected to the combined second inputs of the AND elements of the second group, the input of the delay element is connected to a single output of the trigger, and the output to the third inputs of the And elements of the second group and to the third inputs of the fourth and fifth elements I.

 The presence of distinctive features: the introduction of (n + 2) logical blocks, three groups of AND elements, the sixth OR element, the (n + 1) -th priority register, the fourth and fifth AND elements, the seventh OR element and the delay element with the corresponding relationships determine the conformity of the claimed technical solutions to the criterion of "novelty."

 The work is based on the well-known method based on the provisions of ordinal logic.

где r - адрес члена в вариационном ряде

- число сочетаний из i - элементов по N.Let an input sequence of random numbers X = {x ₁ , x ₂ , ..., x _n } be given. Using some functional dependencies, this series must be ordered, i.e. Y = F (x ₁ , X ₂ , ..., x _n ) = x _Adr ⁽¹⁾ > x _Adr ⁽²⁾ >...> x _Adr ⁽ⁿ⁾ , moreover, the argument x is continuous, i.e. x _i ∈ {a, b} As such a dependence, the so-called order functions are constructed, of the form:

where r is the address of the term in the variational series

- the number of combinations of i - elements in N.

Having constructed these functions, we obtain a variational series of the form Y = x ⁽¹⁾ > x ⁽²⁾ >...> x ^(N) .

 In practice, it makes sense to pose the problem as follows: the proposed device should implement a method for selecting one or more queries that have among n queries the highest priority value of the code combination, followed by priority coding according to a priori given priority sequence.

 This method is based on parallel-bitwise comparison of priority codes (regardless of the code class) with the selection of only that request (or requests) having (having) the highest priority (for example, maximum) code combination value among request priority values code having a single value on the moment of analysis in the corresponding bits of the query register.

If only one unit request is endowed with such a code value, its address is encoded directly; if there are several, the highest priority unit request is allocated according to an a priori set sequence of priorities. The number of possible options for selecting a single request and the coding sequence of all single requests is set by the values of the control signals at the inputs of the priority block. The number of priority levels that the proposed device is endowed with can be defined as:
M = C _n ⁱ 2 ⁱ 2 (C _K ⁱ ) ² ,
where n is the number of priority code values, m = 2 ¹ , m≤n;
l is the number of unit vectors at time t, i ∈ {l, n}
K is the number of unit requests having the same priority code values.

где a_ij∈ {0,1} - элементы кодовых комбинаций, I_i∈ {0,1} - сигналы запроса в момент времени t,
i=l,...,n, j=l,...l, - номер разрядного коэффициента а_ij.So, the set of priority priority code signals, switched to the request inputs of logical blocks, is represented by a quasi-matrix of code values logically multiplied by the signal matrix - request matrix:

where a _ij ∈ {0,1} are elements of code combinations, I _i ∈ {0,1} are request signals at time t,
i = l, ..., n, j = l, ... l, is the number of the discharge coefficient a _ij .

Then the set of code signals at the inputs of logic blocks at time t will be displayed as a quasi-matrix (if I ₂ = 1, I ₅ = 1, I ₇ = 1, I _(n-1) = 1, I _n = 1).

Примечание: в обозначениях старший разряд нумеруется "1",..., младший l в соответствии с нумерацией элементов матрицы.

Note: in the notation, the leading digit is numbered "1", ..., the least l in accordance with the numbering of the matrix elements.

Адреса запросов, имеющих в старшем разряде единичное значение, определяются операцией:

i=l,n (согласно примера i=2,5,7,n-1,n).Thus, the number of rows and their sequence numbers in the quasi-matrix are determined by the sequence numbers of the elements of the matrix column with the unit values of the query signals at time t. In logical blocks, starting with the highest order, the maximum value of the highest order (the first elements of the matrix of priority codes) is determined

Addresses of requests that have a single value in the high order are determined by the operation:

i = l, n (according to the example i = 2,5,7, n-1, n).

 This operation also allows you to display the addresses of all requests, provided that the senior level of the priority codes is equal to zero.

, либо только те, у которых разрядные коэффициенты имеют единичный уровень, т.е.

. На втором шаге реализации метода определяются минимальные значения коэффициентов второго (после старшего) разряда в каждом запросе, относительно значений адресов запросов после первого анализа:

т. е. этой операцией определяется адрес единичного запроса, имеющегося в кодовой комбинации а_i2 = 1. При

- этот сигнал является адресом соответствующего ему запроса.Thus, the unit address Adr (I _i ) = 1, i = 1, ..., n will have either all unit requests (I _i = 1), i.e. bit coefficients with a zero level

, or only those for which the discharge coefficients have a unit level, i.e.

. At the second step of the method implementation, the minimum values of the coefficients of the second (after the senior) rank in each request are determined, relative to the values of the addresses of the requests after the first analysis:

that is, this operation determines the address of a single request, available in the code combination a _i2 = 1. When

- this signal is the address of the corresponding request.

где

Общий адрес запросов по результатам анализа состояния разрядных коэффициентов второго разряда (элементов второго столбца матрицы кодов приоритета) определяется как:

Единичные запросы, у которых первые (старшие разрядные коэффициенты) наделены нулевым уровнем a_i1 = 0, имеют адрес

. Следовательно, такие запросы и на втором шаге анализа состояния разрядных коэффициентов независимо уже от их состояния будут иметь вид Adr(I_i)₂=0, т.е. даже при условии

и т.д. до l - го шага, т.е. единичные сигналы будут на выходах только тех логических блоков, на которые поданы одинаковые коды приоритета, содержащие "1" - цы в старших разрядах.Provided that the coefficients of the second category are equal to the zero level, all requests display the address of the requests at the level of the second category, defined as:

Where

The general address of the requests based on the analysis of the state of the discharge coefficients of the second category (elements of the second column of the matrix of priority codes) is defined as:

Single queries for which the first (highest bit coefficients) are endowed with a zero level a _i1 = 0 have the address

. Consequently, such requests in the second step of analyzing the state of the discharge coefficients, regardless of their state, will have the form Adr (I _i ) ₂ = 0, i.e. even provided

etc. to the lth step, i.e. single signals will be at the outputs of only those logical blocks for which the same priority codes are submitted, containing "1" - ts in the higher digits.

 The alleged invention is illustrated by drawings, where in FIG. 1 is a structural diagram of the device, FIG. 2 is a block diagram of a request register; FIG. 3 is a block diagram of a priority block; FIG. 4 is a table showing the operation of the device; FIG. 5 is a table of hardware resources.

The device contains (Fig. 1) register 1 requests (RE) containing the request inputs 2 (2 ₁ , ..., 2 _n ), which are a group of request inputs of the device, two inputs of the job mode, block 3 priority (PSU), containing inputs 4 (4 ₁ ; 4 ₂ ) of the job mode connected to the inputs of the job mode of the register of requests 1, and n inputs 5 (5 ₁ , ..., 5 _n ) of the control, which are the same inputs of the device, two groups of OR elements (6 and 7, respectively) and a group of elements AND 8, outputs 9 (9 ₁ , ..., 9 _n ) of priority block 3 are connected to the inputs of the encoder 10 (ШК) of the same name, the outputs of which are information outputs 11 (11 ₁ , ..., 11 _n ) of the device, with inputs 12 (12 ₁ , ..., 12 _n ) of the reset of register 1 of the requests and with the inputs of the first element OR 13, the output of which is connected to the zero input of the trigger 14 , the second element OR 15, the first and second inputs (inputs 16, 17, respectively) of which are the inputs of the signals "Answer" and "Start" of the device, respectively, and the output is connected to the first input of the first element And 18, the second input of which is connected to the output of the third element OR 19, the inputs of which are connected respectively to the request inputs of the register 1 requests, and the output p the first- AND gate 18 is connected to the trigger input unit 14, n l-bit registers 20 (20: ₁ -20 _n) priority (RP) (n - number of queries sources) 21 inputs (21, ..., 21 _n) which are inputs of setting priority codes to the request sources of the device, n groups of bit elements AND 22 (22 ₁ ¹ - 22 _l ¹ ; - 22 _l ² - 22 _l ² ; ..., 22 ₁ ⁿ - 22 _l ⁿ ) with l elements in each group, the first inputs of which are grouped together and connected to the corresponding outputs of the register 1 of requests, the second inputs of all bit elements AND 22 ( 22 ₁ ¹ - 22 _l ¹ ; 22 _l ² - 22 _l ² ; ..., 22 ₁ ⁿ - 22 _l ⁿ ) groups are connected to a single output of trigger 14, the outputs of registers 20 (20 ₁ , ..., 20 _n ) priorities are bitwise connected to the third inputs of the bit elements And 22 (22 ₁ ¹ - 22 _l ¹ ;. 22 ₁ ² - 22 _l ² ; .., 22 ₁ ⁿ - 22 _l ⁿ ) of the corresponding groups, n - logical blocks 23 (23 ₁ , ..., 23 _n), whose data inputs are respectively connected to groups of digits and us with bit outputs of AND gates 22 ₍₁ ¹ 22 - ¹ 22 _{l; 1} 22 ² - 22 ² _l; .. ₁ 22 ⁿ - 22 _l ⁿ⁾ groups, wherein each logic block 23 (23 _1, ..., 23 _n ) contains, in each category, except the first, the second elements AND 24 (24 ₁ ¹ - 24 _l ¹ , 24 ₁ ² - 24 _l ² , ..., 24 ₁ ⁿ - 24 _l ⁿ ), the first inputs of which are corresponding (2,3, ..., l) information inputs of logic blocks 23 (23 ₁ ,. . . 23 _n ), the third elements And 25 (25 ₁ ¹ - 25 _l ¹ , 25 ₁ ² - 25 _l ² , ... 25 ₁ ⁿ - 25 _l ⁿ ), the first inputs of which are bitwise combined with the second inputs of the second elements And 24 ( 24 ₁ ¹ - 24 _l ¹ , 24 ₁ ² - 24 _l ² , ..., 24 ₁ ⁿ - 24 _l ⁿ ), the fourth elements OR 26 (26 ₁ ¹ - 26 _l ¹ , 26 ₁ ² - 26 _l ² , ..., 26 ₁ ⁿ - 26 _l ⁿ ), the first inputs of which in each category are connected to the outputs of the second elements AND 24 (24 ₁ ¹ - 24 _l ¹ , 24 ₁ ² - 24 _l ² , ..., 24 ₁ ⁿ - 24 _l ⁿ ), and the second inputs - with the outputs of the third elements AND 25 (25 ₁ ¹ - 25 _l ¹ , 25 ₁ ² - 25 _l ² , ... 25 ₁ ⁿ - 25 _l ⁿ ), the output of every fourth element OR 26th i-th category (i = 2,3, ... l-1) is connected to the combined inputs of the second and third elements And 24 and AND 25 of the subsequent discharge, the output of the fourth element OR 26 of the lth discharge is the information output of the logical block 23 (23 ₁ , ..., 23 _n ), the first bit of each logical block 23 (23 ₁ - 23 _n ) contains the fifth elements OR 27 (27 ₁ ¹ , 27 ₁ ² , ..., 27 ₁ ⁿ ), the first input of every fifth element OR 27 (27 ₁ ¹ , 27 ₁ ² , ..., 27 ₁ ⁿ ) is the first information input of this logic block 23, the output of every fifth element OR 27 (27 ₁ ¹ , 27 ₁ ² , ..., 27 ₁ ⁿ ), connected to the combined second input of the second element And 24 (24 ₁ ¹ , 24 ₁ ² , ..., 24 ₁ ⁿ ) and the first input of the third element And 25 (25 ₁ ¹ , 25 ₁ ² ,. .., 25 ₁ ⁿ ) of the second category of this logic block, the inputs of the first OR element 6, of the first group are connected to the first information inputs of n logic blocks 23 (23 ₁ , ..., 23 _n ), the zero output of the first element OR 6 _{1 of the} first groups connected to the combined second inputs of the fifth elements OR 27 (27 ₁ ¹ , 27 ₁ ² , ..., 27 ₁ ⁿ ) n logic blocks 23 (23 ₁ , ..., 23 _n ), the inputs of the jth (j = 2,3, ..., l) of the element OR 6 (6 ₂ , 6 ₃ , ..., 6 ₁ ) of the first group are connected to the outputs of the second elements AND 24 (24 ₁ ¹ - 24 _l ¹ , 24 ₁ ² - 24 _l ² , ..., 24 ₁ ⁿ - 24 _l ⁿ ) (j-1) -th bit of n logic blocks 23 (23 ₁ - 23 _n ), and the zero output of the mentioned element and OR is connected to the combined second inputs of the third elements AND 25 (25 ₁ ¹ - 25 _l ¹ , 25 ₁ ² - 25 _l ² , ..., 25 ₁ ⁿ - 25 _l ⁿ ) (j-1) th category of n logical blocks 23 (23 ₁ , ..., 23 _n ), the first inputs of the first group of elements AND 8 (8 ₁ , ..., 8 _l ) are respectively connected to the unit outputs of the elements OR 6 (6 ₁ , ..., 6 _l ) of the first group, and the second inputs are combined and connected to the output of the sixth element OR 28, the inputs of which are connected to the information outputs of the logic blocks 23, the first inputs of the second group of elements AND 29 (29 ₁ , ..., 29 _n ) are connected to the information outputs of the corresponding logically of their blocks 23, the second inputs of the mentioned AND elements are combined, and the outputs are respectively connected to the information inputs of the priority block 3, the device also contains a second group of elements OR 7 (7 ₁ - 7 _l ), (n + 1) -th and (n + 2 ) -th identical logic blocks (23 _{(n + 1)} and 23 _{(n + 2),} respectively), information inputs of the (n + 1) -th logical block 23 _{n + 1,} respectively, are connected to the outputs of AND elements 8 (8 ₁ ,. .., 8 _l ) of the first group, (n + 2) —th logical block 23 _{(n + 2)} , the information inputs of which are respectively connected to the outputs of the (n + 1) -th register 20 _{(n + 1)} priority, inputs 21 _{(n + 1)} to orogo are input job code highest device priority, the inputs of first OR July _1, a second group connected to the first data inputs of (n + 1) - th, and (n + 2) - th logical block 23 _{(n + 1)} and 23 _{(n +2)} , the zero output of the first element OR 7 ₁ , the second group is connected to the combined second inputs of the fifth elements OR 27 _{(n + 1)} (n + 1) - logical block and OR 27 _{(n + 1)} (n + 2) of the logical block, the inputs of the jth (j = 2,3, ... l) element OR 7 (7 ₂ , 7 ₃ , ..., 7 _l ) of the second group are connected to the outputs of the second elements And 24 (24 ₁ ^{(n + 1)} , 24 ₂ ^{(n + 1)} , ..., 24 _l ^{(n + 1)} ) and 24 (24 ₁ ^{(n + 2)} , 24 ₂ ^{(n + 2)} , ..., 24 _l ^{(n + 2)} ) (j-1 ) -th discharge of the (n + l) -th and (n + 2) -th logical blocks 23 _{(n + 1)} and 23 _{(n + 2)} , and the zero output of the said OR element is connected to the combined second inputs of the third AND elements 25 (25 ₁ ^{n + 1} , 25 ₂ ^{(n + 1)} , ..., 25 _l ^{(n + 1)} ) and I 25 (25 ₁ ^{(n + 2)} , 25 ₂ ^{(n + 2)} , ... , 25 _l ^{(n + 2)} ) of the (j-1) -th category of the (n + l) -th and (n + 2) -th logic blocks 23 _{(n + 1)} and 23 _{(n + 2)} , the first inputs the fourth and fifth elements And 30 ₁ and And 30 _{2 are} combined and connected to the information output of the (n + l) th logical block 23 _{(n + 1)} , the second inputs are also combined, and the second input of the fourth element And 30 ₁ is inverse, and connected to the information output (n + 2) of the log block 23 _{(n + 2)} , the inputs of the seventh element OR 31 are connected to the outputs of the fourth and fifth elements And 30 ₁ and And 30 ₂ , and the output is connected to the combined second inputs of the elements And 29 (29 ₁ , ..., 29 _n ) of the second group, the input of the delay element 32 is connected to the single output of the trigger 14, and the output is connected with the third inputs of the elements And 29 of the second group and with the third inputs of the fourth and fifth elements And 30 ₁ and And 30 _2, respectively.

The request register 1 contains (Fig. 2) the first group of elements AND 33 (33 ₁ , ..., 33 _n ), the first inputs of which are combined and are the input 4 _{2 of} the reset mode of request register 1, the second inputs of the i-th (i- = l, 2, ..., n) of the And 33 element are respectively connected to the jth input of the reset of the request register (j = n, n-1, ..., 2,1), the second group of And 34 elements (34 ₁ , ..., 34 _n ), the first inputs of which are combined and are the input 4 _{1 of} the reset mode, the second inputs of the i-th (i-th (i = 1, 2, ..., n) element And 34 are respectively connected to j-th input of the reset register request (j = 1,2, ..., n), the first group of elements OR 35 (35 ₁ ,..., 35 _n ) the first inputs of which are connected to the corresponding outputs of the AND 33 elements of the first group, and the second inputs are connected to the corresponding outputs of the AND 34 elements of the second group, the outputs of the OR 35 elements of the first group are connected to the zero inputs of the triggers 36 (36 ₁ , ..., 36 _n ), the unit inputs of which are the request inputs 2 (2 ₁ , ..., 2 _n ) of the request register, and the outputs are the bit outputs of the request register.

Priority block 3 contains (Fig. 3) a trigger 37, the single and zero inputs of which are inputs 4 (4 ₁ ,; 4 ₂ ) of setting the mode of the tunable priority block, the first group of elements AND 38 (38 ₁ , ..., 38 _n ) , the first inputs of which are combined and connected to the single output of the trigger 37, the second input of each i-th (i = 7,2, ..., n) element And 38 of the first group is an information input 29 (29 ₁ , ..., 29 _n ) priority block 3, the second group of elements AND 39 (39 ₁ , ..., 39 _n ), the first inputs of which are combined with the zero output of the trigger 37, the second input of each i-th (i = 1,2, ..., n) element AND 39 second g groups are connected respectively with the j (j = n, n-1, ... 1) - th information input 29 (29 ₁ , ..., 29 _n ) of priority block 3, the first group of OR elements 40 (40 ₁ , .. ., 40 _n ), the inputs of which are connected respectively with the outputs of the elements of the same names And 38 (38 ₁ , ..., 38 _n ) and And 39 (39 ₁ , ..., 39 _n ), respectively, of the first and second groups, and the outputs are with the inputs of the first element OR 41, priority code register 42 (RPC), the inputs of which are control inputs 5 (5 ₁ , ..., 5 _n ) of priority block 3, and the outputs are connected to the inputs of the same name as decoder 43 of the priority code (DCT) , the third group of elements And 44 (44 ₁ , ..., 4 4 _n ), whose inverse inputs are respectively connected to the outputs of the decoder 43, the fourth group of elements AND 45 (45 ₁ , ..., 45 _n , the first inputs of which are connected to the inverse inputs of the elements AND 44 (44 ₁ , ..., 44 _n ) of the third group, the second inputs of the elements AND 45 (45 ₁ , .., 45 _n ) of the fourth group are combined and connected to the output of the first element OR 41, the output of the first element AND 46 _{1 of the} fifth group is connected to the direct input of the second element AND 44 _{2 of the} third group, the output of the i-th (i = 2,3, ..., (n-1)) element And 46 _i , the fifth group is connected to the direct input of the (i + 1) -th element And 44 ^{(i + 1)} third g groups, the output of the nth element And 46 _n , the fifth group is connected to the direct input of the first element And 44 _{1 of the} third group, the outputs of the same elements And 45 (45 ₁ , ..., 45 _n ) and And 44 (44 ₁ , .. ., 44 _n ), respectively, of the fourth and third groups, respectively, are connected to the inputs of the elements of the same name OR 47 (47 ₁ , ..., 47 _n ) of the second group, the outputs of which are respectively connected to the first inputs of the elements AND 48 (48 ₁ , ..., 48 _n ) the sixth group and the direct inputs of the elements AND 46 (46 ₁ , ..., 46 _n ) the fifth group, the inverse inputs of the elements AND 46 (46 ₁ , ..., 46 _n ) and the second inputs of the elements AND 48 (48 ₁ , ..., 48 _n ) of the sixth group, respectively Are connected and connected to the outputs of the corresponding elements OR 40 (40 ₁ , ..., 40 _n ) of the first group, the outputs of the elements AND 48 (48 ₁ , ..., 48 _n ) of the sixth group are the discharge outputs 6 (6 ₁ ,. .., 6 _n ) a tunable priority block.

The device operates as follows. On request inputs 2 ₁ , ..., 2 _n (see Fig. 1), at arbitrary instants of time, single signals of service requests arrive, which are recorded in the corresponding bits of register 1 of the request. The capacity of the register 1 requests is equal to the number of subscribers n, and the number of the category of the register 1 requests determines its static priority. Priority codes corresponding to each request are a priori set by the control computer (operator) and can be calculated, for example, on the basis of statistical data, such as the frequency P _i ^{* of the} appearance of the i-th request signal, among n requests, in a certain period of time. Priority codes 21 applied to the inputs (21 _1, ..., 21 _n) and device 20 are recorded in the registers (20 _1... 20 _n) priority code. The decision to choose the highest priority request among requests with the same priority code is also carried out by the control computer (operator) and is set in the form of single signals applied to inputs 4 (4 ₁ , 4 ₂ ) of the mode job and to control inputs 5 (5 ₁ ,. .., 5 _n ) priority block 3.

 For dynamic and flexible adjustment of variation by a system of priorities in the control process, the proposed device is endowed with the property of tunability with minimal hardware costs, i.e. must possess the property of universality and practically satisfy the needs of computers for various purposes.

 In the initial state, the trigger 14 is in the zero state. In priority registers 20, priority codes are received, and in register 1, service requests from subscribers. The device starts by the “Start” signal, which is input through the OR element 15 and the And 18 element, and the presence of at least one request at the inputs of the register 1 requests received through the OR element 19 and the And 18 element and sets the trigger 14 to a single state.

Единичным сигналом с выхода триггера 14, установленного в единичное состояние сигналом "Пуск" и единичными сигналами второго, пятого, седьмого, (n-1)-то и n - го разрядов регистра 1 указанные коды приоритета, посредством 2, 5, 7, (n-1), n групп разрядных элементов И 22 коммутируются на разрядные входы логических блоков 23₂,23₅, 23₇, 23_n-1,23_n (см. фиг. 4).Suppose that service requests are recorded in the register 1 of requests, which came to the second, fifth, seventh, (n-1) -th, n-th inputs of the register 1 of requests. Accordingly, in the registers 20 ₂ , 20 ₅ , 20 ₇ , 20 _(n-1) , 20 _n of the priority code, priority codes are recorded

The single signal from the output of the trigger 14, set to a single state by the Start signal and the single signals of the second, fifth, seventh, (n-1) -th and n-th bits of register 1, the indicated priority codes, by means of 2, 5, 7, ( n-1), n groups of bit elements AND 22 are switched to the bit inputs of logic blocks 23 ₂ , 23 ₅ , 23 ₇ , 23 _n-1 , 23 _n (see Fig. 4).

In logical blocks 23 ₂ , 23 ₅ , 23 ₇ , 23 _{n + 1} , 23 _n , the operation of bitwise comparison of priority codes is carried out, the requests of which were received at the inputs of the register 1 requests. The comparison begins with the high order, which corresponds to the first information inputs of logical blocks (according to Fig. 4). The first information inputs of the logic blocks 23 ₅ , 23 ₇ , 23 _n-1 , 23 _n receive signals "1", which are simultaneously fed to the inputs of the OR element 6 ₁ , at the inverse input of which the signal "0" is set. From the outputs of the elements OR 27 ₅ , OR 27 ₇ , OR 27 _(n-1) , OR 27 _n, single signals are fed to the second inputs of the elements AND 24 ₁ ⁵ , AND 24 ₁ ⁷ , AND 24 ₁ ^n-1 , AND 24 ₁ ⁿ and to the first inputs of the elements And 25 ₁ ⁵ , And 25 ₁ ⁷ , And 25 ₁ ^n-1 And 25 ⁿ ₁ in the corresponding logical block 23. To the second information inputs (to the first inputs of the elements And 24 ₁ ² , And 24 ₁ ⁵ , And 24 ₁ ⁷ , And 24 ₁ ^(n-1) , And 24 ₁ ⁿ ) single signals of the second most significant category of priority codes are received, respectively, in the second, fifth, seventh, (n-1) - th, n - th logical blocks 23. A single signal from the outputs of the elements And 24 ₁ ⁵ , And 24 ₁ ⁷ , And 24 ₁ ^n-1 , And 24 ₁ ⁿ will go to the moves of the corresponding OR elements 26 and to the input of the OR element 6 ₂ , at the inverse output of which the signal "0" is set. At the outputs of the elements OR 26 ₁ ⁵ , OR 26 ₁ ⁷ , OR 26 ₁ ^n-1 , OR 26 ₁ ^n, signals "1" will be set. The third information input of the logical block 23 ₇ receives a single signal. Accordingly, the signal "1" appears at the output of the AND 24 ₂ ⁷ element, which will go to the inputs of the OR 6 ₃ element, at the inverse output of which the signal "0" arrives at the second inputs of the AND 25 ₂ ⁱ elements (i = 7,2 ,. .., n), where i is the number of the logical block. Thus, the single signals in the 5th, (n-1) and n-th logical blocks 23 do not have the possibility of further "advancement" along the logical circuit to the outputs of the logical blocks 23 ₅ , 23 _n-1 , 23 _n . The "0" -th value of the code combination is supplied to the fourth information input of the logic unit 23 ₇ , respectively, the signal "0" is output at the output of the AND 24 ₃ ⁷ element, the signals "0" are received at the inputs of the OR 6 ₄ element, the signal is set at its inverse output "1" entering the second inputs of the elements AND 25 ₃ ⁱ (i = 1,2, ..., n). Because a single signal from the output of the OR 25 ₃ ⁷ element is supplied to the first input of the AND 25 ₃ ⁷ element, and a single signal from the inverse output of the OR 6 ₄ element is supplied to the second input, then “1” will appear at the output of the OR 26 ₃ ⁷ element. Etc. according to the above algorithm, a single signal will appear at the output of the seventh logical block 23 ₇ . At the direct outputs of the elements OR 6 (6 ₁ , ..., 6 _l ,) there will be an extreme code of the seventh request, which through the elements AND 8 (8 ₁ , ..., 8 _l ) goes to the information inputs (n + 1 ) - then the logical block 23 _{n + 1} . The priority code register 20 _{n + 1 is} designed to receive from the computer (operator) a code that is more priority than the one being processed, to carry out, if necessary, the operation to interrupt the processed request. Suppose that no code arrives at the register of priority code 20 _{n + 1} (we will consider the interruption of the processed request or masking below), causing the interruption of the processed request, then a single signal will appear at the output of the logical block 23 _{n + 1} . From the output of the trigger 14, set to a single state, a single signal through the delay element 32 with a delay equal to the processing time of the signal by the logical unit 23, is fed to the inputs of the elements And 29 (29 ₁ , ..., 29 _n ), And 30 ₁ and And 30 ₂ . A single signal from the output of the OR element 31 allows the passage of a single signal from the output of the seventh logical block 23 ₇ to the information inputs of the priority block 3, the signals of the job direction are sent to the inputs 4 of the mode setting (let a single signal be input to the input 4 ₁ or 4 ₂ , in this case it does not matter). This is significant when two or more single request signals are received at the information inputs of the tunable priority block 3, and a code that changes the service algorithm in the direct range (when applying a single one) is sent to the control inputs 5 (5 ₁ , ..., 5 _n ) input signal 4 ₁ 1 → 2 → ... → (n-1) → n or the reverse (when applying a single signal to input 4 ₂ n → (n-1) → ... → 2 → 1 of the sequence of priorities) . (In more detail about mode setting inputs, control inputs and signals supplied to them, will be discussed below.) A single signal of the seventh request appears Xia output unit 3 priority, then arrive at the encoder 10 inputs the output of which it will be submitted in anti-interference code through the OR gate 13 will set the flip-flop 14 to the zero state and arrive at the input 12 ₇ in register 1 requests where reset 7 discharge in The signal from the input 12 _{7 of the} register 1 of the request will go through the AND 34 ₇ element, to the second input of which the resolving unit signal 4 ₁ is supplied, and through the OR 35 ₇ element to the zero input of the trigger 36 ₇ , thereby bringing it to the zero state. Thus, on the seventh output of the register 1 of the request is fixed "0".

In the memory of register 1 of requests, the second, fifth, (n-1) and n-th requests remained fixed. Consider their further maintenance. As can be seen from FIG. 4 and based on the processing algorithm described above, in contrast to the priority codes of the fifth, (n-7) and n-th requests, the code of the second request in the high order contains "0", therefore, does not take part in the service algorithm. The priority codes of the fifth, (n-1) -th and n-th requests have the same values, therefore, at the outputs of the fifth, (n-1) -th and n-th logical blocks 23 ₅ , 23 _n-1 , 23 _n will appear the signals are “1”, and at the direct outputs of the OR 6 elements - the code corresponding to the fifth, (n-1) - th, n - for requests that through the And 8 elements will go to the information inputs (n + 1) of the logical block 23. Let priority code 20 _{n + 1} does not receive an interrupt code, then the information inputs of priority block 3 will receive the signals "1" of the fifth, (n-1) and n-th service requests. By applying the signals "1" to the inputs 4 of the job mode, you can change the processing order of simultaneously received requests, i.e. giving a signal "1" to input 4 ₁ , the order of service is established: 5th, (n-1) -th, n -th. And giving a signal "1" to input 4 ₂ : n-th, (n-1) -th, 5th. Let in our case, the signal "1" is fed to input 4 ₁ and a direct order of servicing requests is established. Inputs 5 (5 ₁ , ..., 5 _n ) of control are supplied with codes that change the service algorithm in the range of direct or reverse sequence of priorities. When directly following priorities (by supplying “1” to input 4 ₁ ): the 5th, (n-1), and nth cases of variation are possible (see table 1), and with the reverse range (set by feed "1" to the input 4 ₂ ) (see table. 2).

Let, in our case, the code applied to the control inputs 5 ₁ , ..., 5 _n defines an algorithm for servicing priorities: (n-1), n, 5. Further, the above-described algorithm for servicing requests is repeated, i.e. first, the signal of the (n-7) th request will be presented in an anti-interference code, respectively, the (n-1) th bit of the register 1 of requests will be reset. A similar procedure will be carried out with the signal of the fifth request.

 Consider the work of tunable priority block 3 in more detail.

We set the signals “1.0” at the inputs 4 ₁ , 4 ₂ of the priority block 3, respectively, which determines the service mode 1 → 2 → ... → (n-1) → n, and at the inputs 5 (5 ₁ , ... , 5 _n ) the code combination corresponding to the fifth request for servicing, thereby setting the following polling sequence: 5 → 6 → ... → (n-1) → n → 1 → 2 → 3 → 4. At 5, n- 1 and n inputs of priority block 3 single signals are output from the outputs of the second group of elements AND 29 (AND 29 ₅ , AND 29 _n-1 , AND 29 _n ) (respectively, the mask of priority is not fixed in register 20 _{n + 1} ). A single signal from the trigger output 37 through the first group of AND 38 elements (AND 38 ₅ , AND 38 _n-1 , AND 38 _n ) and the first group of OR 40 elements (OR 40 ₅ , OR 40 _n-1 , OR 40 _n ) unit signals from the inputs of block 3 priority will go to the inverse inputs of the elements And 46 (And 46 ₅ , And 46 _n-1 , And 46 _n ), which are respectively closed and a single signal will receive the output of the element OR 41. In the decoder 43, a single signal appears on the fifth output, which opens the And 45 ₅ element and closes the And 44 ₅ element. Thus, a single signal will appear at the fifth output of priority block 3.

 The signal of the second request will be served last, the code of which is the least priority in comparison with the codes of other requests, simultaneously with the second received for service.

Let the threshold value of the priority code be fixed in the register 20 _{n + 1} , and, as noted above, the value of the extreme interrupt code is applied to the inputs of the logic block 23 _{n + 1} . According to the logic of functioning of logical blocks 23 (see above), a single signal will appear at the output of block 23 _{n + 1} if the value of the priority code at its inputs is greater than the threshold recorded at the inputs of block 23 _{n + 2} and vice versa. Consider the first case. So, at the output of the logical block 23 _{n + 1} , a single signal is fixed. This signal, passing through the AND elements 30 and the OR element 31, will open the AND element 29 _i , (i-request number with an extreme code) and the request signal from this element will go to priority block 3. If a single signal is fixed at the output of the logic block 23 _{n + 2} , and at the output of the logic block 23 _{n + 1} - a zero signal, then both elements And 30 will be closed, and accordingly, element 29 _i will also be closed (i is the request number with extreme code) and the request signal does not arrive at the input of block 3 interrupts. Thus, a priority service operation can be carried out only for those requests whose priority code values exceed the level recorded in the register 20 _{n + 1} .

 After resetting the second bit of the register 1 of requests, the device returns to its initial state and is ready to serve requests that arrived during the processing of the seventh, (n-1) th, n-th, fifth and second requests.

Using a combination of essential features - general: the presence of a register of 1 requests, priority block 3, the first group of elements OR 6, the second group of elements OR 7, the first group of elements 8, encoder 10, element 13, trigger 14, element 15, n - bit registers 20 of priority, n groups of bit elements And 22, with the corresponding functional relationships and new sets of essential features: the presence of element And 18, element OR 19, (n + 1) register of priority 20 _{n + 1} , (n + 2) - x logical blocks 23, each of which contains a group of elements AND 24, a group of elements AND 25, a group of elements OR 26, an element OR 27 element OR 28, two elements 30, an element OR 31, a delay element 32 with their corresponding functional relationships, which allowed: to obtain a device with advanced functionality with the reduction hardware costs. It is not tied to a specific class of codes (in contrast to known devices), in addition, it became possible to obtain a structure that implements an algorithm for determining a request with the highest priority code, with respect to known devices, this structure is minimal, in the proposed device controllability is ensured by setting threshold, you can select a group of queries.

 The expansion of functionality, which consists in increasing the information capacity of the device, is achieved by using logical blocks 23, in addition, the use of an additional priority code register allows you to mask requests by setting a threshold value for the priority code.

 The proposed device also allows to reduce hardware costs, and therefore, to increase reliability relative to the prototype device with the same number of information inputs. A comparative analysis of hardware costs for the prototype device and the proposed device is shown in FIG. 5. When calculating the number of elements, a parallel priority device was used as the group priority block, and the matrix design of the decoders was used to open the group decoders. The request register is 20-input and each code sequence of priority values is represented in a 16-bit grid. For clarity, the heterogeneous blocks of the prototype device and the proposed device are reduced to one basis: two-input elements AND and OR. It should be noted that the proposed device has a uniform structure, which facilitates its implementation and increasing information inputs.

 Thus, the proposed device allows you to expand the functionality by introducing logical blocks and an additional register of priority code, as well as reduce hardware costs, and therefore increase the reliability of the device.

 The device can be implemented on elements of computer technology series K1533.

Claims (1)

 A variable priority device containing a request register containing a group of request inputs that are a group of request inputs of a device and two mode setting inputs, a priority block containing two mode set inputs connected to the request register mode setting inputs and n control inputs of the same name device inputs, two groups of OR elements and a group of AND elements, the outputs of the priority block are connected to the inputs of the encoder, the outputs of which are the information outputs of the device, with reset inputs request register with the inputs of the first OR element, the output of which is connected to the zero input of the trigger, the second OR element, the first and second inputs of which are inputs of the "Answer" and "Start" signals of the device, respectively, nl - bit priority registers (n - the number of request sources ), the inputs of which are inputs of the set of priority codes of the request sources of the device, n groups of bit elements AND l elements in each group, the first inputs of which are grouped together and connected to the corresponding outputs of the request register , the second inputs of all the bit elements AND groups are connected to a single output of the trigger, the outputs of the priority registers are bitwise connected to the third inputs of the bit elements AND of the corresponding groups, characterized in that the first AND element is added to it, the first input of which is connected to the output of the second OR element, the second input of the first AND element is connected to the output of the third OR element, the inputs of which are connected respectively to the query inputs of the query register, and the output of the first AND element is connected to a single input trigger, n logical blocks, the information inputs of which, respectively, of the bits and groups are connected to the outputs of the bit elements AND groups, and each logical block contains in each bit, except the first, the second elements And, the first inputs of which are corresponding (2,3 ... l - information inputs of the logical unit, the third AND elements, the first inputs of which are bitwise combined with the second inputs of the second AND elements, the fourth OR elements, the first inputs of which in each category are connected to the outputs of the second AND elements, and the second ith inputs - with outputs of the third AND elements, the output of every fourth OR element of the i-th category (where i = 1,2 ..., l-1) is connected to the combined inputs of the second and third elements AND the subsequent discharge, the output of the fourth OR element l the bit is the information output of the logical block, the first bit of each logical block contains the fifth OR element, the first input of the fifth OR element is the first information input of this logical block, the output of the fifth OR is connected to the combined second input of the second AND element and by the input of the third AND element of the second bit of this logic block, the inputs of the first OR element of the first group are connected to the first information inputs of n logical blocks, the zero output of the first OR of the first group is connected to the combined second inputs of the fifth elements OR n logic blocks, the inputs of the jth ( j = 2,3. ..l) the OR element of the first group is connected to the outputs of the second elements of the And (jl) -th discharge of n-logical blocks, and the zero output of the said OR element is connected to the combined second inputs of the third elements of the And (j-1) -th discharge of n logical blocks , the first inputs of the first group of AND elements are respectively connected to the unit outputs of the OR elements of the first group, and the second inputs are combined and connected to the output of the sixth OR element, the inputs of which are connected to the information outputs of the logical blocks, the first inputs of the second group of elements And so are connected to the information outputs of the corresponding logical blocks, the second inputs of the AND elements are combined, and the outputs are respectively connected to the information inputs of the priority block, the device also contains a second group of OR elements, the (n + 1) th and (n + 2) th identical logical blocks, information inputs of the (n + 1) -th logical block are respectively connected to the outputs of the elements of the first group, (n + 2) -th logical block, the information inputs of which are respectively connected to the outputs of the (n + 1) -th priority register, inputs which are I have the inputs of the task code of the highest priority of the device, the inputs of the first OR element of the second group are connected to the first information inputs of the (n + 1) th and (n + 2) th logical blocks, the zero output of the first OR of the second group is connected to the combined second inputs of the fifth OR elements of the (n + 1) th and (n + 2) th logical blocks, the inputs of the jth (j = 2,3 ...., l) OR element of the second group are connected to the outputs of the second AND elements (j - 1) -th category of the (n + 1) -th and (n + 2) -th logical blocks, and the zero output of the said OR element is connected to the combined second inputs of the third x elements of the And (j -1) -th category of the (n + 1) -th and (n + 2) -th logical blocks, the first inputs of the fourth and fifth AND elements are combined and connected to the information output of the (n + 1) -th logical block, the second inputs are also combined, and the second input of the fourth element is I-inverse, and connected to the information output of the (n + 2) -th logical block, the inputs of the seventh element OR are connected to the outputs of the fourth and fifth AND elements, and the output is connected to the combined second inputs of elements AND of the second group, the input of the delay element is connected to a single output of the trigger a, and the output from the third inputs of AND gates of the second group and the third inputs of the fourth and fifth elements I.

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