RU2777841C1 - Multichannel task manager arbiter - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention relates to the field of computer technology. The device contains an external input request bus IP and N external bus parameters of channels IC1, IC2, …, ICN, which consist of L groups of channel parameters, N external busses of channels IT1, IT2, …, ITN, which each contain M bits of priority rank ( the highest priority rank has the lowest zero digit, the highest priority has the highest channel ITN), the external bus of channel numbers MK, the external input of the IK mode, the first group of N external outputs of the channel indicators of the highest priority QU1, QU2, …, QUN, the second group of M external outputs of indicators of the highest priority rank in the channel OZ0, OZ1, …, OZ(M-1) and an external ready flag QF, as well as N internal request buses IZ1, IZ2, …, IZN, internal status buses S1 channels, S2, …, SN, channel readiness K1, K2, …, KN and priority U1, U2, …, UN, internal flags FK and FU, as well as parameter analysis group 1₁, 1₂, …, 1_N, each of which contains a group of comparators 2₁, 2₂, …, 2_L and element AND 3, a group of request resolution blocks 4₁, 4₂, …, 4_N, each of which contains the first group of elements AND 5₀, 5₁, …, 5_(M-1), the first group of elements OR 6₀, 6₁, …, 6_(М-1), the second group of prohibition elements AND with inverse inputs 7₁, 7₂, …, 7_(M-1), a group of blocks for analyzing the readiness of channels 8₁, 8₂, …, 8_N, each of which contains the third group of elements AND 9₁, 9₂, …, 9_(M-1) and the first OR element 10, as well as the second OR element 11, the third OR element 12, the AND element 13, the group of INE elements 14₁, 14₂, …, 14_N, the fourth group of AND elements with inverse inputs 151, 152, …, 15(N-1), multiplexer 16 and group of multiplexers 17₁, 17₂, …, 17_N.

EFFECT: providing the possibility of simultaneous selection of several channels.

1 cl, 1 dwg, 1 tbl

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer technology and can be used for arbitration in multiprocessor information processing systems for parallelizing the flow of applications.

PRIOR ART

A multi-channel priority device is known (RU No. 2415465 C2, IPC G06F 9/46, declared 06/01/2009, published 03/27/2011, Bull. No. 9), containing M channels, each of which contains a decoder, a group of elements AND, the first and second elements OR, an AND element with direct and inverse inputs, a delay element, a group of priority code inputs, a request input and a response output, moreover, in each channel, the request input is connected to the input of the delay element, the output of which is connected to the second inputs of all AND elements of the AND group of elements of its channel , the group of code inputs of the channel is connected to the group of inputs of the channel decoder, and the output of the first OR element is the output of the channel response.

This device introduced the discipline of servicing subscribers' requests with absolute priorities, which can be quickly changed when the computer system is reconfigured. The disadvantage of this device is the job only not the same priorities and the inability to simultaneously set multiple levels (ranks) of priorities in each channel.

A multi-output index of the highest unit is known (RU No. 2591017 C1, IPC H03M 7/22, G06F 13/37, G06F 9/46, declared on 07/23/2015, published on 07/10/2016, Bull. No. 19), containing a group of N external query inputs Z1, Z2, …, ZN (the input ZN has the highest priority), K cascades (K is the number of generated pointers of high units) and K groups of external outputs U pointers of the high unit, with each i-th stage (i=1, 2, …, K) contains a group of (Ni-1) OR elements 1 _i1 , l _i2 , …, l _i(Ni-1) and a group of (Ni) prohibition elements AND with one inverse input 2 _i1 , 2 _i2 , …, 2 _i(Ni) , as well as a group of (N+1-i) request inputs to the i-th stage A _i1 , A _i2 , …, A _i(N+i-1) and a group of (N+1-i ) external outputs of pointers of the highest unit of the i-th rank U _i1 , U _i2 , ..., U _i(N+1-i) (1st rank has the highest priority), each of the first (K-1) cascades, except for the last K -th cascade also contains a group of (Ni) elements AND 3 _i1 , 3 _i2 , …, 3 _i(Ni) and a group of (Ni) query outputs S _i1 , S _i2 , …, S _i(Ni) to the next (i +1)-th cascade.

The disadvantage of this device is the determination of the precedence of priorities of only one rank.

The reasons hindering the achievement of the technical result indicated below include the lack of means for analyzing the rank of multi-priority requests and indicating the rank number of the priority request.

A multi-rank request priority arbiter is known (RU No. 2649948 C1, IPC G06F 13/37, announced on May 15, 2017, published on April 5, 2018, Bull. No. 10), containing N groups of external query inputs IZ1, IZ2, ..., IZN, each of which contains M bits of the priority rank (the highest priority rank has the highest M-th bit, the highest priority has the highest group IZN), the first group of N external outputs of the indicators of the highest priority group U1, U2, ..., UN, the second group of M external outputs of the indicators of the highest priority rank in the group OZ1, OZ2, ..., OZM, a group of (N-2) elements OR 4 ₁ , 4 ₂ , ..., 4 _(N-2) , the first group of (N-1) prohibition elements AND with one inverse input 5 ₁ , 5 ₂ , …, 5 _(N-1) , a group of M elements OR-NOT 6 ₁ , 6 ₂ , …, 6 _M , the second group of (M-1) prohibition elements AND with one inverse input 7 ₁ , 7 ₂ , …, 7 _(M-1) , inverter 8 and a group of N blocks of priority analysis channels 1 ₁ , 1 ₂ , …, 1 _N , each of which contains an OR element 3 and a group of (M-1) elements AND 2 ₁ , 2 ₂ , …, 2 _{(M-1 )} , and each v-th element AND 2 _v (v=1, 2, ..., (M-1)) contains (M-v+1) inputs.

The disadvantage of this device is the lack of tools for analyzing the parameters of the required parameters of input requests and parameters of task processing channels.

The closest device for the same purpose to the claimed invention in terms of the totality of features is, taken as a prototype, the task manager arbitrator (RU No. 2749151 C1, IPC G06F 13/37, G06F 9/50 declared on 10/26/2020, published on 06/07/2021, Bull. No. 16) containing the external bus of the input request IP and N external bus parameters of the channels IC1, IC2, ..., ICN, which consist of L groups of parameters, N external busses of the channels IT1, IT2, ..., ITN, each of which contains M bits of rank priority (the highest priority rank has the lowest zero digit, the highest priority has the highest channel ITN), the first group of N external outputs of the highest priority channel indicators QUI, QU2, ..., QUN and the second group of M external outputs of the highest priority rank indicators in the channel OZ0, OZ1, …, OZ(M-1), N internal request buses IZ1, IZ2, …, IZN, each of which contains M priority bits, N bits of the internal status bus of channels S1, S2, …, SN, N bits of the internal readiness bus channels K1, K2, ..., KN and readiness flag F, and also contains a group of N blocks of parameter analysis 1 ₁ , 1 ₂ , …, 1 _N , each of which contains a group of L comparators 2 ₁ , 2 ₂ , …, 2 _L and an AND element 3, a group of N request permission blocks 4 ₁ , 4 ₂ , …, 4 _N , each of which contains the first group of M elements AND 5 ₀ , 5 ₁ , …, 5 _(M-1) , the first group of M elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1) , the second group of (M-1) prohibition elements AND with inverted inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , a group of N channels readiness analysis blocks 8 ₁ , 8 ₂ , ..., 8 _N , each of which contains the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) and the first element OR 10, as well as the second element OR 11, the second group of (N-2) OR elements 12 ₁ , 12 ₂ , …, 12 _(N-2) and the fourth group of (N-1) prohibition elements AND with one inverse input 13 ₁ , 13 ₂ , …, 13 _{(N- 1)} .

This device provides analysis of input task parameters and parameters of task processing channels. At the same time, at the outputs of the high-priority channel indicators QU1, QU2, ..., QUN, the result is formed in the form of a unitary code “1 out of N.

The disadvantage of this device is the lack of funds for simultaneous access to multiple channels of task processing.

OBJECT OF THE INVENTION

The task to be solved by the present invention is to create a task manager arbiter for multiprocessor processing systems and reduce the waiting time for service, by analyzing the parameters of the processing channels and the time the channels are busy with servicing previous requests, and providing the possibility of accessing several task processing channels.

The technical result of the invention is the expansion of the arsenal of tools for the same purpose, in terms of the possibility of analyzing the parameters of the input task and the parameters of the task processing channels, as well as providing the possibility of simultaneously selecting several channels.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved by the fact that the multi-channel task manager arbiter contains an external bus of the input request IP, which consists of L groups of task parameters, N external bus parameters of the channels IC1, IC2, ..., ICN, each of which consists of L groups channel parameters, N external busy buses of IT1, IT2, ..., ITN channels, each of which contains M bits of priority rank (the highest priority rank has the lowest zero digit, the highest priority has the highest ITN channel), the first group of N external outputs of the highest channel indicators priority QU1, QU2, ..., QUN and the second group of M external outputs of indicators of the highest priority rank in the channel OZ0, OZ1, ..., OZ(M-1), N internal request buses IZ1, IZ2, ..., IZN, each of which contains M bits of priority, N bits of the internal status bus of channels S1, S2, ..., SN, N bits of the internal bus of readiness of channels K1, K2, ..., KN and an external ready flag QF,

and also contains a group of N blocks for analyzing parameters 1 ₁ , 1 ₂ , …, 1 _N , each of which contains a group of L comparators 2 ₁ , 2 ₂ , …, 2 _L and an AND element 3, a group of N blocks for resolving requests 4 ₁ , 4 ₂ , …, 4 _N , each of which contains the first group of M elements AND 5 ₀ , 5 ₁ , …, 5 _(M-1) , the first group of M elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1) , the second group of (M-1) prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , a group of N blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 _N , each of which contains the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) and the first element OR 10, as well as the second element OR 11,

moreover, L groups of parameters of the task of the external bus of the input request IP are connected to the first groups of inputs of the corresponding comparators of the same name 2 ₁ , 2 ₂ , …, 2 _L of all N blocks of parameter analysis 1 ₁ , 1 ₂ , …, 1 _N , each of which contains the second groups the inputs of the comparators 2 ₁ , 2 ₂ , …, 2 _L are connected to the corresponding L groups of the same name of the corresponding N external busses of the parameters of the channels IC1, IC2, …, ICN, as well as in each parameter analysis block 1 ₁ , 1 ₂ , …, 1 _N outputs comparators 2 ₁ , 2 ₂ , ..., 2 _L are connected to the corresponding element I3, the outputs of which are the corresponding N bits S ₁ , S ₂ , ..., SN of the internal channel status bus,

in each of N query resolution blocks 4 ₁ , 4 ₂ , …, 4 _N the first inputs of elements AND of the first groups of M elements AND 5 ₀ , 5 ₁ , …, 5 _(M-1) are interconnected and also connected to the corresponding N bits S1, S2, ..., SN of the internal channel status bus to the channel number of the same name, and the second inputs of the AND elements of the first groups of M elements AND 5 ₀ , 5 ₁ , ..., 5 _(M-1) are connected to the corresponding M digits of the same name from N external busy buses of channels IT1, IT2, ..., ITN of the same name to the channel number, and the outputs of the elements AND of the first groups of M elements AND 5 ₀ , 5 ₁ , ..., 5 _(M-1) are the corresponding M digits of the priority rank, from the 0th by (M-1)-th bits corresponding to N internal query buses IZ1, IZ2, ..., IZN. channel number of the same name,

moreover, all M bits of the priority of each of the N internal request buses IZ1, IZ2, ..., IZN are connected to the corresponding inputs of the same name of the same name N blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N , as well as each i-th bit (i= 0, 1, ..., (M-1)) priority of each of the N internal query buses IZ1, IZ2, ..., IZN is connected to the corresponding input of the i-th element of the same name from the first group of M elements OR 6 ₀ , 6 ₁ , ..., 6 _(M-1) , while the outputs of the OR elements, starting from the first 6 ₁ to the M-th 6 _(M-1) , are connected to the first direct inputs of the same-name elements of the second group from (M-1) prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , in which the inverse inputs of the j-th element 7 _j (j=1, 2, …, (M-1)) are connected to the corresponding outputs to the elements (k=0 , 1, …, (j-1)) of the first group of M elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1) ,

inputs of the same name M, (M+1), ..., (2M-2) of each of the N blocks of channels for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N are interconnected and also connected to the corresponding outputs (M-1) elements, starting from the first to (M-1)-th element, from the second group of elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) ,

the outputs of the AND elements of the second group of (M-1) prohibition elements AND with one inverse input 7 ₁ , 7 ₂ , …, 7 _(M-1) are the corresponding (M-1) outputs OZ1, OZ2, …, OZ(M- 1) the second group of M external outputs of pointers of the highest priority rank in the channel, and the lower zero output OZ0 is the output of the OR element 6 ₀ ,

in each of N blocks 8 ₁ , 8 ₂ , ..., 8 _N readiness analysis channels (M-1) of the inputs of the block, starting from the first input to (M-1) input, are connected to the corresponding first inputs of the same-name elements AND from the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block, in which the second inputs are connected to the corresponding inputs of the block, starting from the M-th input to the (2M-2)-th input, and the outputs of the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block and the 0th input of the block are connected to the corresponding inputs of the element OR 10, the output of which is the output of the corresponding block of channels for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 _N , which are connected to N bits of the internal readiness bus of channels K1, K2, …, KN and the corresponding inputs of the second element OR 11,

additionally introduced an external input of the IK mode, an external bus of channel numbers MK, containing N digits, N digits of the internal priority bus U1, U2, ..., UN, an internal readiness flag for several channels FK and an internal readiness flag for the priority channel FU,

and also introduced the third element OR 12, element AND 13, a group of N elements INE 14 ₁ , 14 ₂ , ..., 14 _N , the fourth group of (N-1) elements AND with inverse inputs 15 ₁ , 15 ₂ , ..., 15 _(N-1) , multiplexer 16 and a group of N multiplexers 17 ₁ , 17 ₂ , ..., 17 _N ,

moreover, N bits of the external bus of MK channel numbers are connected to the inputs of the third element OR 12, and are also connected to the first inputs of the corresponding INE elements of the same name from the group 14 ₁ , 14 ₂ , ..., 14 _N , in which the second inverse inputs are connected to the corresponding N digits of the same name S1, S2, ..., SN of the internal channel status bus, and the inverse outputs of the INE elements from the group 14 ₁ , 14 ₂ , ..., 14 _N are connected to the corresponding outputs of the OR element 13, to the corresponding input of which the output of the third element OR 12 is connected,

moreover, the first (N-1) bits of the internal readiness bus of the channels K1, K2, ..., K (N-1) are connected to the direct inputs of the corresponding identical (N-1) elements AND with inverse inputs from the group 15 ₁ , 15 ₂ , ..., 15 _(N-1) , in which the inverse inputs of the h-th element 15h (h=(1, 2, ..., (N-1)) are connected to the corresponding Kp bits of the internal readiness bus of channels K1, K2, ..., KN (p =(h+1), (h+2), …, N), while the outputs (N-1) of the AND elements with inverse inputs from the group 15 ₁ , 15 ₂ , …, 15 _(N-1) are the lowest ( (N-1) bits of the internal priority bus U1, U2, ..., U(N-1), and the most significant N-th bit KN of the internal channel readiness bus is also connected to the N-th bit of the internal priority bus UN,

in addition, N bits of the external bus of MK channel numbers are connected to the first information inputs of the corresponding multiplexers of the same name from the group 17 ₁ , 17 ₂ , ..., 17 _N , in which the second information inputs are connected to the corresponding same-name N bits of the internal priority bus U1, U2, ..., UN,

moreover, the external input of the IK mode is connected to the control inputs of N multiplexers from the group 17 ₁ , 17 ₂ , ..., 17 _N and multiplexer 16, and the outputs of N multiplexers from the group 17 ₁ , 17 ₂ , ..., 17 _N are the corresponding N external outputs QU1, QU2, ..., QUN from the first group of external outputs of the channel indicators of higher priority,

the output of the OR element 13 is an internal readiness flag of several channels FK and is connected to the first information input of the multiplexer 16, and the output of the second element OR 11 is the internal flag of the priority channel FU and is connected to the second information input of the multiplexer 16, the output of which is the external ready flag QF.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. 1 shows a diagram of the proposed multi-channel task manager arbiter for input IP requests containing L=2 groups of task parameters and for N=4 processing channels, each of which contains M=3 levels (rank) of the duration of processing requests (the highest priority rank has the lowest zero digit, the highest priority has the highest 4th channel).

In FIG. 1 and the following designations are introduced in the text:

IP - external bus of the input request, containing L groups of task parameters IC1, IC2, ..., IC4 (ICN) - external bus parameters of N=4 task processing channels, containing L groups of channel parameters;

IT1, IT2, ..., IT4 (ITN) - external busy buses N=4 channels for servicing applications, each of which contains M=3 digits of the level (rank) of the duration of processing applications (the highest priority rank has the lowest zero digit, the highest priority has the highest 4 -th channel IT4 (ITN));

IZ1, IZ2, ..., IZ4 (IZN)-N=4 internal request buses, each of which contains M=3 bits of the priority rank (the highest priority rank has the lowest zero digit, the highest priority has the group IZ4 (IZN)),

IK - external mode input;

MK - external bus of channel numbers;

FK - internal readiness flag for several channels;

FU - internal priority channel readiness flag;

K1, K2, ..., K4 (KN) - N bits of the internal bus of readiness of channels for service;

S1, S2, ..., S4 (SN) - N bits of the internal channel status bus;

U1, U2, ..., U4 (QUN) - N bits of the internal priority bus;

V1, V2, ..., V4 (QVN) - N outputs of the group of elements INE 14 ₁ , 14 ₂ , ..., 14 _N ;

QU1, QU2, ..., QU4 (QUN) - the first group of N=4 external outputs of the high priority channel indicators;

QZ0, QZ1, ..., QZ2 (QZ(M-1)) - the second group of M=3 external outputs of pointers of the highest priority rank in the channel,

QF - external ready flag;

1 ₁ , 1 ₂ , …, 1 _N - group of N=4 blocks of parameter analysis;

2 ₁ , 2 ₂ , …, 2 _L - group of L=2 comparators (COMP) of each block of analysis of parameters 1 ₁ , 1 ₂ , …, 1 _N ;

3 - element AND (AND) of each block of channels for analyzing parameters 1 ₁ , 1 ₂ , …, 1 _N ; 4 ₁ , 4 ₂ , …, 4 _N - a group of N=4 request resolution blocks;

5 ₀ , 5 ₁ , …, 5 _(M-1) - the first group of M=3 elements AND (AND) of each request resolution block 4 ₁ , 4 ₂ , …, 4 _N ;

6 ₀ , 6 ₁ , ..., 6 _(M-1) - the first group of M=3 elements OR (OR);

7 ₁ , 7 ₂ , ..., 7 _(M-1) - the second group of (M-1)=2 prohibition elements AND (AND) with inverse inputs;

8 ₁ , 8 ₂ , …, 8 _N - a group of N=4 blocks of channel readiness analysis;

9 ₁ , 9 ₂ , …, 9 _(M-1) - the third group of (M-1)=2 elements AND (AND) of each block of analysis of the readiness of channels 8 ₁ , 8 ₂ , …, 8 _N ;

10 - the first element OR (OR) of each block for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N ;

11 - the second element OR (OR);

12 - the third element OR (OR);

13 - element AND (AND);

14 ₁ , 14 ₂ , …, 14 _N - group of N=4 INE elements (NAND);

15 ₁ , 15 ₂ , …, 15 _(N-1) - the fourth group of (N-1)=3 elements AND (AND) with inverse inputs;

16 - multiplexer (MUX);

17 ₁ , 17 ₂ , …, 17 _N - group of N=4 multiplexers (MUX).

The proposed multichannel task manager arbiter contains an external IP input request bus, which consists of L task parameter groups, N external channel parameter buses IC1, IC2, ..., ICN, each of which consists of L channel parameter groups, N external busses of channels IT1, IT2, ..., ITN, each of which contains M digits of the priority rank (the lowest priority rank has the lowest zero digit, the highest priority has the highest ITN channel), an external bus of MK channel numbers containing N digits, an external input of the IK mode, the first group of N external outputs of the highest priority channel indicators QU1, QU2, ..., QUN, a second group of M external outputs of the highest priority channel indicators OZ0, OZ1, ..., OZ(M-1) and an external ready flag QF, as well as N internal request buses IZ1, IZ2, ..., IZN, each of which contains M priority bits, N bits of the internal status bus of channels S1, S2, ..., SN, N bits of the internal readiness bus of channels K1, K2, KN, N bits of the internal bus n priority U1, U2, UN, internal multi-channel ready flag FK and internal priority channel ready flag FU.

The proposed multi-channel task manager arbiter also contains a group of N parameter analysis blocks 1 ₁ , 1 ₂ , …, 1 _N , each of which contains a group of L comparators 2 ₁ , 2 ₂ , …, 2 _L and an AND element 3, a group of N request resolution blocks 4 ₁ , 4 ₂ , …, 4 _N , each of which contains the first group of M elements AND 5 ₀ , 5 ₁ , …, 5 _(M-1) , the first group of M elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1) , the second group of (M-1) prohibition elements AND with inverted inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , a group of N channels readiness analysis blocks 8 ₁ , 8 ₂ , ..., 8 _N , each of which contains the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) and the first element OR 10, as well as the second element OR 11, the third element OR 12, AND element 13, a group of N elements INE 14 ₁ , 14 ₂ , ..., 14 _N , the fourth group of (N-1) AND elements with inverse inputs 15 ₁ , 15 ₂ , 15 _(N-1) , multiplexer 16 and a group of N multiplexers 17 ₁ , 17 ₂ , ..., 17 _N .

Moreover, L groups of parameters of the task of the external bus of the input request IP are connected to the first groups of inputs of the corresponding comparators of the same name 2 ₁ , 2 ₂ , …, 2 _L of all N blocks of parameter analysis 1 ₁ , 1 ₂ , …, 1 _N , each of which contains the second groups the inputs of comparators 2 ₁ , 2 ₂ , …, 2 _L are connected to the corresponding L groups of the same name of the corresponding N external busses of the parameters of the channels IC1, IC2, …, ICN. Also, in each parameter analysis block 1 ₁ , 1 ₂ , …, 1 _N , the outputs of the comparators 2 ₁ , 2 ₂ , …, 2 _L are connected to the corresponding element I3, the outputs of which are the corresponding N bits S1, S2, …, SN of the internal status bus channels.

In each of the N query resolution blocks 4 ₁ , 4 ₂ , …, 4 _N the first inputs of the AND elements of the first groups of M elements AND 5 ₀ , 5 ₁ , …, 5 _(M-1) are interconnected and also connected to the corresponding N bits S1, S2, ..., SN of the internal channel status bus to the channel number of the same name, and the second inputs of the AND elements of the first groups of M elements AND 5 ₀ , 5 ₁ , ..., 5 _(M-1) are connected to the corresponding M digits of the same name from N external buses busy channels IT1, IT2, ..., ITN of the same name to the channel number. Moreover, the outputs of the elements AND of the first groups of M elements AND 5 ₀ , 5 ₁ , ..., 5 _(M-1) are the corresponding M bits of priority rank, from the 0th to the (M-1)th bits, corresponding to N internal request buses IZ1, IZ2, …, IZN. channel number of the same name.

Moreover, all M bits of priority of each of the N internal request buses IZ1, IZ2, ..., IZN are connected to the corresponding inputs of the same name of the same name N blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N , as well as each i-th bit (i= 0, 1, ..., (M-1)) priority of each of the N internal query buses IZ1, IZ2, ..., IZN is connected to the corresponding input of the i-th element of the same name from the first group of M elements OR 6 ₀ , 6 ₁ , ..., 6 _(M-1) . At the same time, the outputs of the OR elements, starting from the first 6 ₁ to the M-th 6 _(M-1) , are connected to the first direct inputs of the same-name elements of the second group from (M-1) prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , ... , 7 _(M-1) , in which the inverse inputs of the j-th element 7 _j (j=1, 2, ..., (M-1)) are connected to the corresponding outputs of k elements (k=0, 1, ..., (j -1)) of the first group of M elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1) .

The same-named inputs M, (M+1), ..., (2M-2) of each of the N blocks of channels for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N are interconnected and also connected to the corresponding outputs (M-1) elements, starting from the first to (M-1)-th element, from the second group of elements AND with inverse inputs 7 ₁ , 7 ₂ , ..., 7 _(M-1 ).

The outputs of the AND elements of the second group of (M-1) prohibition elements AND with one inverse input 7 ₁ , 7 ₂ , ..., 7 _(M-1) are the corresponding (M-1) outputs OZ1, OZ2, ..., OZ(M- 1) the second group of M external outputs of pointers of the highest priority rank in the channel, and the lower zero output OZ0 is the output of the OR element 6 ₀ .

In each of the N blocks 8 ₁ , 8 ₂ , ..., 8 _N analysis of the readiness of the channels (M-1) of the inputs of the block, starting from the first input to the (M-1) input, are connected to the corresponding first inputs of the same-name elements AND from the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block, in which the second inputs are connected to the corresponding inputs of the block, starting from the M-th input to the (2M-2)-th input. The outputs of the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block and the 0th input of the block are connected to the corresponding inputs of the element OR 10, the output of which is the output of the corresponding block of channels for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 _N , which are connected to N bits of the internal readiness bus of channels K ₁ , K2, …, KN and the corresponding inputs of the second element OR 11.

Moreover, N bits of the external bus of MK channel numbers are connected to the inputs of the third element OR 12, and are also connected to the first inputs of the corresponding INE elements of the same name from the group 14 ₁ , 14 ₂ , ..., 14 _N , in which the second inverse inputs are connected to the corresponding N digits of the same name S1, S2, ..., SN of the internal channel status bus. The inverse outputs of the INE elements from the group 14 ₁ , 14 ₂ , ..., 14 _N are connected to the corresponding outputs of the OR 13 element, to the corresponding input of which the output of the third element OR 12 is connected.

Moreover, the first (N-1) bits of the internal readiness bus of the channels K1, K2, ..., K (N-1) are connected to the direct inputs of the corresponding identical (N-1) elements AND with inverse inputs from the group 15 ₁ , 15 ₂ , 15 _{( N-1)} , in which the inverse inputs of the h-th element 15h (h=(1, 2, ..., (N-1)) are connected to the corresponding Kp bits of the internal readiness bus of channels K1, K2, ..., KN (p=( h+1), (h+2), ..., N). In this case, the outputs (N-1) of the AND elements with inverse inputs from the group 15 ₁ , 15 ₂ , ..., 15 _(N-1) are the lowest ((N -1) by bits of the internal priority bus U1, U2, ..., U(N-1), and the senior Nth bit KN of the internal channel readiness bus is also connected to the Nth bit of the internal priority bus UN.

In addition, N digits of the external bus of the MC channel numbers are connected to the first information inputs of the corresponding multiplexers of the same name from the group 17 ₁ , 17 ₂ , ..., 17 _N , in which the second information inputs are connected to the corresponding N digits of the same name of the internal priority bus U1, U2, ..., UN.

Moreover, the external input of the IK mode is connected to the control inputs of N multiplexers from the group 17 ₁ , 17 ₂ , ..., 17 _N and multiplexer 16. The outputs of N multiplexers from the group 17 ₁ , 17 ₂ , ..., 17 _N are the corresponding N external outputs QU1, QU2 , …, QUN from the first group of external outputs of the high priority channel indicators.

The output of the OR element 13 is an internal readiness flag of several FK channels and is connected to the first information input of the multiplexer 16. The output of the second OR element 11 is the internal readiness flag of the priority channel FU and is connected to the second information input of the multiplexer 16, the output of which is the external ready flag QF.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows.

In the device, the input request on the external IP bus contains L groups of required parameters for the execution of the computational task - the amount of memory for input and output of information, the availability of appropriate programs for the algorithm for processing the computational task, and the corresponding group masks. The proposed arbiter of the task manager in N blocks of analysis of parameters 1 ₁ , 1 ₂ , …, 1 _N checks the possibility of servicing requests by comparing L groups of required parameters for a task on the external IP bus and the corresponding L groups of parameters of task processing channels arriving via buses IC1, IC2 , …, ICN. If all the parameters of the L groups by channels correspond, single values are formed in the corresponding N bits of the internal bus of the state of the channels S1, S2, ..., SN or zero values if the parameters do not match.

The device can operate in two modes, set by the external input of the IK mode - priority channel selection (IK=0) or operation with several channels (IK=1).

In the priority channel selection mode, N channels IT1, IT2, ..., ITN are received in the unitary code “1 out of M” in the priority channel selection mode corresponding to the time the channels are busy with servicing previous requests (the lowest priority rank has the lowest zero digit, the highest priority has the highest 4 ( N)-th channel IT4 (ITN)). A single value in the zero digit corresponds to the absence of service requests in the channel - the channel is ready to service the request without waiting. A single value in the most significant (M-1) digit corresponds to the maximum occupancy of the channel - the maximum waiting time for service.

In N request resolution blocks 4 ₁ , 4 ₂ , …, 4 _N , with single values of the corresponding bits of the internal status bus of the channels S1, S2, …, SN, the values from the input busses of channels IT1, IT2, …, ITN are transmitted to the corresponding internal request buses IZ1, IZ2, …, IZN or zero values at zero values of the corresponding digits of the internal status bus of channels S1, S2, …, SN.

Further, in the proposed device in the first group of elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1) and the second group of prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , the highest priority is determined (rank) of the request for the readiness of channels for service according to the values on the internal request buses IZ1, IZ2, ..., IZN and the rank number is formed in the unitary code "1 out of M" on the second group of M external outputs of the highest priority rank indicators in the channel QZ0, QZ1, …, QZ(M-1) or zero code if the parameters of all channels do not match the parameters of the input IP request.

In the channels readiness analysis blocks 8 ₁ , 8 ₂ , …, 8 _N , based on the highest priority rank in the channel QZ0, QZ1, …, QZ(M-1), the outputs form single values on the bits of the internal bus of the channels ready for servicing K1 , K2, …, KN, which are used to search for the service ready channel with the highest priority. At the same time, at the outputs of the fourth group of (N-1) elements And with inverse inputs 15 ₁ , 15 ₂ , ..., 15 _(N-1) on N bits of the internal priority bus U1, U2, ..., UN, a single signal will be set only to one output corresponding to the highest priority channel. Further, in the priority channel mode (IK=0), the value of N bits from the internal priority bus U1, U2, ..., UN through a group of multiplexers 17 ₁ , 17 ₂ , ..., 17 _N is transmitted to the first group of external outputs of the highest priority channel indicators QU1, QU2 , …, QUN. Thus, the result is generated at the outputs in the form of a unitary code "1 out of N" or a zero code if all channels are not ready to receive a request. At the same time, if there is a single value on one of the bits of the internal bus of readiness for service channels K1, K2, ..., KN, a single value of the internal priority channel readiness flag FU is formed, which is transmitted through the multiplexer 16 to the output of the external ready flag QF.

In the mode of operation with several channels (IK=1), single values are set in the corresponding bits of the channels on the external bus of the channel numbers of the MCU. In the group of elements INE 14 ₁ , 14 ₂ , ..., 14 _N , with single values of the corresponding bits of the internal bus of the state of the channels S1, S2, ..., SN, single values are formed at the outputs and a single value of the internal readiness flag of several channels FK is formed, which through the multiplexer 16 is transmitted to the output of the external ready flag QF (at IK=0). At the same time, the value from the external bus of MK channel numbers through a group of multiplexers 17 ₁ , 17 ₂ , ..., 17 _N is transmitted to the first group of external outputs of the highest priority channel indicators QU1, QU2, ..., QUN.

The proposed device works as follows.

The external bus IP receives L groups of required parameters of the input request for the execution of the computational task and from N processing channels via external buses IC1, IC2, ..., ICN-comes via L groups of channel parameters and via external busy buses N channels IT1, IT2, ..., ITNs are received in the unitary code "1 of M" values corresponding to the time the channel is busy with servicing previous requests (the highest priority rank has the lowest zero digit, the highest priority has the highest 4 (N)th channel IT4 (ITN)). These signals are fed to the corresponding inputs of the parameter analysis blocks 1 ₁ , 1 ₂ , …, 1 _N and request resolution blocks 4 ₁ , 4 ₂ , …, 4 _N .

Table 1 shows test examples of the formation of high-priority channel indicators QU1, QU2, ..., QU4 and the highest priority rank QZ0, QZ1, QZ2 for N=4 processing channels, each of which contains M=3 level (rank) of the waiting time for processing applications ( the highest priority rank has the lowest zero digit QZ0, the highest priority has the highest 4th channel QU4), as well as the value of the external ready flag QF, depending on the mode of operation of the IK. Tests No. 1-No. 5 are given for the priority channel selection mode (single-channel IK=0), tests No. 6 - No. 9 for the multi-channel operation mode (multi-channel IK=1). When forming values on the first group of external outputs of the highest priority channel indicators QU1, QU2, ..., QU4, on the second group of external outputs of the indicator of the highest priority rank in the channel QZ0, QZ1, QZ2 and the external ready flag QF in single-channel mode (IK=0) bits of the external bus of MK channel numbers and the internal readiness flag of several channels FK are involved, and in multi-channel mode (IK=1) the bits of the internal bus of priority U1, U2, ..., U4 and the internal flag of readiness of the priority channel FU are not involved.

In test No. 1 (single-channel mode IK=0), the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups of all channels IC1, IC2, ..., IC4, therefore, zero values are formed in all N=4 bits of the internal state bus of channels S1, S2 , S4 (code "0000"). At the same time, the values of unitary codes "001" are received on all input busses of channels IT1, IT2, ..., IT4, which corresponds to the absence of processed requests in the channels, but zero values are formed on the internal request buses IZ1, IZ2, ..., IZ4 (code "000" ), since zero values are set in the bits of the internal status bus of channels S1, S2, S4 (code "0000"). Further, zero values are formed at the outputs of the indicator of the highest priority rank in the channel QZ0, QZ1, QZ2 (code "000"), in the bits of the internal bus of readiness for servicing channels K1, K2, ..., K4 (code "0000") and further through the group of multiplexers 17 ₁ , 17 ₂ , ..., 17 _N (code "0000") is set on the first group of external outputs of the highest priority channel indicators QUI, QU2, ..., QU4, and the external ready flag QF=0 is set to zero, which corresponds to the prohibition of access across all channels.

In test No. 2 (single-channel mode IK=0), the values of the parameters of L groups of the input request IP correspond to the parameters of L groups of all channels IC1, IC2, ..., IC4, therefore, single values are formed in all N=4 bits of the internal state bus of channels S1, S2, ..., S4 (code "1111"). At the same time, the values of the unitary codes "001" are received on all input busses of channels IT1, IT2, ..., IT4, which corresponds to the absence of processed requests in the channels that are transmitted to the bits of all internal request buses IZ1, IZ2, ..., IZ4. Further, at the outputs of the indicator of the highest priority rank in the channel QZ0, QZ1, QZ2, a unitary code "001" is formed (a single value corresponds to the least significant zero digit QZ0=1), which further forms single values in all bits of the internal bus of readiness for service channels K1, K2 , ..., K4 (code "1111"), which corresponds to the readiness of all N=4 channels to service the request without waiting. But since the highest priority is assigned to the highest fourth channel, then in N bits of the internal priority bus U1, U2, ..., U4, a unitary code “1000” is formed (a single value corresponds to the highest channel U4=1) and at the same time a single value of the internal priority channel readiness flag is formed FU=1. Further, at a zero value of the mode input IK=0, these values are transmitted through a group of multiplexers 17 ₁ , 17 ₂ , ..., 17 _N and multiplexer 16, respectively, to the first group of external outputs of the high-priority channel indicators QU1, QU2, ..., QU4 code "1000" and a single value to the output of the external ready flag QF=1.

In test No. 3 (single-channel mode IK=0), the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups in the third channel S3=0 and correspond to the parameters in the first S1=1, second S2=1 and fourth S4=1 channels (code "1011"). At the same time, the corresponding values of unitary occupancy codes are set on the input busy buses of channels IT1, IT2, ..., IT4, which are then transferred to the internal request buses IZ1, IZ2, IZ4 and zero values code "000" are set on the bus IZ3 = 0, since the zero value set in the third bit S3=0 of the internal channel status bus. The highest readiness priority (lowest zero digit) is set on the IZ1 bus, therefore, at the outputs of the indicator of the highest priority rank in the QZ0, QZ1, QZ2 channels, a unitary code “001” is generated, which then forms a single value for the first channel K1 = 1 on the internal readiness bus channels for service. Therefore, further on the internal priority bus U1, U2, ..., U4, the code "0001" is generated, which is then transmitted to the first group of external outputs of the high-priority channel indicators QU1, QU2, ..., QU4 (a single value corresponds to the first channel QU1=1) and at the same time a single value is formed at the output of the external ready flag QF=1.

In test No. 4 (single-channel mode IK=0), the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups in the first S1=0 and fourth S4=0 channels and correspond to the parameters in the second S2=1 and third S3=1 channels (code "1011"), according to which the corresponding unitary codes "010" from the busy buses of the IT2 and IT3 channels are transmitted to the corresponding internal request buses IZ2 and IZ3 and the unitary code "010" is formed at the outputs of the indicator of the highest priority rank in the QZ0, QZ1, QZ2 channels . Further, single values are set for the second K2=1 and third K3=1 channels on the internal bus of readiness of these channels for service (code "0110"). Since the third channel has the highest priority, the code "0100" is generated on the internal priority bus U1, U2, ..., U4, which is then transmitted to the first group of external outputs of the channel indicators of the highest priority QU1, QU2, ..., QU4 (a single value corresponds to the third channel QU3=1) and at the same time a single value is generated at the output of the external ready flag QF=1.

In test No. 5 (single-channel mode IK=0), the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups in the fourth channel S4=0 and correspond to the parameters in the first S1=1, second S2=1 and third S3=1 channels (code "0111"), according to which the corresponding unitary codes from the busy buses of the IT1, IT2 and IT3 channels are transmitted to the corresponding internal request buses IZ1, IZ2 and IZ3 and the unitary code "001 » (a single value corresponds to the least significant zero digit QZ0=1). Further, single values are set for the first K1=1 and the second K2=1 channels on the internal bus of readiness of these channels for service (code "0011"). Since the second channel has the highest priority, then on the internal priority bus U1, U2, ..., U4 the code "0010" is generated, which is then transmitted to the first group of external outputs of the high-priority channel indicators QU1, QU2, ..., QU4 (a single value corresponds to the second channel QU2=1) and at the same time a single value is generated at the output of the external ready flag QF=1.

In test No. 6 (multi-channel mode IK=1), the values of the parameters of L groups of the input request IP correspond to the parameters of L groups of all channels IC1, IC2, ..., IC4, therefore single values (code "1111") are formed in all N=4 bits of the internal bus channel states S1, S2, …, S4. At the same time, single values are set on the external bus of MK channel numbers for all digits (code "1111"), which corresponds to the request for accessing all N=4 channels. In this case, a single value is formed at the output of the third element OR 12. At the same time, single values (code "1111") are also set at the outputs V1, V2, ..., V4 of the INE elements of the group 14 ₁ , 14 ₂ , ..., 14 _N . Therefore, a single value of the internal readiness flag of several channels FK=1 is formed at the output of the AND element 13. Further, since the multi-channel mode IK=1 is set, then through the group of multiplexers 17 ₁ , 17 ₂ , ..., 17 _N and the multiplexer 16 is transmitted to the first group of external outputs of high-priority channel indicators QU1, QU2, ..., QU4 code "1111" and a single value of the external ready flag QF=1, which corresponds to access through all channels.

In test No. 7 (multi-channel mode IK=1), the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups in the first S1=- and third channel S3=0 (code "1010"). At the same time, single values are set on the external bus of MK channel numbers for all digits (code "1111"), which corresponds to the request for accessing all N=4 channels. In this case, a single value is formed at the output of the third element OR 12. At the same time, the code "1010" is also set at the outputs V1, V2, ..., V4 of the INE elements of the group 14 ₁ , 14 ₂ , ..., 14 _N . Therefore, a zero value of the internal readiness flag of several channels FK=0 is formed at the output of the AND element 13. Further, since the multi-channel mode IK=1 is set, then through the group of multiplexers 17 ₁ , 17 ₂ , ..., 17 _N and the multiplexer 16 is transmitted to the first group of external outputs of high-priority channel indicators QU1, QU2, ..., QU4 code "1111" and the external ready flag QF=0 is set to zero, which corresponds to the prohibition of access on all channels.

In test No. 8 (multi-channel mode IK=1), the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups of the fourth channel S4=0 (code "0111"). At the same time, the code “0110” is set on the external bus of MK channel numbers, which corresponds to the request for accessing the second and third channels. In this case, a single value is formed at the output of the third element OR 12. At the same time, single values (code "1111") are set at the outputs V1, V2, ..., V4 of the INE elements of the group 14 ₁ , 14 ₂ , ..., 14 _N . Therefore, a single value of the internal readiness flag of several channels FK=1 is formed at the output of the AND element 13. Further, since the multi-channel mode IK=1 is set, then through the group of multiplexers 17 ₁ , 17 ₂ , ..., 17 _N and the multiplexer 16 is transmitted to the first group of external outputs of high-priority channel indicators QU1, QU2, ..., QU4 code "0110" from the external bus of MC channel numbers and a single value of the external ready flag QF=1, which corresponds to the permission to access the second and third channels.

In test No. 9 (multi-channel mode IK=1), the values of the parameters of L groups of the input request IP do not correspond to the parameters of L groups of the third channel S3=0 (code "1011"). At the same time, the code “0000” is set on the external bus of MK channel numbers, which corresponds to the absence of requests for accessing channels. In this case, a zero value is formed at the output of the third element OR 12. At the same time, single values (code "1111") are set at the outputs V1, V2, ..., V4 of the INE elements of the group 14 ₁ , 14 ₂ , ..., 14 _N . In this case, a zero value of the internal readiness flag of several channels FK=0 is formed at the output of the AND element 13. Further, since the multi-channel mode IK=1 is set, then through the group of multiplexers 17 ₁ , 17 ₂ , ..., 17 _N and the multiplexer 16 is transmitted to the first group external outputs of high-priority channel indicators QU1, QU2, ..., QU4 code "0000" from the external bus of MK channel numbers and zero value of the external ready flag QF=0, which corresponds to the prohibition of access on all channels.

Thus, in the proposed device in the priority channel selection mode (single-channel IK=0), the values of the unitary codes “1 out of N” will be set on the first group of external outputs of the high-priority channel indicators QU1, QU2, ..., QUN, and on the outputs of the second group from M external outputs of pointers of the highest priority rank in the channel OZ0, OZ1, ..., OZ(M-1) the value corresponding to the number of the highest priority rank in the unitary code "1 from M" will be set and a single value of the external ready flag QF=1 is formed. If the parameters of L groups of the input request on the IP bus do not correspond to the parameters of L groups on the buses of all processing channels IC1, IC2, ..., ICN, then on the first QU1, QU2, ..., QUN and the second OZ0, OZ1, ..., OZ(M-1 ) groups of outputs will be set to zero values, as well as the zero value of the external ready flag QF=0. In the multi-channel operation mode (multi-channel IK=1), on the first group of external outputs of the high-priority channel indicators QU1, QU2, ..., QUN, the channel code from the external bus of the MK channel numbers and a single value of the external ready flag QF=1 will be set when access is enabled to the channels.

The above information allows us to conclude that the proposed multi-channel arbiter of the task manager has the regularity of nodes and connections and corresponds to the claimed technical result - providing the ability to analyze the parameters of the input task and the parameters of the task processing channels and selects the priority channel or allows access to the specified channels in the multi-channel mode.

Claims (15)

A multi-channel task manager arbiter containing an external IP input request bus, which consists of L groups of task parameters, N external bus parameters of channels IC1, IC2, ..., ICN, each of which consists of L groups of channel parameters, N external busses of channels IT1, IT2, ..., ITN, each of which contains M bits of the priority rank (the lowest priority rank has the lowest zero digit, the highest priority has the highest channel ITN), the first group of N external outputs of the highest priority channel indicators QU1, QU2, ..., QUN and the second a group of M external outputs of indicators of the highest priority rank in the channel OZ0, OZ1, ..., OZ(M-1), N internal request buses IZ1, IZ2, ..., IZN, each of which contains M priority bits, N bits of the internal channel status bus S1, S2, ..., SN, N bits of the internal readiness bus of channels K1, K2, ..., KN and an external ready flag QF, and also contains a group of N blocks for analyzing parameters 1 ₁ , 1 ₂ , …, 1 _N , each of which contains a group of L comparators 2 ₁ , 2 ₂ , …, 2 _L and an AND element 3, a group of N blocks for resolving requests 4 ₁ , 4 ₂ , …, 4 _N , each of which contains the first group of M elements AND 5 ₀ , 5 ₁ , …, 5 _(M-1) , the first group of M elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1) , the second group of (M-1) prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , a group of N blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 _N , each of which contains the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) and the first element OR 10, as well as the second element OR 11, moreover, L groups of parameters of the task of the external bus of the input request IP are connected to the first groups of inputs of the corresponding comparators of the same name 2 ₁ , 2 ₂ , …, 2 _L of all N blocks of parameter analysis 1 ₁ , 1 ₂ , …, 1 _N , each of which contains the second groups the inputs of the comparators 2 ₁ , 2 ₂ , …, 2 _L are connected to the corresponding L groups of the same name of the corresponding N external busses of the parameters of the channels IC1, IC2, …, ICN, as well as in each parameter analysis block 1 ₁ , 1 ₂ , …, 1 _N outputs comparators 2 ₁ , 2 ₂ , ..., 2 _L are connected to the corresponding element AND 3, the outputs of which are the corresponding N bits S1, S2, ..., SN of the internal channel status bus, in each of N query resolution blocks 4 ₁ , 4 ₂ , …, 4 _N the first inputs of elements AND of the first groups of M elements AND 5 ₀ , 5 ₁ , …, 5 _(M-1) are interconnected and also connected to the corresponding N bits S1, S2, SN of the internal channel status bus to the channel number of the same name, and the second inputs of the AND elements of the first groups of M elements AND 5 ₀ , 5 ₁ , ..., 5 _(M-1) are connected to the corresponding M bits of the same name from N external buses occupancy of channels IT1, IT2, ..., ITN of the same name to the channel number, and the outputs of the elements AND of the first groups of M elements AND 5 ₀ , 5 ₁ , ..., 5 _(M-1) are the corresponding M digits of the priority rank, from 0 to ( M-1)-th bits corresponding to N internal request buses IZ1, IZ2, ..., IZN, of the same name to the channel number, moreover, all M bits of the priority of each of the N internal request buses IZ1, IZ2, ..., IZN are connected to the corresponding inputs of the same name of the same name N blocks for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N , as well as each i-th bit (i= 0, 1, ..., (M-1)) priority of each of the N internal query buses IZ1, IZ2, ..., IZN is connected to the corresponding input of the i-th element of the same name from the first group of M elements OR 6 ₀ , 6 ₁ , ..., 6 _(M-1) , while the outputs of the OR elements, starting from the first 6 ₁ to the M-th 6 _(M-1) , are connected to the first direct inputs of the same-name elements of the second group from (M-1) prohibition elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , in which the inverse inputs of the j-th element 7 _j (j=1, 2, …, (M-1)) are connected to the corresponding outputs of k elements (k=0 , 1, …, (j-1)) of the first group of M elements OR 6 ₀ , 6 ₁ , …, 6 _(M-1) , inputs of the same name M, (M+1), ..., (2M-2) of each of the N blocks of channels for analyzing the readiness of channels 8 ₁ , 8 ₂ , ..., 8 _N are interconnected and also connected to the corresponding outputs (M-1) elements, starting from the first to (M-1)-th element, from the second group of elements AND with inverse inputs 7 ₁ , 7 ₂ , …, 7 _(M-1) , the outputs of the AND elements of the second group of (M-1) prohibition elements AND with one inverse input 7 ₁ , 7 ₂ , ..., 7 _(M-1) are the corresponding (M-1) outputs OZ1, OZ2, ..., OZ(M- 1) the second group of M external outputs of pointers of the highest priority rank in the channel, and the lower zero output OZ0 is the output of the OR element 6 ₀ , in each of N blocks 8 ₁ , 8 ₂ , ..., 8 _N readiness analysis channels (M-1) of the inputs of the block, starting from the first input to (M-1) input, are connected to the corresponding first inputs of the same-name elements AND from the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block, in which the second inputs are connected to the corresponding inputs of the block, starting from the M-th input to the (2M-2)-th input, and the outputs of the third group of (M-1) elements AND 9 ₁ , 9 ₂ , ..., 9 _(M-1) of the block and the 0th input of the block are connected to the corresponding inputs of the element OR 10, the output of which is the output of the corresponding block of channels for analyzing the readiness of channels 8 ₁ , 8 ₂ , …, 8 _N , which are connected to N bits of the internal readiness bus of channels K1, K2, …, KN and the corresponding inputs of the second element OR 11, characterized in that it additionally includes an external input of the IK mode, an external bus of MK channel numbers containing N bits, N bits of the internal priority bus U1, U2, ..., UN, an internal readiness flag for several channels FK and an internal readiness flag for the priority channel FU, and also introduced the third element OR 12, element AND 13, a group of N elements INE 14 ₁ , 14 ₂ , ..., 14 _N , the fourth group of (N-1) elements AND with inverse inputs 15 ₁ , 15 ₂ , ..., 15 _(N-1) , multiplexer 16 and a group of N multiplexers 17 ₁ , 17 ₂ , ..., 17 _N , moreover, N bits of the external bus of MK channel numbers are connected to the inputs of the third element OR 12, and are also connected to the first inputs of the corresponding INE elements of the same name from the group 14 ₁ , 14 ₂ , ..., 14 _N , in which the second inverse inputs are connected to the corresponding N digits of the same name S ₁ , S ₂ , ..., SN of the internal channel state bus, and the inverse outputs of the INE elements from the group 14 ₁ , 14 ₂ , ..., 14 _N are connected to the corresponding outputs of the OR element 13, to the corresponding input of which the output of the third element OR 12 is connected, moreover, the first (N-1) bits of the internal readiness bus of the channels K1, K2, ..., K (N-1) are connected to the direct inputs of the corresponding identical (N-1) elements AND with inverse inputs from the group 15 ₁ , 15 ₂ , ..., 15 _(N-1) , in which the inverse inputs of the h-th element 15h (h=(1, 2, ..., (N-1)) are connected to the corresponding Kp bits of the internal readiness bus of channels K1, K2, ..., KN (p =(h+1), (h+2), …, N), while the outputs (N-1) of the AND elements with inverse inputs from the group 15 ₁ , 15 ₂ , …, 15 _(N-1) are the lowest ( (N-1) bits of the internal priority bus U1, U2, ..., U(N-1), and the most significant N-th bit KN of the internal channel readiness bus is also connected to the N-th bit of the internal priority bus UN, in addition, N bits of the external bus of the MC channel numbers are connected to the first information inputs of the corresponding multiplexers of the same name from the group 17 ₁ , 17 ₂ , ..., 17 _N , in which the second information inputs are connected to the corresponding same-name N bits of the internal priority bus U1, U2, ... , UN, moreover, the external input of the IK mode is connected to the control inputs of N multiplexers from the group 17 ₁ , 17 ₂ , ..., 17 _N and multiplexer 16, and the outputs of N multiplexers from the group 17 ₁ , 17 ₂ , ..., 17 _N are the corresponding N external outputs QU1, QU2, ..., QUN from the first group of external outputs of the channel indicators of higher priority, the output of the OR element 13 is an internal readiness flag of several channels FK and is connected to the first information input of the multiplexer 16, and the output of the second element OR 11 is the internal flag of the priority channel FU and is connected to the second information input of the multiplexer 16, the output of which is the external ready flag QF.

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