RU2717631C1 - Unit for single-bit range detection - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to the field of computer equipment, in particular to data processing devices, and can be used for construction of automation equipment and functional units of control systems, as well as for processing results of physical experiments. Device comprises N bits of input bus D – D1, D2, …, DN, N bits of output bus Q – Q1, Q2, ..., QN, first group of (N-2) elements OR 1₁, 1₂, ..., 1_(N-2), the second group of (N-2) elements OR 2₁, 2₂, ..., 2_(N-2) and a group of (N-2) elements AND 3₁, 3₂, ..., 3_(N-2). First group of elements OR 1₁, 1₂, ..., 1_(N-2), combined into a chain, forms an ordered group of contiguous units in the least significant bits, the second group of elements OR 2₁, 2₂, ..., 2_(N-2) generates ordered group of units in high-order bits, and in group of elements AND 3₁, 3₂, ..., 3_(N-2) checking unit values in similar bits of ordered groups of units.

EFFECT: possibility of detecting the range of single bits.

1 cl, 1 dwg, 1 tbl

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer engineering, in particular to data processing devices, and can be used to build automation equipment and functional units of control systems, as well as to process the results of physical experiments.

BACKGROUND OF THE INVENTION

A device is known for determining the number of units in an ordered binary number (RU No. 2522875, IPC Н03К 21/12, announced May 24, 2012, published July 20, 2014, Bull. No. 20), containing buffers with three states with direct and inverse resolution inputs, n bits of the input binary number, (k + 1) bits of the output binary code (k = [log ₂ n] is a smaller integer), and buffers with three states are combined into a pyramidal structure consisting of (m-1) steps (m =] log ₂ n [larger integer), and into the output block containing k buffers with three states with an inverse input of permission and k buffer ers with three states with a direct resolution input, each i-th step (i = 1, ..., (m-1)) contains (2 ⁱ -1) buffers with three states with an inverse resolution input and 2 ⁱ -1 buffers with three states with direct entry permission.

The disadvantage of this device is the determination of the number of units in an ordered binary number, and not the identification of a range of unit bits.

A device for organizing units is known (SU No. 1751746 A1, IPC G06F 7/38, 7/06, claimed on 11/26/1990, published on 07/30/1992, Bull. No. 28), containing the (n-1) th group of elements And and OR (where n is an even number, the length of the operand, n = 2K), two groups of K-bit inputs of ordered units and an n-bit output of ordered units.

The disadvantage of this device is the formation at the outputs of an ordered code, and not the identification of a range of single bits.

A device is known for determining the number of units (zeros) in a binary number (RU No. 2446442, IPC G06F 7/50, Н03К 21/00, announced April 11, 2011, published March 27, 2012, Bull. No. 9), containing a controlled inversion unit consisting of of the n-elements “EXCLUSIVE OR” (n is the number of bits of the input number), the OR elements and modules consisting of the element EXCLUSIVE OR and the element And, which are combined into groups consisting of tiers and combined into k-cascades (k =] log ₂ n [), so that each ith cascade contains g (i) = n / 2 ⁱ groups (i = 1, ..., k), each group of the ith cascade is divided into j tiers (j = 1, ..., i), at m first tier of each group i-th stage comprises a module i and each j-th stage every group i-th stage (j = 2, ..., i,) comprises (ij) module and an element "OR".

The disadvantage of this device is the determination of only the total number of units (zeros) in a binary number, and not the identification of a range of unit bits.

The index of the senior unit is known (Ugryumov EP Digital circuitry. - St. Petersburg: BHV-Petersburg, 2000. - 528 s., Fig. 2.8 p. 50-54) containing a group of elements And and a group of elements of prohibition And with one inverse the entrance. This device implements a chain diagram for transmitting a polling signal by sequential polling, starting with the highest level, and terminating further polling when the first unit is detected.

The closest device of the same purpose to the claimed invention according to the totality of features is the pointer of the senior unit adopted as a prototype (Computer circuitry. Task book: study guide. M .: NRNU MEPhI, 2012. - 240 s, Fig. 53, p. 55 -56), containing a group of OR elements combined in a chain and a group of AND inhibit elements with one inverse input.

The disadvantage of these devices is the identification of only one senior single bit.

OBJECT OF THE INVENTION

The objective of the invention is to identify the left (high) bit and the right (low) bit in the input data and fill the range of bits between them with unit values.

When processing the results of physical experiments, the device is designed to identify a range of events. In addition, the invention can be used to indicate a range of single bits.

The technical result of the invention is the expansion of functionality in terms of the ability to identify a range of single bits.

SUMMARY OF THE INVENTION

The specified technical result in the implementation of the invention is achieved by the fact that the device for detecting the range of single bits contains N bit input bus D, N bit output bus O, the first group of (N-2) elements OR 1 ₁ , 1 ₂ , ..., 1 _{(N -2)} , the second group of (N-2) elements OR 2 ₁ , 2 ₂ , ..., 2 _(N-2) and the group of (N-2) elements AND 3 ₁ , 3 ₂ , ..., 3 _{(N- 2)}

moreover, (N-2) bits D2, D3, ..., D (N-2) of the input bus D, starting from the second to the (N-1) -th bits, are connected to the second inputs of the corresponding (N-2) elements of the first group OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , starting from the first to the (N-2) -th elements, and connected to the first inputs of the corresponding (N-2) elements of the second group OR 2 ₁ , 2 ₂ , ... , 2 _N , starting from the first to the (N-2) -th element,

the first inputs of the first (N-3) elements 1 ₁ , 1 ₂ , ..., 1 _(N-3) from the first group of OR elements, starting from the first to the (N-3) th elements, are connected to the outputs of the corresponding subsequent ( N-3) elements 1 ₂ , 1 ₃ , ..., 1 _(N-2) from the first group of OR elements, starting from the second to the (N-2) -th elements, and the first input of the last (N-2) -th element 1 _(N-2) from the first group of OR elements is connected to the last Nth digit DN of the input bus D,

moreover, the second inputs (N-3) of the elements of the second group OR 2 ₂ , 2 ₃ , ..., 2 _(N-2) , starting from the second to the (N-2) -th elements, are connected to the outputs of the corresponding previous (N-3) elements 2 ₁ , 2 ₂ , ..., 2 _(N-2) from the second group of OR elements, starting from the first to the (N-3) -th elements, and the first input of the first element 2 ₁ from the second group of OR elements is connected to the first discharge D1 input bus D,

in addition, the outputs of (N-2) elements of the first group OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , starting from the first to the (N-2) -th elements, are also connected to the first inputs of the corresponding elements of the same group from (N-2) elements AND 3 ₁ , 3 ₂ , ..., 3 _(N-2) , in which the second inputs are connected to the corresponding outputs of the same name (N-2) elements of the second group OR 2 ₁ , 2 ₂ , ..., 2 _{( N-2)}

moreover, the outputs of (N-2) elements of the group of elements And 3 ₁ , 3 ₂ , ..., 3 _(N-2) are the corresponding (N-2) bits of the output bus Q, starting from the second to the (N-1) -th discharge, and the first and Nth digits of the output bus Q are connected respectively to the first and Nth digits of the input bus D.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. 1 shows a functional diagram of the proposed device for detecting the range of single bits with the number of bits N = 8 of the input bus D - D1, D2, ..., D8 (N). Table 1 shows test examples of the formation of unit ranges with the number of bits N = 8.

In FIG. 1 and the following notation is introduced in the text:

D - N bit input bus

D1, D2, ..., D8 - bits of the input bus,

O - N bit output bus,

Q1, Q2, ..., Q8 - bits of the output bus,

i is the right (least) bit having a unit value, where 1≤i≤N;

j is the left (senior) bit having a unit value, where i≤j;

1 ₁ , 1 ₂ , ..., 1 _(N-2) - the first group of (N-2) OR elements,

2 ₁ , 2 ₂ , ..., 2 _(N-2) - the second group of (N-2) elements OR,

3 ₁ , 3 ₂ , ..., 3 _(N-2) - a group of (N-2) elements I.

The proposed device for detecting the range of single bits contains N bits of the input bus D - D1, D2, ..., DN, N bits of the output bus Q - Q1, Q2, ..., QN, the first group of (N-2) elements OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , the second group of (N-2) elements OR 2 ₁ , 2 ₂ , ..., 2 _(N-2) and the group of (N-2) elements AND 3 ₁ , 3 ₂ , ..., 3 _(N-2) .

The first group of elements OR 1 ₁ , 1 ₂ , ..., 1 _{(N-2) is} designed to form an ordered group of units (in succession) in the lower digits, starting from the second digit to the j-th left (senior) digit, and the second group of elements OR 2 ₁ , 2 ₂ , ..., 2 _{(N-2) is} intended to form an ordered group of units in the higher digits, starting from the i-th right (least) digit to the (N-1) -th digit. In the group of elements And 3 ₁ , 3 ₂ , ..., 3 _(N-2) , unit values are checked in the same digits of the ordered groups of units.

Moreover, (N-2) bits D2, D3, ..., D (N-2) of the input bus D, starting from the second to the (N-1) -th bits, are connected to the second inputs of the corresponding (N-2) elements of the first group OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , starting from the first to the (N-2) -th elements, and connected to the first inputs of the corresponding (N-2) elements of the second group OR 2 ₁ , 2 ₂ , ... , 2 _N , starting from the first to the (N-2) -th element.

Moreover, the first inputs of the first (N-3) elements 1 ₁ , 1 ₂ , ..., 1 _(N-3) from the first group of OR elements, starting from the first to the (N-3) th elements, are connected to the outputs of the corresponding subsequent ( N-3) elements 1 ₂ , 1 ₃ , ..., 1 _(N-2) from the first group of OR elements, starting from the second to the (N-2) -th elements, and the first input of the last (N-2) -th element 1 _(N-2) from the first group of OR elements is connected to the last Nth digit DN of the input bus D.

Moreover, the second inputs (N-3) of the elements of the second group OR 2 ₂ , 2 ₃ , ..., 2 _(N-2) , starting from the second to the (N-2) -th elements, are connected to the outputs of the corresponding previous (N-3) elements 2 ₁ , 2 ₂ , ..., 2 _(N-2) from the second group of OR elements, starting from the first to the (N-3) -th elements, and the first input of the first element 2 ₁ from the second group of OR elements is connected to the first discharge D1 input bus D.,

In addition, the outputs (N-2) of the elements of the first group OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , starting from the first to the (N-2) -th elements, are also connected to the first inputs of the corresponding elements of the same group from (N-2) elements AND 3 ₁ , 3 ₂ , ..., 3 _(N-2) , in which the second inputs are connected to the corresponding outputs of the same name (N-2) elements of the second group OR 2 ₁ , 2 ₂ , ..., 2 _{( N-2)} .

The outputs (N-2) of the elements of the group of elements And 3 ₁ , 3 ₂ , ..., 3 _(N-2) are the corresponding (N-2) bits of the output bus Q, starting from the second to the (N-1) -th discharge, and the first and Nth digits of the output bus Q are connected respectively to the first and Nth digits of the input bus D.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows.

The proposed device allows to detect the right (junior) i bit (where 1≤i≤N) and the left (senior) j bit (where i≤j) of the input bus D, which have a unit value, and fill the range of bits between them, starting with i th to jth digits, output bus Q with unit values. In the absence of unit values in the bits of the output bus Q, zero values are set.

At the inputs of the device simultaneously received N bits of the input bus D - D1, D2, ..., DN. If only one unit value is detected in the i-th category (where 1≤i≤N, with j = i) of the input bus D at the outputs of the OR elements, starting from the first to the (i-1) th element, the first group of OR elements 1 ₁ , ..., 1 _(i-1) , single values are set and simultaneously at the outputs of the OR elements, starting from the (i-1) th to the (N-2) th elements, the second group of elements OR 2 _(i-1) , ..., 2 _(N-2) unit values are also set. In this case, two inputs of only one (i-1) -th element And 3 _{(i-1) of the} group of (N-2) elements And receive single values and therefore at the output of only one element And 3 _{(i-1) is} set to value.

With the simultaneous receipt of several unit values on the input bus D and the identification of unit values in the right (junior) i-th category and in the left (senior) j-th category (where i≤j) at the outputs of the OR elements, starting from the first to (j -1) th elements, the first group of elements OR 1 ₁ , ..., 1 _(j-1) and at the outputs of the elements OR, starting from the (i-1) th to (N-2) th elements, the second group of elements OR 2 _(i-1) , ..., 2 _(N-2) unit values are set. In this case, unit values are supplied to two inputs of AND elements, starting from the (i-1) th to the (j-1) th elements, a group of (N-2) elements AND 3 ₁ , 3 ₂ , ..., 3 _{(N -2)} and therefore, unit values are set at the outputs of the elements And 3 ( _i-1) , ..., 3 _(j-1) , which are then transferred to the bits, starting from the i-th discharge to the j-th discharge, the output bus Q - Qi , ..., Qj.

In addition, the values of the lowest first bit and the highest Nth bit of the input bus D directly go to the lowest first bit and the highest Nth bit of the output bus Q.

Thus, in the range of bits from the i-th to the j-th output bus O, unit values are set.

The proposed device operates as follows.

At the input bus of the bus D, N bits simultaneously arrive - D1, D2, ..., DN. The values from the input bus D go to the corresponding inputs of the first group of elements OR 1 ₁ , 1 ₂ , ... 1 _(N-2) and the second group of elements OR 2 ₁ , 2 ₂ , ..., 2 _(N-2) .

When identifying unit values in the right (junior) i-th category (where 1≤i≤N) and in the left (senior) j-th category, unit values are sequentially transmitted to the outputs of the OR elements, starting from the (j-1) -th to the first elements, the first group of OR elements 1 ₁ , ..., 1 _(j-1) , and are also sequentially transmitted to the outputs of the OR elements, starting from the (i-1) th to the (N-2) th elements, of the second group elements OR 2 _(i-1) , ..., 2 _(N-2) . Further, the values from the outputs of the first group 1 ₁ , 1 ₂ , ..., 1 _(N-2) and the second group 2 ₁ , 2 ₂ , ..., 2 _(N-2) of OR elements go to the inputs of the group of elements AND 3 ₁ , 3 ₂ , ..., 3 _(N-2) , the outputs of which together with the first D1 and N-th bits of the input bus D are the corresponding bits of the output bus Q.

Table 1 shows test examples of the formation of unit ranges with the number of bits N = 8.

In test No. 1, a single value occurs only in one fourth bit D4 of the input bus D, with i = 4 and j = 4. Therefore, unit values are sequentially set at the outputs of the elements of the first group 1 ₁ , ..., 1 ₃ and elements of the second group 2 ₃ , ..., 2 ₆ , which then go to the inputs of the group of elements And 3 ₁ , 3 ₂ , ..., 3 ₆ . In this case, a single value is set only on one (i-1) th element And 3 ₃ . The values from the outputs of the group of elements And 3 ₁ , 3 ₂ , ..., 3 ₆ , as well as from bits D1 and D8 of the input bus are transferred to the corresponding bits Q1, ..., Q8 of the output bus Q, on which only one unit value is set in the fourth bit Q4 .

In test No. 2, single values are received in the third D3, fourth D4, and sixth D6 bits of the input bus D. In this case, single values are detected in the right (lower) i = 3 and left (senior) j = 6 bits. Therefore, unit values are sequentially set at the outputs of the elements of the first group 1 ₁ , ..., 1 ₅ and elements of the second group 2 ₂ , ..., 2 ₆ , which then go to the inputs of the group of elements And 3 ₁ , 3 ₂ , ..., 3 ₆ . In this case, unit values are set on the elements And 3 ₂ , ..., 3 ₅ . Next, the unit values are set in bits from the third to the sixth output bus Q, which corresponds to the values i = 3 and j = 6.

In test examples No. 3 - No. 8, there are special cases when the input bus D receives single values for the last eighth digit D8 (test No. 3) or the first bit D1 (test No. 4) simultaneously with the single values in other bits of the input bus D, either only zero values come in (test No. 5), or single values come in all digits (test No. 6), or single values come only in the last eighth digit of D8 (test No. 7) or only in the first bit of D1 (test No. 8) .

In test No. 3, unit values are received in the third D3, sixth D6, seventh D7 and eighth D8 bits of the input bus D. In this case, single values are detected in the right (lower) i = 3 and left (high) j = 8 bits. Therefore, unit values are sequentially set at the outputs of all elements of the first group 1 ₁ , ..., 1 ₆ and elements of the second group 2 ₂ , ..., 2 ₆ , which then go to the inputs of the group of elements And 3 ₁ , 3 ₂ , ..., 3 ₆ . In this case, unit values are set on the elements And 3 ₂ , ..., 3 ₆ . Next, the unit values are set in the bits from the third to the seventh Q3, ..., Q7 of the output bus Q, and the unit value in the bit Q8 from the eighth bit D8 of the input bus is set, which corresponds to the values i = 3 and j = 8 of the input bus D.

In test No. 4, unit values are received in the first D1 and third D3 bits of the input bus D. In this case, unit values are detected in the right (junior) i = 1 and left (senior) j = 3 digits. Therefore, unit values are sequentially set at the outputs of the elements of the first group 1 ₁ , ..., 1 ₂ and all elements of the second group 2 ₁ , ..., 2 ₆ , which then go to the inputs of the group of elements And 3 ₁ , 3 ₂ , ..., 3 ₆ . In this case, unit values are set on two elements And - 3 ₁ , 3 ₂ . Next, the unit values are set in the second and third bits Q2, Q3 of the output bus Q, and the unit value in bit Q1 from the bit D1 of the input bus is set, which corresponds to the values i = 1 and j = 3 of the input bus D.

In test No. 5, unit values are absent in the bits of the input bus D, with i = 0 and j = 0. Therefore, zero values are set at the outputs of all elements of the first group 1 ₁ , ..., 1 ₆ and all elements of the second group 2 ₁ , ..., 2 ₆ , which then go to the inputs of the group of elements And 3 ₁ , 3 ₂ , ..., 3 ₆ , and then to the corresponding bits of the output bus Q, which also receives zero values from D1 and D8 of the bits of the input bus D. Therefore, zero values are set in all bits of the output bus Q, which corresponds to the values i = 0 and j = 0 of the input bus D.

In test No. 6, unit values are received in all bits of the input bus D. In this case, unit values are detected in the right (junior) i = 1 and left (senior) j = 8 bits. Therefore, unit values are set at the outputs of all elements of the first group 1 ₁ , ..., 1 ₆ and all elements of the second group 2 ₁ , ..., 2 ₆ , which then go to the inputs of the group of elements And 3 ₁ , 3 ₂ , ..., 3 ₆ , and then to the corresponding bits of the output bus Q, which also receives the unit values from D1 and D8 of the bits of the input bus D. Therefore, unit values are set in all the bits of the output bus Q, which corresponds to the values i = 1 and j = 8 of the input bus D.

In test No. 7, a single value comes in only one eighth bit D8 of the input bus D, with i = 8 and j = 8. Therefore, the unit values are sequentially set at the outputs of all elements of the first group 1 ₁ , ..., 1 ₃ and zero values at the outputs of all elements of the second group 2 ₃ , ..., 2 ₆ , which then go to the inputs of the group of elements And 3 ₁ , 3 ₂ , ... , 3 ₆ . In this case, zero values are set at the outputs of all elements of the group of elements And 3 ₁ , 3 ₂ , ..., 3 ₆ , and then on the corresponding bits of the output bus Q. Moreover, the zero value comes from the first bit D1 and a single value comes from the eighth bit D8 the input bus D, respectively, to the first Q1 and eighth Q8 bits of the output bus Q. Therefore, only one unit value in the eighth bit Q8 is generated on the output bus Q.

In test No. 8, a single value occurs only in the first eighth bit D1 of the input bus D, with i = 1 and j = 1. Therefore, zero values are sequentially set at the outputs of all elements of the first group 1 ₁ , ..., 1 ₃ and single values at the outputs of all elements of the second group 2 ₃ , ..., 2 ₆ , which then go to the inputs of the group of elements And 3 ₁ , 3 ₂ , ... , 3 ₆ . In this case, zero values are set at the outputs of all elements of the group of elements And 3 ₁ , 3 ₂ , ..., 3 ₆ , and then on the corresponding bits of the output bus Q. In this case, the zero value also comes from the eighth bit D8 and a single value comes from the first bit D1 the input bus D, respectively, on the eighth Q8 and the first Q1 bits of the output bus Q. Therefore, only one unit value is generated on the output bus Q in the first bit Q1.

Thus, at the outputs of the proposed device between the identified left (high) bit and the right (low) bit is formed a range of single bits.

The above information allows us to conclude that the proposed device solves the problem and corresponds to the claimed technical result.

DEVICE FOR DETECTING THE RANGE OF SINGLE BITS

Claims (6)

The device for detecting the range of single bits contains N bit input bus D, N bit output bus Q, the first group of (N-2) elements OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , the second group of (N- 2) elements OR 2 ₁ , 2 ₂ , ..., 2 _(N-2) and a group of (N-2) elements And 3 ₁ , 3 ₂ , ..., 3 _(N-2) , moreover, (N-2) bits D2, D3, ..., D (N-2) of the input bus D, starting from the second to the (N-1) -th bits, are connected to the second inputs of the corresponding (N-2) elements of the first group OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , starting from the first to the (N-2) -th elements, and connected to the first inputs of the corresponding (N-2) elements of the second group OR 2 ₁ , 2 ₂ , ... , 2 _N , starting from the first to the (N-2) -th element, the first inputs of the first (N-3) elements 1 ₁ , 1 ₂ , ..., 1 _(N-3) from the first group of OR elements, starting from the first to the (N-3) th elements, are connected to the outputs of the corresponding subsequent ( N-3) elements 1 ₂ , 1 ₃ , ..., 1 _(N-2) from the first group of OR elements, starting from the second to the (N-2) -th elements, and the first input of the last (N-2) -th element 1 _(N-2) from the first group of OR elements is connected to the last Nth digit DN of the input bus D, moreover, the second inputs (N-3) of the elements of the second group OR 2 ₂ , 2 ₃ , ..., 2 _(N-2) , starting from the second to the (N-2) -th elements, are connected to the outputs of the corresponding previous (N-3) elements 2 ₁ , 2 ₂ , ..., 2 _(N-2) from the second group of OR elements, starting from the first to the (N-3) -th elements, and the first input of the first element 2 ₁ from the second group of OR elements is connected to the first discharge D1 input bus D, in addition, the outputs of (N-2) elements of the first group OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , starting from the first to the (N-2) -th elements, are also connected to the first inputs of the corresponding elements of the same group from (N-2) elements AND 3 ₁ , 3 ₂ , ..., 3 _(N-2) , in which the second inputs are connected to the corresponding outputs (N-2) of the same name for the elements of the second group OR 2 ₁ , 2 ₂ , ..., 2 _(N-2) moreover, the outputs of (N-2) elements of the group of elements And 3 ₁ , 3 ₂ , ..., 3 _(N-2) are the corresponding (N-2) bits of the output bus Q, starting from the second to the (N-1) -th discharge, and the first and Nth digits of the output bus O are connected respectively to the first and Nth digits of the input bus D.

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