RU2703335C1 - Pyramidal structure for detecting groups of zero and single bits and determining their number - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to computer engineering, particularly to data processing devices, and can be used for constructing automation means and functional units of control systems, for analyzing properties of pseudo-random sequence generators of binary numbers, as well as for processing results of physical experiments. Device comprises N bits of input binary number which are divided into N/2 groups by two digits in group, Z stages of elements units, where Z=]log₂N[ (] [ - a greater integer), and a unit for generating device flags, wherein the first stage comprises N/2 units of elements of the first type, and each i-th stage, from the second stage to the Z-th stage, contains N/2ⁱ units of elements of the second type.

EFFECT: possibility of detecting groups of single and zero bits in binary numbers, as well as simple increase in input information capacity while reducing hardware costs.

1 cl, 3 dwg, 5 tbl

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer engineering, in particular to data processing devices, and can be used to build automation equipment and functional units of control systems, to analyze the properties of pseudorandom sequences of binary numbers, and also to process the results of physical experiments.

BACKGROUND OF THE INVENTION

A known system and method for calculating the initial zero digits and counting the initial unit digits in a digital signal processor (RU No. 2409837 C2, IPC G06F 7/74, announced July 27, 2006, published January 20, 2011, Bull. No. 2) in which the number of bits for different sizes of data words. The device expands the input data with a sign to a temporary sixty-four-bit data word. When counting zero digits, the word digits are inverted. A binary counter is used to calculate the initial bits.

The disadvantage of this device is the low speed, as well as counting only the initial zero digits and the initial single digits in a digital signal.

A device is known for determining the number of units in an ordered binary number (RU No. 2522875, IPC Н03К 21/12, announced May 24, 2012, published July 20, 2014, Bull. No. 20), containing buffers with three states with direct and inverse resolution inputs, n bits of the input binary number, (k + 1) bits of the output binary code (k = [log ₂ n] is a smaller integer), and buffers with three states are combined into a pyramidal structure consisting of (m-1) steps (m =] log ₂ n [larger integer), and to the output block containing k buffers with three states with an inverse of the resolution input and k buffers moat tristate direct enable input, wherein each stage i-i (i = 1, ..., (m-1)) contains (2 ⁱ -1) buffer tristate enable input with an inverted and a buffer 2 ⁱ -1 with three states with direct permission input.

The disadvantage of this device is the determination of the number of units in only an ordered binary number, and not in groups of zero and single digits.

A device is known for determining the number of units (zeros) in a binary number (RU No. 2446442, IPC G06F 7/50, Н03К 21/00, announced April 11, 2011, published March 27, 2012, Bull. No. 9), containing a controlled inversion unit consisting of of n-elements “EXCLUSIVE OR” (n is the number of digits of the input number), OR elements and modules consisting of an EXCLUSIVE OR element and an element that are combined into groups consisting of tiers and combined into k-cascades (k =] log ₂ n [), so that each ith cascade contains g (i) = n / 2 ⁱ groups (i = 1, ..., k), each group of the ith cascade is divided into j tiers (j = 1, ..., i), at m first tier of each group i-th stage comprises a module i and each j-th stage every group i-th stage (j = 2, ..., i,) comprises (ij) module and an element "OR".

The disadvantage of this device is the determination of only the total number of units (zeros) in a binary number, and not by groups of zero and single digits.

The reasons that impede the achievement of the technical result indicated below include the lack of funds for identifying groups and determining the number (sums) of zero and single bits in groups, and determining the total number of groups.

The closest device of the same purpose to the claimed invention according to the totality of features is, adopted for the prototype, a device for determining the number of zeros and ones by groups in a binary number (RU No. 2672626, IPC G06F 7/74, announced December 21, 2017, published November 16, 2018 , Bull. No. 32), containing N bits of the input binary number D1, D2, ..., DN, (N + 1) groups of output data G1, G1, ..., G (N + 1), the output group K the number of groups of zeros and ones , a group of (N-1) internal buses of ordered binary numbers S1, S2, ..., S _(N-1) , (N-1) cascades of ordered binary generator numbers 1 ₁ , 1 ₂ , ..., 1 _N , and each i-th cascade 1 _i (i = 1, ..., (N-1)) contains a group of (Ni) elements OR 2 ₁ , 2 ₂ , ..., 2 _(Ni) , a group of (Ni) elements XOR 3 ₁ , 3 ₂ , ..., 3 _(Ni) , a group of (N + 1-i) inputs A1, A2, ..., A (N + 1-i), a group from (Ni) outputs Q1, Q2, ..., Q (Ni) to the next stage and a group of (N + 1-i) bit outputs of the corresponding i-th internal bus S _i from the bus group S1, S2, ..., S _{(N -1)} , and also the first group of (Ni) counting units of the lowest ordered units 4 ₁ , 4 ₂ , ..., 4 _(Ni) , a group of N adders 5 ₁ , 5 ₂ , ..., 5 _N , with an inverse group of inputs of the second term, OR element with one inverse with 6 and the second block counting younger ordered units 7, each i-th adder 5 _i includes a] log ₂ (N + 3-i) [(greater integer) bits, the last N-th adder 5 _N comprises two bits, and outputs the number of groups K contain] log ₂ (N + 1) [(larger integer) digits.

The disadvantage of this device is the large hardware costs for the implementation of cascades of the ordered binary numbers shaper, counting units of the lowest ordered units and the adder group, as well as a linear increase in hardware with increasing bit depth of the input information.

OBJECT OF THE INVENTION

The objective of the invention is to develop hardware for studying the properties of generators of pseudo-random sequences of binary numbers, as well as for processing the results of physical experiments.

When analyzing generators of pseudorandom sequences of binary numbers, the device is designed to identify groups (rows) of consecutive single and zero bits, determine the number of bits in groups, the total number of groups and the total number of single and zero bits.

When processing the results of physical experiments, the device is designed to detect events (groups of single bits) and intervals between events (groups of zero bits), determine their duration and determine the total number and duration of events.

The technical result of the invention is to expand the arsenal of tools for the same purpose, in terms of the ability to identify groups of single and zero bits in binary numbers, as well as a simple increase in bit depth of input information while reducing hardware costs.

SUMMARY OF THE INVENTION

The specified technical result in the implementation of the invention is achieved by the fact that in the device of the pyramidal structure for detecting groups of zero and single bits and determining their number

contains N bits of the input binary number D1, D2, ..., DN, which are divided into N / 2 groups of two bits in a group, Z steps of blocks of elements, where Z =] log ₂ N [(] [is a larger integer), and the module the formation of the flags of the device 4,

moreover, the first stage contains N / 2 blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type, and each i-th stage, starting from the second stage to the Z-th stage, contains N / 2 ⁱ blocks of elements 2ij the second type, where i = 2, 3, ..., Z, j = 1, 2, N / 2 ⁱ ,

moreover, N bits of the input binary number D1, D2, ..., DN in groups of two bits are connected to the inputs of the blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage corresponding to the same names of the input, the outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{(N / 2-1)} (low) and outputs of even blocks of elements 1 ₂ , 1 ₄ , ..., 1 _{N / 2} (th) of the first stage are paired with the corresponding groups of the same inputs of the first and second sections, respectively the inputs of the blocks of elements 2 ₂₁ , 2 ₂₂ , ..., 2 _{2N / 4 of the} second type of the second stage, and the outputs of the odd blocks of elements 2ij (low) and the outputs are even ith blocks of elements 2ij (th) of each i-th stage, starting from the second stage to the penultimate (Z-1) -th stage, are paired with the corresponding groups of inputs of the same name, respectively, of the first and second sections of the inputs of blocks of elements 2ij of the next stages, starting from the third stages to the last Zth stage, and the outputs of the groups of the block of elements 2zj of the last Zth stage are the corresponding groups Q of the external outputs of the same name of the device of the group QK of the total number of groups of single and zero bits, groups QU of the number of unit bits in the input m binary number D1, D2, ..., DN, N of the groups QG1, QG2, ..., QGN of zero and single bits and the output QLB corresponding to the left bit of the input binary number D1,

each of the N / 2 blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage contains the element "EQUIVALENCE" 5, the first element "EXCLUSIVE OR" 6 and the element AND 7,

moreover, the pairs of bits of each of the N / 2 groups of the input binary number D1, D2, ..., DN, starting from the first bit, are connected respectively to the inputs A1 and A2 of the corresponding blocks of the same name elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type the first stage of the N / 2 groups of the same name, while the inputs A1 and A2 are connected to the first and second inputs of the “EQUIVALENCE” element 5, the first element of “EXCLUSIVE OR” 6 and the element And 7, as well as the first input A1 is connected to the output of the left bit of the LB block the first type 1, the output of the element "EQUIVALENCE" 5 is connected to the first bit g11 of the first output of the bottom group G1 bits and zero bit k0 of the output group K of the total number of groups of single and zero bits, the output of the first EXCLUSIVE OR element 6 is connected to zero bit g10 of the first output group G1 bits, with zero bit g20 of the second output group G2 bits, with the first bit k1 of the output group K to the total number of groups of unit and zero bits and with a zero bit u0 of the output group U of the number of unit bits, the output of element And 7 is connected to the first bit u1 of the output group U of the number of unit bits,

each block of elements 2ij of the second type of the second, third, ..., Zth stage contains a second EXCLUSIVE OR element 8, a DC 9 decoder, a subtractor SB 10, a group of multiplexers MX 11, a first adder SM 12, a second adder SM 13, a shift module groups SF 14, element groups AND with one inverse input 15, element groups OR 16 and the third adder SM 17,

moreover, the input 1LB of the left bit of the first section is connected to the output of the left bit LB of the block of the second type 2, all 2 ^(i-1) input groups of the first sections, starting from the first 1G1 group to the last 1G (2 ^(i-1) ) group, are connected to the first direct inputs of the elements of the corresponding groups of elements of the same name And with one inverse input 15 and are also connected to the corresponding information inputs of the group of multiplexers MX 11, the outputs of which are connected to the group of inputs of the first term of the second adder 13, in which the group of inputs of the second term is connected to the first uppp 2G1 of the second section, and the output of the second adder 13 is connected to the first group of inputs of the group shift module SF 14, in which (2 ^(i-1) -1) input groups, starting from the second group to the last group, are connected to the corresponding groups of the same name 2G the second section, starting from the second 2G2 group to the last 2G (2 ^(i-1) ) group, and the first 2 ^(i-1) outputs of the shift module of the SF 14 groups, starting from the first output to 2 ^(i-1) outputs, are connected with the second inputs of the elements of the corresponding groups of elements of the same name OR 16, the first inputs of which are connected to the corresponding one the outputs of the elements of the groups of elements And with one inverse input 15,

in addition, in blocks 2 of the second type, the input 1LB of the left bit of the first section, the input 2LB of the left bit of the second section and the least significant bit 1k0 of group 1K of the total number of groups of single and zero bits of the first section are connected to the corresponding inputs of the second element “EXCLUSIVE OR” 8, the output of which connected to the operation enable input E of the DC 9 decoder and the second input of the subtractor SB 10, the input group 1K of the total number of groups of single and zero bits of the first section is connected to the first group of inputs of the subtractor SB and to the group of inputs of the decoder DC 9, and the output the subtractor SB 10 are connected to the bus SK for setting the number of shifts, which is connected to the group of control inputs of the shift module of groups SF 14 and to the group of inputs of the first term of the first adder SM 12, in which the group of inputs of the second term is connected to the input group 2K of the total number of unit groups and zero bits of the second section, the input groups 1U and 2U of the number of unit bits of the first and second sections are connected to the input groups of the first and second terms of the third adder SM 17, the outputs of the DC 9 decoder are connected to the corresponding ravlyaetsya group multiplexers MX sample input 11 and to the second inverted input elements of the respective groups of like elements and with one inverted input 15,

moreover, the outputs of the groups of elements OR 16 are the first 2 ^(i-1) outputs of the groups of blocks 2, starting from the first G1 of the group to G (2 ^(il) ) of the group, and the outputs of the groups of the module of the shift of groups SF 14, starting from the group (2 ^{(i -1)} +1) outputs to the group of 2 ⁱ outputs are the corresponding outputs of the same group of blocks 2, starting from the group G (2 ^(i-1) +1) of outputs to the group G2 ^{i of} outputs, and in addition the outputs of the first adder SM 12 are a group of outputs K of the total number of groups of unit and zero bits of blocks 2, and the outputs of the third adder SM 17 are a group of outputs U of the number of unit bits,

the flag generation module of device 4 comprises a fourth adder SM with an inverse group of inputs 18, a fifth adder SM with an inverse group of inputs 19, a first element OR-NOT 20, a third group of elements EXCLUSIVE OR 21, a second element OR-NOT 22 and an incrementor SI 23 ,

moreover, the group of outputs U of the number of unit bits from the last Zth stage is connected to the first group of inputs of the device flag generation module 4, for which the binary number code "N" corresponding to the number of bits of the input binary number D1, D2, ..., DN, while the first group of inputs of the device flag generation module 4 is connected to the first inverse groups of inputs of the first terms of the fifth adder 19 and the fourth adder 18, while the fourth adder 18 has a second direct group of inputs of the second slug the binary code “N” is supplied and the logical unit value “1” is fed to the transfer input CI, and the output group of the fourth adder 18 is a group of external outputs QZ of the number of zero bits in the input binary number D1, D2, ..., DN and is also connected with the second direct group of inputs of the second term of the fifth adder 19, for which the logical unit value “1” is applied to the transfer input CI, and the bits of the group of outputs of the fifth adder 19 are connected to the corresponding inputs of the first element OR NOT 20 and to the first inputs of the corresponding one name elements from the third group of elements “EXCLUSIVE OR” 21, the second inputs of which are interconnected and connected to the inverse output of the CO transfer of the fifth adder 19, which is also connected to the second input of the incrementator SI 23, with the second input of the second element OR-NOT 22 and is by the external output of the flag F10 “ONE MORE ZEROES”, the output of the first element OR NOT 20 is the external output of the FE flag “SUM OF ZERO IS EQUAL TO THE SUM OF UNITS” and also connected to the first input of the second element OR-NOT 22, the output of which is the external output of the flag F01 “ WELL HER MORE UNITS ", the outputs of the third group of elements" exclusive OR "21 are connected to respective bits of the first group of inputs SI incrementer 23, the outputs of which are a group of external Q01 outputs the difference between the number of zero and one bits,

moreover, the output group QK of the total number of groups of unit and zero bits, the output group QU of the number of unit bits, the output group QZ of the number of zero bits and the output group Q01 of the difference between the number of zero and unit bits in the N bit input binary number D1, D2, ..., DN contain by] log ₂ (N + 1) [(larger integer) bits, and the output groups of zero and single bits of QGw contain by] log ₂ (N + 2-w) [(larger integer) bits, where w = 1, 2, ..., N.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. 1 is a structural diagram of the proposed device of a pyramidal structure for detecting groups of zero and single bits and determining their number. In FIG. 2 shows a functional diagram of the proposed device with N = 8 and Z = 3. In FIG. Figure 3 shows the output data formats Q at the external outputs 24 and the bit sizes of the groups for N bits of the input data at QLB = D1 = 0 and QLB = D1 = 1, for N = 4 at QLB = D1 = 0 and for N = 8 at QLB = D1 = 1. Table 1 shows the values of the output functions for blocks 1 of the first type of the first stage. Table 2 shows examples of combining groups of consecutive single or zero bits and forming the total number of groups K at N = 4 for blocks 2 _{2 of the} second stage. Table 3 shows examples of combining groups of consecutive single or zero bits and forming the total number of groups K at N = 8 for blocks 2 _{3 of the} third stage. Table 4 shows the function values for the decrement flag FD, adjustments to the sum code K of the total number of groups and the amount of shift code on the SK bus. Table 5 shows the function values for generating the external flags FE, F10, and F01.

In FIG. 1, FIG. 2, FIG. 3, the following notation is used in the tables and in the text:

N is the number of bits of the input binary number,

D1, D2, ..., DN - bits of the input binary number,

Z is the number of steps, where Z =] log ₂ N [(] [is a larger integer),

And - the inputs of the blocks of elements 1 of the first type of the first stage,

G - groups of single and zero bits,

G ⁰ - groups of zero bits,

G ¹ - group of single bits,

K is a group of the total number (sum) of groups of single and zero bits,

U is a group of the quantity (sum) of unit bits,

LB is the left bit,

DC - decoder (demultiplexer),

E - input permit work,

MX - a group of multiplexers (switches),

SB - subtractor (decrementor),

SI - increment (adder),

SM - adder

CI - adder transfer input,

СО - adder transfer output,

FD - flag decrement code sum 1K the number of groups of the first section,

SF is the group shear modulus,

SK is a bus for setting the number of shifts,

1LB, 1G, 1K, 1U - groups of inputs of the first sections of blocks of elements 2ij of the second type,

i is the number of the stage, where i = 2, 3, ..., Z,

j is the block number of elements in the i-th step, where j = 1, 2, ..., N / 2 ⁱ ,

1k0 - the lowest zero bit of group 1K of the total number of groups of single and zero bits of the first section,

2LB, 2G, 2K, 2U - groups of inputs of the second sections of the blocks of elements 2ij of the second type,

QLB, QG, QK, QU - groups of device outputs,

QU - group of outputs of the quantity (sum) of zero bits,

QZ - group of outputs of the quantity (sum) of zero bits,

ZU - the bus of the sum QZ + not QU + 1,

Q01 - group of outputs of the difference between the number of zero QZ and unit bits,

F0 - flag “ALL ZERO”,

F01 - flag “ZERO MORE UNITS”,

FE - flag “SUM OF ZEROES IS EQUAL TO SUMME UNITS”,

F10 - flag “UNITS MORE ZEROES”,

1 ₁ , 1 ₂ , ..., 1 _{N / 2} - N / 2 blocks of elements of the first type of the first stage,

2ij - blocks of elements of the second type of the i-th stage, where i = 2, 3, ..., Z, j = 1, 2, ..., N / 2 ⁱ ,

3 - external inputs of the device,

4 - module flags the device

5 - element "EQUIVALENCE (SIGNIFICANCE)" (XNOR),

6 - the first element "EXCLUSIVE OR" (XOR),

7 - element And

8 - the second element of "EXCLUSIVE OR" (XOR),

9 - decoder (demultiplexer) DC,

10 - subtractor (decrementor) SB,

11 - group of multiplexers (switches) MX,

12 is the first adder SM,

13 - second adder SM,

14 - shear modulus of groups SF,

15 - groups of elements And with one inverse input,

16 - groups of elements OR,

17 - the third adder SM,

18 - the fourth adder SM with an inverse group of inputs,

19 - fifth adder SM with an inverse group of inputs,

20 - the first element OR-NOT,

21 - the third group of elements "EXCLUSIVE OR" (XOR),

22 - the second element OR NOT,

23 - increment (adder) SI,

24 - external outputs of the device.

The proposed device of the group structure of the pyramidal structure for detecting groups of zero and single bits and determining their number contains N bits of the input binary number D1, D2, ..., DN, which are divided into N / 2 groups of two bits in the group, Z steps of blocks of elements, where Z =] log ₂ N [(] [is a larger integer), and the flag generation module of device 4. wherein the first stage contains N / 2 blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type, and each i- th stage from the second stage to the Z-th stage comprises N / 2 ⁱ blocks 2ij elements of the second type, de i = 2, 3, ..., Z, j = 1, 2, N / 2 ^i.

Moreover, N bits of the input binary number D1, D2, ..., DN in groups of two bits are connected to the inputs of the corresponding blocks of the elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage of the same name.

The outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{(N / 2-1)} (low) and the outputs of the even blocks of elements 1 ₂ , 1 ₄ , ..., 1 _{N / 2} (th) of the first stage are paired with the corresponding groups the inputs of the same name, respectively, of the first and second sections of the inputs of the blocks of elements 2 ₂₁ , 2 ₂₂ , ..., 2 _{2N / 4 of the} second type of the second stage.

The outputs of the odd blocks of elements 2ij (woofer) and the outputs of the even blocks of elements 2ij (th) of each i-th stage, starting from the second stage to the penultimate (Z-1) -th stage, are paired with the corresponding groups of inputs of the same name, respectively, of the first and second sections the inputs of the blocks of elements 2ij of subsequent stages, starting from the third stage to the last Z-th stage.

The outputs of the groups of the block of elements 2zj of the last Z-th stage are the corresponding groups Q of the external outputs of the same name of the device of the group QK of the total number of groups of single and zero bits, groups QU of the number of unit bits in the input binary number D1, D2, ..., DN, N of the groups QG1, QG2 , ..., QGN of zero and single bits and the output QLB corresponding to the left bit of the input binary number D1.

Each of the N / 2 blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage contains the element "EQUIVALENCE" 5, the first element "EXCLUSIVE OR" 6 and the element AND 7.

Moreover, the pairs of bits of each of the N / 2 groups of the input binary number D1, D2, ..., DN, starting from the first bit, are connected respectively to the inputs A1 and A2 of the corresponding blocks of the same elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type the first stage of the same group N / 2. The inputs A1 and A2 of the blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage are connected to the first and second inputs of the element "EQUIVALENCE" 5, the first element "EXCLUSIVE OR" 6 and the element And 7. In addition the first input A1 is connected to the output of the left bit LB of the block of the first type 1. The output of the “EQUIVALENCE” element 5 is connected to the first bit g11 of the first output group G1 bits and zero bit k0 of the output group K of the total number of groups of single and zero bits. The output of the first EXCLUSIVE OR element 6 is connected to the zero bit g10 of the first output group G1 bits, with the zero bit g20 of the second output group G2 bits, with the first bit k1 of the output group K of the total number of groups of single and zero bits and with the zero bit u0 of the output group U is the number of unit bits. The output of the element And 7 is connected to the first bit u1 of the output group U of the number of unit bits.

Each block of elements 2 _{ij of the} second type of the second, third, ..., Z-th stage contains a second EXCLUSIVE OR element 8, a DC 9 decoder, a subtractor SB 10, a group of multiplexers MX 11, a first adder SM 12, a second adder SM 13, a module shift groups SF 14, element groups AND with one inverse input 15, element groups OR 16 and the third adder SM 17.

Moreover, the input 1LB of the left bit of the first section is connected to the output of the left bit LB of the block of the second type 2. All 2 ^(i-1) input groups of the first sections, starting from the first 1G1 group to the last 1G (2 ^(i-1) ) group, are connected to the first direct inputs of the elements of the corresponding groups of elements of the same name And with one inverse input 15 and are also connected to the corresponding information inputs of the group of multiplexers MX 11, the outputs of which are connected to the group of inputs of the first term of the second adder 13. The group of inputs of the second term of the second adder 13 is connected to the first group 2G1 of the second section.

The output of the second adder 13 is connected to the first group of inputs of the group shift module SF 14, in which (2 ^(i-1) -1) input groups, starting from the second group to the last group, are connected to the corresponding 2G groups of the second section, starting from the second 2G2 groups to the last 2G (2 ^(i-1) ) group.

The first 2 ^(i-1) outputs of the shift module of the groups of SF 14, starting from the first output to 2 ^(i-1) outputs, are connected to the second inputs of the elements of the corresponding groups of elements OR 16, the first inputs of which are connected to the corresponding outputs of the elements of the groups of elements And with one inverse input 15.

In addition, in blocks 2 of the second type, the input 1LB of the left bit of the first section, the input 2LB of the left bit of the second section and the least significant bit 1k0 of group 1K of the total number of groups of single and zero bits of the first section are connected to the corresponding inputs of the second EXCLUSIVE OR element 8, output which is connected to the work enable input E of the DC 9 decoder and the second input of the subtractor SB 10. The input group 1K of the total number of groups of single and zero bits of the first section is connected to the first group of inputs of the subtractor SB and to the group of inputs of the DC 9 decoder.

The outputs of the subtractor SB 10 are connected to the bus SK for setting the number of shifts, which is connected to the group of control inputs of the shift module of groups SF 14 and to the group of inputs of the first term of the first adder SM 12. The group of inputs of the second term of the first adder SM 12 is connected to the input group 2K of the total number groups of single and zero bits of the second section, input. Groups 1U and 2 U of the number of unit bits of the first and second sections are connected to the input groups of the first and second terms of the third adder SM 17. The outputs of the DC 9 decoder are connected to the corresponding control inputs of the sample of the multiplexer group MX 11 and to the second inverse inputs of the elements of the corresponding groups of elements of the same name with one inverse input 15.

Moreover, the outputs of the groups of elements OR 16 are the first 2 ^(i-1) outputs of the groups of blocks 2, starting from the first G1 of the group to G2 ^(i-1) ) of the group, and the outputs of the groups of the module of the shift of groups SF 14, starting from the group (2 ^{(i -1)} +1) outputs to the group of 2 ⁱ outputs are the corresponding outputs of the same group of blocks 2, starting from the group G (2 ^(i-1) +1) of outputs to the group G2 ^{i of} outputs. In addition, the outputs of the first adder SM 12 are a group of outputs K of the total number of groups of unit and zero bits of blocks 2, and the outputs of the third adder SM 17 are a group of outputs U of the number of unit bits.

The flag generation module of device 4 comprises a fourth adder SM with an inverse group of inputs 18, a fifth adder SM with an inverse group of inputs 19, a first element OR-NOT 20, a third group of elements “EXCLUSIVE OR” 21, a second element OR-NOT 22 and an incrementor SI 23 .

Moreover, the group of outputs U of the number of unit bits from the last Zth stage is connected to the first group of inputs of the device flag generation module 4, for which the binary number code "N" corresponding to the number of bits of the input binary number D1, D2, ..., DN The first group of inputs of the device flag generation module 4 is connected to the first inverse input groups of the first terms of the fifth adder 19 and the fourth adder 18. In this case, the fourth adder 18 has a binary number code “N” for the second direct group of inputs of the second term, and the input CI transfer of which the value of the logical unit is "1".

The group of outputs of the fourth adder 18 is a group of external outputs QZ of the number of zero bits in the input binary number D1, D2, ..., DN and is also connected to the second direct group of inputs of the second term of the fifth adder 19. The value of the logical unit " one". The bits of the group of outputs of the fifth adder 19 are connected to the corresponding inputs of the first element OR NOT 20 and to the first inputs of the corresponding elements of the same name from the third group of elements “EXCLUSIVE OR” 21.

The inverse CO transfer output of the fifth adder 19 is connected to the second inputs of the elements from the third group of EXCLUSIVE OR elements 21 connected to each other, and is also connected to the second input of the SI 23 incrementor, with the second input of the second OR-NOT 22 element and is an external flag output F10 "ONE MORE ZEROES."

The output of the first OR-NOT 20 element is the external output of the FE flag “SUM OF ZERO IS EQUAL TO THE AMOUNT OF UNITS” and is also connected to the first input of the second element OR-NOT 22. The output of the second OR-NOT 22 element is the external output of the flag F01 “ZERO MORE UNITS”. The outputs of the third group of elements “EXCLUSIVE OR” 21 are connected to the corresponding bits of the first group of inputs of the incrementator SI 23, the outputs of which are a group of external outputs Q01 of the difference between the number of zero and single bits.

In addition, the output group QK of the total number of groups of unit and zero bits, the output group QU of the number of unit bits, the output group QZ of the number of zero bits and the output group Q01 of the difference between the number of zero and unit bits in the N bit input binary number D1, D2, ..., DN each contain] log ₂ (N + 1) [(larger integer) digits. The output groups of the zero and single bits of QGw contain each] log ₂ (N + 2-w) [(larger integer) bits, where w = 1, 2, ..., N.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows.

The input N bit unsigned binary number is divided into N / 2 groups, two bits in a group and fed in pairs to the inputs A1 and A2 to the corresponding N / 2 blocks of the same name elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage .

In the blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage, in accordance with Table 1, for each pair of bits A1, A2, the binary codes of groups G1 and G2 are generated corresponding to the number of consecutive single or zero bits in the group, the binary code K of the total number of groups and the binary code U of the total number of single bits are also formed. In addition, the value of the left bit A1 is also transmitted to the outputs LB of the blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2} . Moreover, if LB takes a zero value LB = 0, then the first group of bits contains zero bits G1 ⁰ , and if LB takes a single value LB = 1, then the first group of bits contains single bits G1 ¹ . In this case, subsequent groups of unit bits G ¹ and zero bits G ⁰ alternate. The binary codes of groups G1 can take values 0, 1 or 2, and the binary codes of groups G2 can take values 0 or 1. The binary codes K of the total number (sum) of groups take values 1 or 2. The binary codes U of the total number of single bits can take values 0, 1 or 2. These code values are generated on the “EQUIVALENCE” element (XNOR) 5, the first element “EXCLUSIVE OR” (XOR) 6 and the element And 7 and are transmitted to the corresponding outputs of the blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage.

Further, the values of the codes for groups from the outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{(N / 2-1)} (low) and from the outputs of the even blocks of elements 1 ₂ , 1 ₄ , ..., 1 _{N / 2} (Th) of the first stage are transferred in pairs to the same groups of inputs of the first and second sections of the inputs of blocks 2 ₂₁ , 2 ₂₂ , ..., 2 _{2N / 4 of the} second type of the second stage, respectively. Then, the values from the outputs of the odd blocks of elements 2ij (woofer) and from the outputs of the even blocks of elements 2ij (th) of each i-th stage, starting from the second stage to the penultimate (Z-1) -th stage, are transmitted in pairs to the corresponding groups of inputs of the same name, respectively the first and second sections of the inputs of the blocks of elements 2ij of the next stages, starting from the third stage to the last Z-th stage. In FIG. 1 is a structural diagram of combining blocks of step elements.

In each block of elements 2ij of the second type, the binary values of neighboring groups of inputs of inputs of zero G ⁰ bits or groups of inputs of individual G ¹ bits of the first 1G and second 2G sections are combined. Possible options for combining groups for the second stage are shown in Table 2 and for the third stage are shown in Table 3. On the second adders 13, the binary codes of the senior group of the first sections 1G and the lower group 2G1 of the second sections are summed up, while the consecutive single or zero bits match in them . The leading group of the first section 1G is transmitted to the group of inputs of the first term of the second adders 13, with single or zero bits in consecutive sections coming in succession, or a zero binary code if one group contains single bits G ¹ and the other group contains zero bits G ⁰ . The input group of the second term always receives the binary code value of the lower first group 2G1 of the second section. In tables 2 and 3, the shading indicates the groups summed on the second adders 13.

Groups of single bits G ¹ and zero bits G ^{0 are} sequentially alternated, while the value of the first group G1 is set by the left bit LB. To determine the type of value of single or zero bits in the senior group of the first sections, it is enough to analyze the value of the left bits 1LB of the first sections and the value of the lowest zero bit 1k0 of group 1K of the total number of groups of single and zero bits of the first section, which indicates the parity of the number of groups (at 1k0 = 0 ) and, accordingly, the heterogeneity of the first and senior groups or the odd number of groups (with 1k0 = 1) and, accordingly, the same type of the first and senior groups (tables 2 and 3).

To identify groups (rows) of consecutive single and zero bits and to combine the same type groups of neighboring sections, the values of the inputs of the left bits 1LB and 2LB of the first and second sections, respectively, and the value of the lowest zero bit 1k0 of group 1K of the total number of groups of single and zero bits of the first section are analyzed. If in adjacent sections in the senior group of the first section 1G and in the younger group of the second section 2G1 consecutive single G ¹ or zero G ⁰ bits are output at the output of the second EXCLUSIVE OR element 8 in accordance with table 4, the decrement flag FD is generated. With a single value of the decrement flag FD = 1, a unit is subtracted from the sum code 1K of the number of groups of the first section on the subtractor SB (decrementor) 10, at the output of which a code of the number of shifts arriving at the bus SK is generated. At the same time, the code value of group 1K of the total number of groups of single and zero bits of the first section is transmitted to the sampling inputs of the DC decoder (demultiplexer) 9. If the decrement flag FD = 0 is zero, the operation decryptor DC (demultiplexer) 9 is prohibited from the work enable input E and zero values are generated at all outputs of it. With a single value of the decrement flag FD = 1, the unitary code “1 of 2 ^(i-1) ” is generated at the outputs of the DC decoder (demultiplexer) 9, by which the binary code of the senior group of the first section 1G is transmitted to the outputs of the MX multiplexer group (switches) 11, which goes to the group of inputs of the first term of the second adders 13.

In the modules SF shift groups 14 to the inputs of the younger group, the value is transmitted from the outputs of the second adders 13, and the subsequent senior groups of inputs, starting from the second group, receive the corresponding groups of the same name 2G of the second sections. In the modules SF shift groups 14, the groups of zero G ⁰ and unit G ¹ bits are shifted by the value of the shift code on the SK bus towards the higher groups and the lower groups of zero values are entered into the shifted bits.

The values of zero G ⁰ and unit G ¹ bits of the 1G groups of the first sections are supplied to the first direct inputs of the corresponding groups of elements AND with one inverse input 15, to the second inverse inputs of which the values from the corresponding outputs of the same name of the DC decoder (demultiplexer) 9 are received. Thus, the outputs And element groups with one inverse input 15, the values of the 1G groups of the first sections or zero values are transmitted, which are fed to the first inputs of the corresponding element groups of the same name OR 16, the second inputs of which receive values from the outputs of the corresponding groups of the same name module SF shift groups 14.

In all steps in each block of elements 2ij, the outputs of the group of elements OR 16 are the corresponding lower-order groups of outputs G1, G2, ..., G2 ^(i-1) , and the outputs of the highest groups of the module shift module SF 14 of the corresponding high-order groups of outputs G (2 ^{( i-1)} +1), G (2 ^(i-1) +2), ..., G2 ⁱ . In addition, the first adders 12 summarize the corrected group code value of the total number of groups SK = 1K-FD of the first section and the 2K code value of the total number of groups of single and zero bits of the second section and form the sum code of the groups K, which is transmitted to the corresponding group of outputs of the block K elements 2ij. Also, at the third adders 17, the groups of the number (sum) of unit bits 1U of the first sections and 2U of the second sections are summed up and a binary code of the quantity (sum) of unit bits U is generated at the output and transmitted to the corresponding output group U of the element block 2ij.

The outputs of the groups of the last Z-th stage are the corresponding groups Q of the external device outputs of the same name - groups QK of the total number (sum) of groups of single and zero bits, groups QU of the number (sum) of unit bits in the input binary number D1, D2, ..., DN, N groups QG of zero and single bits and the output QLB corresponding to the left bit of the input binary number D1.

In addition, the output of the QU group of the number (sum) of unit bits from the last Zth stage goes to the first group of inputs of the device flag generation module 4, to the second group of inputs of which the binary code “N” corresponding to the number of bits of the input binary number D1, D2, ..., DN. The value of the QU code of the quantity (sum) of unit bits goes to the first inverse group of inputs of the first term of the fourth adder 18, and the binary code “N” comes to the second direct group of the second term of the fourth adder 18 and the unit value CI = 1 is transferred to the transfer input CI. Thus, the output of the fourth adder 18 generates the value of the binary code QZ corresponding to the number (sum) of zero bits in the input number - QZ = N + not QU + 1 (table 5), which is transmitted to the corresponding group of outputs QZ of flag module 4.

At the same time, the value of the QU code of the quantity (sum) of unit bits is also transmitted to the first inverse group of inputs of the first term of the fifth adder 19, the value of the binary code QZ corresponding to the number (sum) of zero bits is received to the second direct group of the second term of the fifth adder 19, and to the transfer input CI of which the unit value CI = 1 arrives. At the same time, at the output of the fifth adder 19, the value of the binary code ZU is generated, which corresponds to the difference between the number (sums) of zero QZ and single QU bits: ZU = QZ + not QU + 1 and the output transfer of CO is formed (table 5). All output bits of the fifth adder 19 are supplied to the corresponding inputs of the first OR-NOT 20 element, the output of which forms the flag F0 "ALL ZERO", which takes the unit value F0 = 1 if all the bits have a zero value, which corresponds to the equality of terms when the number of units QU and zero QZ bits are equal. The value of the flag F0 "ALL ZERO" is transmitted to the corresponding output of the device as the output flag FE "SUM OF ZERO IS EQUAL TO SUM OF UNITS". The output CO transfer of the fifth adder 19 assumes a unit value CO = 1 when the quantity (sum) of zero QZ bits is not less than (greater than or equal to) the number (sum) of unit QUs and takes a zero value CO = 0 when the number (sum) of zero QZ bits is less than the number (sums) of unit QU. Therefore, in accordance with Table 5, the output flags are generated: the F10 flag “ONE MORE THAN ZERO” as F10 = not СО and the F01 flag “ZERO MORE THAN ONE” as F01 = not (not СО OR F0), the value of which is generated on the second OR-NOT element 22.

At the same time, all output bits of the fifth adder 19 go to the first inputs of the corresponding elements of the same name from the third group of XOR elements 21, the second inputs of which are interconnected and connected to the inverted output of the CO transfer of the fifth adder 19. In this case, at a single transfer value СО = 1, the direct values of the bits from the outputs of the fifth adder 19 are transmitted to the outputs of the third group of EXCLUSIVE OR (XOR) 21 elements, and at zero transfer value CO = 0, inverse values are transmitted. Next, on the incrementator (adder) SI 23 with a unit value not CO = 1, which is fed to the transfer input CI and corresponds to the case when the number (sum) of zero QZ bits is less than the number (sum) of single QU, the value of the ZU code is converted as an addition to N, into the code of the difference between the number of zero and single bits, and when the value is zero, not СО = 0 is transmitted without conversion (table 5). Further, from the outputs of the incrementer (adder) SI 23, the value is transmitted to the corresponding group of outputs Q01 of the difference between the number (sums) of zero and single bits. In table 5, in the subscript characters the form of data representation is indicated - binary (2) or decimal (10). In FIG. Figure 3 shows the output data formats Q at the external outputs 24 and the bit sizes of the groups for N bits of the input data at QLB = D1 = 0 and QLB = D1 = 1, for N = 4 at QLB = D1 = 0 and for N = 8 at QLB = D1 = 1.

The proposed device operates as follows.

The external inputs of device 3 receives N bits of the unsigned input binary number D1, D2, ..., DN, which are divided into N / 2 groups of two bits in the group. The least significant bit D1 is the first left bit of the input binary number. In pairs, input discharges enter the inputs A1 and A2 into the corresponding N / 2 blocks of the same name elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage. The values from inputs A1 and A2 are supplied to the first and second inputs of the “EQUIVALENCE” element (XNOR) 5, the first element of the “EXCLUSIVE OR” (XOR) 6 and the element And 7.

In the blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage for each pair of input bits A1, A2, in accordance with table 1, the values of binary codes of groups G1 and G2 corresponding to the number of consecutive a group of single or zero bits, and a binary code K of the total number of groups and a binary code U of the total number of unit bits are also generated. For example, for the input number A1, A2 = 00, since the left bit LB and both bits A1 and A2 take zero values, the following values are generated at the block outputs: LB = 0, G1 ⁰ = 10 ₂ = 2 ₁₀ , G2 ¹ = 0 , K = 01 ₂ = 1 ₁₀ , U = 00 ₂ = 0 ₁₀ , and for the input number A1 A2 = 10 the following values are formed: LB = 1, G1 ¹ = 01 ₂ = 1 ₁₀ , G2 ⁰ = 1, K = 10 ₂ = 2 ₁₀ , U = 01 ₂ = 1 ₁₀ .

Further, the values from the outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{(N / 2-1)} (low) and the outputs of the even blocks of elements 1 ₁ , 1 ₄ , ..., 1 _{N / 2} (Th) of the first stage are received in pairs to the corresponding groups of the inputs of the same name, respectively, of the first and second sections of the inputs of the corresponding blocks 2 ₂₁ , 2 ₂₂ , ..., 2 _{2N / 4 of the} second stage (Fig. 1).

In each block of elements 2 _{2j of the} second type of the second stage, the values of the inputs of the left bits 1LB of the first section and the 2LB of the second section and the value of the lowest zero bit 1k0 of group 1K of the total number of groups of single and zero bits of the first section and the output of the second EXCLUSIVE OR element 8 are analyzed, 8 in accordance with table 4, the decrement flag FD is generated. If the decrement flag FD = 0 is zero, the DC decoder (demultiplexer) 9 is disabled and zero values are generated at all outputs. With a single decrement flag FD = 1, a unitary code “1 of 2 ^(i-1) ” is generated at the outputs of the DC decoder (demultiplexer) 9, by which the binary code of the senior group 1G of the first section is transmitted to the outputs of the MX multiplexer group (switches) 11, which goes to the group of inputs of the first term of the second adders 13. For example, in accordance with table 2, for the values of the inputs 1k0 = 0, 1LB = 0 and 2LB = 0 (zero line No. = 0 of table 2 when the first section contains two groups (1k0 = 0) and the first lower groups of the first 1G1 ⁰ and second 2G1 ⁰ sections contain zero bits) the decrement flag FD = 0 is generated (table 4), since the second group 1G2 ^{1 of the} first section contains unit bits, and the first group 2G1 ^{0 of the} second section contains zero bits. Since the zero decrement flag FD = 0 is generated, a zero code is supplied to the group of inputs of the first term of the second adder 13, and the value of the binary code of the lower group of the second section 2G1 ⁰ is supplied to the group of inputs of the second term. At the same time, the value 1K = 2 ₁₀ without correction is transmitted to the output of the subtractor SB (decrementor) 10, which is transmitted to the number of shifts bus SK, by which the group is shifted from the outputs of the second adder 13 and group 2G of the second section to the older ones in the group shift module SF 14 groups into two groups.

Further, since zero values are transmitted from the outputs of the DC decoder (demultiplexer) 9 and the two senior groups at the output of group shift module SF 14 also take zero values, the first two groups of the first section 1G1 ⁰ and 1G2 ¹ are transmitted through the groups of AND elements with one inverse input 15 and the group of elements OR 16 to the corresponding groups of outputs G1 and G2. In this case, the values from the outputs of the third and fourth groups of the group shift module SF 14 are transmitted to the output groups G3 and G4. At the same time, the values of the total number of groups 1K and 2K are summed on the first adder 12 without correction for the decrement flag value, since FD = 0, as well as on the third adder 17 the values of codes 1U and 2U of the quantity (sum) of single bits in the first and second sections are summed, the outputs of which are respectively sent to the output groups of the block K and U.

For the values of the inputs 1k0 = 0, 1LB = 0 and 2LB = 1 (the first row No. = 1 of table 2 when the first section contains two groups (1k0 = 0), the first least significant group 1G1 ^{0 of the} first section contains zero bits, and the first least significant group 2G1 ^{1 of the} second section contains single bits) a single decrement flag FD = 1 is generated, according to which the DC decoder (demultiplexer) 9 is allowed to work and therefore the binary code of the single bits of the highest one is sent to the group of inputs of the first term of the second adder 13 from the outputs of the group of MX multiplexers (switches) 11 1G2 group ¹ of the first section, and the groups second summand input of which receives the value of binary one bits younger group 2G1 ^one second section, which are summed in the second adder 13, since the input data D1, D2, ..., DN these groups form a common group unit bit. Further, since the output of subtractor SB (dekrementora) 10 formed 1K value = 1 ₁₀ with correction code phase, the shear bands SF module 14 is performed on one group offset and zero values in the input left younger group. Since at the output of the DC decoder (demultiplexer) 9 a unity value is set at the second output corresponding to the second group 1G2 ¹ , it is forbidden to transfer this group through the corresponding elements And with one inverse input 15, and the value of the corresponding group from the output of the second adder is transmitted to the output G2 of the block 13 through the group shift module SF 14. Similarly to the above, codes are generated on the output groups of the blocks K and U.

The above algorithm for generating group values, in accordance with tables 2 and 4, is implemented in each block of elements 2 _{ij of the} second type of the second stage.

Further, the values from the outputs of the odd blocks of elements 2 ₂₁ , 2 ₂₃ , ..., 2 _{2 (N / 4-1)} (low) and the outputs of the even blocks of elements 2 ₂₂ , 2 ₂₄ , ..., 2 _{2N / 4} (Th) of the second stage in pairs arrive at the corresponding groups of inputs of the same name, respectively, of the first and second sections of the inputs of the respective blocks 2 ₃₁ , 2 ₃₂ , ..., 2 _{3N / 4 of the} third stage (Fig. 1).

In each block of elements 2 _{3j of the} second type of the third stage, the values of the inputs of the left bits 1LB of the first section and 2LB of the second section and the value of the lowest zero bit 1k0 of the group 1K of the total number of groups of single and zero bits of the first section and the output of the second EXCLUSIVE OR element are similarly analyzed 8 , in accordance with table 4, the decrement flag FD is generated. Further, in accordance with Table 3, the second adders 13 summarize the corresponding senior right groups 1G of the first sections and the lower left groups 2G of the second sections (indicated by shading in Table 3); the values of the shift code SK are generated on the subtractors SB (decrementors) 10 taking into account the flag value decrement FD and in the module SF shift groups 14 is shifted to the shift code SK and enter zero values in the lower left groups. At the same time, on the first adder 12, the codes of the total number of groups 1K and 2K are summed up, taking into account the value of the decrement flag FD, on the third adder 17, the codes 1U and 2U are summed up of the number (sum) of unit bits in the first and second sections, from the outputs of which are transmitted respectively to the groups outputs K and U of the respective blocks.

For example, according to table 3, for the values of the inputs 1k0 = 1, 1LB = 0 and 2LB = 0 (fourth row No. = 4 of table 3 when the first section contains an odd number of groups (1k0 = 1), and the first lower groups of the first 1G1 ⁰ and the second 2G1 ⁰ sections contain zero bits at 1Knch = 1 or the highest group 1G3 ^{0 of the} first section and the lowest group 2G1 ^{0 of the} second section also contain zero bits at 1Knch = 3) the decrement flag FD = 1 is generated (table 4), which indicates that neighboring groups contain zero bits and they must be combined into one group and corrected for the value of the shift code SK and reduce by one the sum of the total number of groups 1K and 2K of the first and second sections.

Next, the formation of group code values for the third, fourth, ..., Zth steps is carried out in a similar manner. In FIG. Figure 3 shows the output data formats Q at the external outputs 24 and the bit depth of the corresponding groups.

In addition, the output of the QU group of the number (sum) of unit bits goes to the group of inputs of the device flag generation module 4, to the second group of inputs of which the binary code "N" is received, corresponding to the number of bits of the input binary number D1, D2, ..., DN. In accordance with Table 5, the outputs of module 4 are formed: the values of the FE flag “TOTAL ZERO IS EQUAL TO THE TOTAL UNITS”, the flag F10 “TOTAL ZERO UNITS”, the flag F01 “TOTAL ZERO UNITS”, and also the QZ code value of the number (sum) of zero bits and the value of the Q01 code is the difference between the number (sums) of zero and one bits.

The proposed device can be used for hardware implementation of statistical tests developed by the laboratory of information technology of the National Institute of Standards and Technology (NIST, USA), the purpose of which is to determine the measure of randomness of binary sequences generated by random number generators. In particular, the proposed device implements:

- frequency bit test, the essence of which is to determine the ratio between zeros and ones in the entire binary sequence. The goal is to find out if the number of zeros and ones in the sequence is really about the same. The test evaluates how close the proportion of units is to 0.5.

- frequency block test, the essence of which is the determination of the fraction of units inside a block of length K bits. The goal is to find out if the repetition frequency of units in a block of length K bits is approximately equal to K / 2.

- a test for a sequence of identical bits, the essence of which is to calculate the total number of rows (groups) in the original sequence, where a series is a continuous subsequence of identical bits. A series (group) of length k bits consists of k absolutely identical bits, begins and ends with a bit containing the opposite value. The goal is to conclude whether the number of rows (groups) consisting of ones and zeros with different lengths really corresponds to their number in a random sequence. In particular, the units and zeros in the initial sequence are determined either quickly or slowly.

When processing the results of physical experiments, the proposed device provides the detection of events (groups of single bits) and intervals between events (groups of zero bits), determining the duration of events and intervals between them, as well as determining the total number and duration of events.

Thus, the binary codes corresponding to the number of zero QG ⁰ and unit QG ¹ bits in the input binary number groups are generated at the outputs of the proposed device, and the total number of QK groups, the total number (sum) of unit QU and zero QZ bits, and the difference code value are generated Q01 between them and the corresponding flags FE, F01, F10. In the proposed device of the pyramidal structure at each stage, the number of possible groups of zero QG ⁰ and single QG ¹ bits doubles.

The above information allows us to conclude that the proposed device solves the problem - identifying groups of identical bits, determining the number of single and zero bits in groups and determining the total number of groups, has regular nodes and connections, and corresponds to the claimed technical result - expanding the arsenal of tools for the same purpose and simplification of increasing the bit depth of the input data while reducing hardware costs.

Claims (12)

The device of the pyramidal structure for detecting groups of zero and single bits and determining their number contains N bits of the input binary number D1, D2, ..., DN, which are divided into N / 2 groups of two bits in a group, Z steps of blocks of elements, where Z =] log ₂ N [(] [is a larger integer), and the flag generation module of device 4, moreover, the first stage contains N / 2 blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type, and each i-th stage, starting from the second stage to the Z-th stage, contains N / 2 ⁱ blocks of elements 2ij the second type, where i = 2, 3, ..., Z, j = 1, 2, N / 2 ⁱ , moreover, N bits of the input binary number D1, D2, ..., DN in groups of two bits are connected to the inputs of the blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage corresponding to the same names of the input, the outputs of the odd blocks of elements 1 ₁ , 1 ₃ , ..., 1 _{(N / 2-1)} (low) and outputs of even blocks of elements 1 ₂ , 1 ₄ , ..., 1 _{N / 2} (th) of the first stage are paired with the corresponding groups of the same inputs of the first and second sections, respectively the inputs of the blocks of elements 2 ₂₁ , 2 ₂₂ , ..., 2 _{2N / 4 of the} second type of the second stage, and the outputs of the odd blocks of elements 2ij (low) and the outputs are even ith blocks of elements 2ij (th) of each i-th stage, starting from the second stage to the penultimate (Z-1) -th stage, are paired with the corresponding groups of inputs of the same name, respectively, of the first and second sections of the inputs of blocks of elements 2ij of the next stages, starting from the third stages to the last Zth stage, and the outputs of the groups of the block of elements 2zj of the last Zth stage are the corresponding groups Q of the external outputs of the same name of the device of the group QK of the total number of groups of unit and zero bits, groups QU of the number of unit bits in the input ary including D1, D2, ..., DN, N groups QG1, QG2, ..., QGN zero and one bits and QLB output corresponding to the input left bit binary number D1, each of the N / 2 blocks of elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type of the first stage contains the element "EQUIVALENCE" 5, the first element "EXCLUSIVE OR" 6 and the element AND 7, moreover, the pairs of bits of each of the N / 2 groups of the input binary number D1, D2, ..., DN, starting from the first bit, are connected respectively to the inputs A1 and A2 of the corresponding blocks of the same name elements 1 ₁ , 1 ₂ , ..., 1 _{N / 2 of the} first type the first stage of the N / 2 groups of the same name, while the inputs A1 and A2 are connected to the first and second inputs of the “EQUIVALENCE” element 5, the first element of “EXCLUSIVE OR” 6 and the element And 7, as well as the first input A1 is connected to the output of the left bit of the LB block the first type 1, the output of the element "EQUIVALENCE" 5 is connected to the first bit g11 of the first output of the bottom group G1 bits and zero bit k0 of the output group K of the total number of groups of single and zero bits, the output of the first EXCLUSIVE OR element 6 is connected to zero bit g10 of the first output group G1 bits, with zero bit g20 of the second output group G2 bits, with the first bit k1 of the output group K to the total number of groups of unit and zero bits and with a zero bit u0 of the output group U of the number of unit bits, the output of element And 7 is connected to the first bit u1 of the output group U of the number of unit bits, each block of elements 2 _{ij of the} second type of the second, third, ..., Z-th stage contains a second EXCLUSIVE OR element 8, a DC 9 decoder, a subtractor SB 10, a group of multiplexers MX 11, a first adder SM 12, a second adder SM 13, a module shift groups SF 14, groups of elements AND with one inverse input 15, groups of elements OR 16 and the third adder SM 17, moreover, the input 1LB of the left bit of the first section is connected to the output of the left bit LB of the block of the second type 2, all 2 ^(i-1) input groups of the first sections, starting from the first 1G1 group to the last 1G (2 ^(i-1) ) group, are connected to the first direct inputs of the elements of the corresponding groups of elements of the same name And with one inverse input 15 and are also connected to the corresponding information inputs of the group of multiplexers MX 11, the outputs of which are connected to the group of inputs of the first term of the second adder 13, in which the group of inputs of the second term is connected to the first uppp 2G1 of the second section, and the output of the second adder 13 is connected to the first group of inputs of the group shift module SF 14, in which (2 ^(i-1) -1) input groups, starting from the second group to the last group, are connected to the corresponding groups of the same name 2G the second section, starting from the second 2G2 group to the last 2G (2 ^(i-1) ) group, and the first 2 ^(i-1) outputs of the shift module of the SF 14 groups, starting from the first output to 2 ^(i-1) outputs, are connected with the second inputs of the elements of the corresponding groups of elements of the same name OR 16, the first inputs of which are connected to the corresponding one the outputs of the elements of the groups of elements And with one inverse input 15, in addition, in blocks 2 of the second type, the input 1LB of the left bit of the first section, the input 2LB of the left bit of the second section and the least significant bit 1k0 of group 1K of the total number of groups of single and zero bits of the first section are connected to the corresponding inputs of the second element “EXCLUSIVE OR” 8, output which is connected to the operation enable input E of the DC 9 decoder and the second input of the subtractor SB 10, the input group 1K of the total number of groups of single and zero bits of the first section is connected to the first group of inputs of the subtractor SB and to the group of inputs of the decoder DC 9, and the output The subtractor SB 10 is connected to the bus SK for setting the number of shifts, which is connected to the group of control inputs of the shift module of groups SF 14 and to the group of inputs of the first term of the first adder SM 12, in which the group of inputs of the second term is connected to the input group 2K of the total number of unit groups and zero bits of the second section, the input groups 1U and 2 U of the number of unit bits of the first and second sections are connected to the input groups of the first and second terms of the third adder SM 17, the outputs of the DC 9 decoder are connected to the corresponding directs input multiplexers MX sample group 11 and to the second inverted input elements of the respective groups of like elements and with one inverted input 15, moreover, the outputs of the groups of elements OR 16 are the first 2 ^(i-1) outputs of the groups of blocks 2, starting from the first G1 of the group to G (2 ^(i-1) ) of the group, and the outputs of the groups of the module of the shift of groups SF 14, starting from group (2 ^(i-1) +1) outputs to group 2 ⁱ outputs are the corresponding outputs of the same group of blocks 2, starting from group G (2 ^(i-1) +1) outputs to group G2 ⁱ outputs, and in addition the outputs of the first adder SM 12 are a group of outputs K of the total number of groups of unit and zero bits of blocks 2, and the outputs of the third adder SM 17 are a group of outputs U of the number of unit bits, the flag generation module of device 4 comprises a fourth adder SM with an inverse group of inputs 18, a fifth adder SM with an inverse group of inputs 19, a first element OR-NOT 20, a third group of elements EXCLUSIVE OR 21, a second element OR-NOT 22 and an incrementor SI 23 , moreover, the group of outputs U of the number of unit bits from the last Zth stage is connected to the first group of inputs of the device flag generation module 4, for which the binary number code "N" corresponding to the number of bits of the input binary number D1, D2, ..., DN, while the first group of inputs of the device flag generation module 4 is connected to the first inverse groups of inputs of the first terms of the fifth adder 19 and the fourth adder 18, while the fourth adder 18 has a second direct group of inputs of the second term the binary code “N” is supplied and the logical unit value “1” is fed to the transfer input CI, and the output group of the fourth adder 18 is a group of external outputs QZ of the number of zero bits in the input binary number D1, D2, ..., DN and is also connected with the second direct group of inputs of the second term of the fifth adder 19, for which the logical unit value “1” is applied to the transfer input CI, and the bits of the group of outputs of the fifth adder 19 are connected to the corresponding inputs of the first element OR NOT 20 and to the first inputs of the corresponding one exchange elements from the third group of EXCLUSIVE OR elements 21, the second inputs of which are interconnected and connected to the inverse output of the CO transfer of the fifth adder 19, which is also connected to the second input of the incrementator SI 23, with the second input of the second element OR-NOT 22 and is by the external output of the flag F10 “ONE MORE ZEROES”, the output of the first element OR NOT 20 is the external output of the FE flag “SUM OF ZERO IS EQUAL TO THE SUM OF UNITS” and also connected to the first input of the second element OR-NOT 22, the output of which is the external output of the flag F01 “ Null J MORE UNITS ", the outputs of the third group of elements" exclusive OR "21 are connected to respective bits of the first group of inputs SI incrementer 23, the outputs of which are a group of external Q01 outputs the difference between the number of zero and one bits, moreover, the output group QK of the total number of groups of unit and zero bits, the output group QU of the number of unit bits, the output group QZ of the number of zero bits and the output group Q01 of the difference between the number of zero and unit bits in the N bit input binary number D1, D2, ..., DN contain by] log ₂ (N + 1) [(larger integer) bits, and the output groups of zero and single bits of QGw contain by] log ₂ (N + 2-w) [(larger integer) bits, where w = 1, 2, ..., N.

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