RU2758205C1 - Two-threshold comparator of the binary bit range - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: two-threshold comparator of the binary bit range is disclosed, containing an N-bit input bus D, an input bus of a lower threshold (of boundary) GL and an input bus of an upper threshold (of boundary) GM containing M bits, where M=]log₂(N+1)[ (a larger integer), an output bus QL of the number of single bits up to a lower boundary, an output bus QC of the number of single bits inside the range and an output bus QM of the number of single bits above an upper boundary, also containing M bits, flag FL of single bits up to the lower boundary, flag FC of single bits inside the range, flag FM of single bits above the upper boundary, and an internal bus UL of junior ordered units, an internal bus UC of ordered units within the range, an internal bus UM of senior ordered units containing M bits, a decoder of the lower boundary 1, a decoder of the upper boundary 2, the first group 3₁, 3₂, …, 3_N-1, and the second group 4₁, 4₂, …, 4_N-1, each of which contains (N-1) elements OR, the group 5₁, 5₂, …, 5_N of N elements OR-NOT, the first group 6₁, 6₂, …, 6_N, the second group 7₁, 7₂, …, 7_N, and the third group 8₁, 8₂, …, 8_N, each of which contains N elements AND, the first 9₁, the second 9₂ and the third 9₃ blocks of counting units, as well as the first 10₁, the second 10₂ and the third 10₃ elements OR.

EFFECT: technical result of the invention is providing the possibility of determining the number of single bits in the given range between lower and upper boundaries and the number of single bits outside the range.

1 cl, 1 dwg, 1 tbl

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer technology, in particular to data processing devices, and can be used to build automation tools and functional units of control systems, as well as to process the results of physical experiments, signals and images.

PRIOR ART

Known device for determining the number of ones (zeros) in a binary number (RU No. 2446442, IPC G06F 7/50, Н03К 21/00, declared 04/11/2011, published 03/27/2012, Bull. No. 9), containing a block of controlled inversion, consisting of n-elements "EXCLUSIVE OR" (n is the number of bits of the input number), OR elements and modules consisting of an EXCLUSIVE OR element and an AND element, which are combined into groups consisting of tiers and are combined into k-cascades (k =] log ₂ n [), so that each i-th cascade contains g (i) = n / 2 ⁱ groups (i = 1, ..., k), each group of the i-th cascade is divided into j tiers (j = 1, ..., i), while the first tier of each group of the i-th cascade contains i modules, and each j-th tier of each group of the i-th cascade (j = 2, ... i,) contains (ij) modules and an OR element ...

The disadvantage of this device is the determination of only the total number of ones (zeros) in a binary number, and not the identification of groups of the range of single bits.

Known indicator of the senior unit (Ugryumov E.P. Digital circuitry. - SPb .: BHV-Petersburg, 2000. - 528 p., Fig. 2.8 p. 50-54), containing a group of elements I and a group of elements of the prohibition I with one inverse entrance. This device implements a chain circuit for transmitting a polling signal by sequential polling, starting from the most significant bit, and stopping further polling when the first unit is detected.

Known index of the senior unit (Computer circuitry. Collection of tasks: study guide. M: NRNU MEPhI, 2012. - 240 p., Fig. 53, p. 55-56), containing a group of elements OR combined into a chain and a group of elements of the prohibition AND with one inverse input.

The disadvantage of these devices is the identification of only one most significant one bit.

A known device for detecting the range of single bits (RU No. 2717631, IPC G06F 7/74, declared 11/07/2019, published 03/24/2020, bull. No. 9), containing N bits of the input bus D - D1, D2, ..., DN, N bits of the output bus Q - Q1, Q2, ..., QN, the first group of (N-2) elements OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , the second group of (N-2) elements OR 2 ₁ , 2 ₂ ,…, 2 _(N-2) and a group of (N-2) elements I 3 ₁ , 3 ₂ ,…, 3 _(N-2) . Moreover, the first group of elements OR 1 ₁ , 1 ₂ , ..., 1 _(N-2) , combined into a chain, forms an ordered group of consecutive units in the lowest digits, the second group of elements OR 2 ₁ , 2 ₂ , ..., 2 _{(N- 2)} forms an ordered group of ones in the most significant digits, and in the group of elements I 3 ₁ , 3 ₂ , ..., 3 _(N-2) , the unit values are checked in the same digits of the ordered groups of ones.

The disadvantage of this device is only the identification of the range of single bits and the formation between the single left (low) and right (high) ordered group of single bits.

The closest device for the same purpose to the claimed invention in terms of a set of features is a device for detecting the boundaries of the range of single bits (RU No. 2717934, IPC G06F 7/74, N03K 21/00, declared 12/19/2019, published 03/27/2020, Bul. No. 9 ), containing the N bit input bus D, the output bus QR of the least significant bit and the output bus QL of the most significant bit numbers each containing M bits, where M =] log ₂ (N + 1) [(greater integer), a group of (N-1 ) elements OR 1 ₁ , 1 ₂ , ..., 1 _(N-1) , a group of (N-1) elements OR NOT 2 ₁ , 2 ₂ , ..., 2 _(N-1) , the first 3 ₁ and the second 3 ₂ count units of the least significant ordered ones, as well as the internal right shift bus SR and the internal left shift bus SL, which each contain N bits.

The disadvantage of this device is only the detection of the boundaries of the range of single bits - the identification of the number of the left (most significant) single bit and the number of the right (least significant) single bit in the input data and the lack of means for counting single bits in the identified range of units.

OBJECT OF THE INVENTION

The object of the invention is to detect and count single bits both within the bit range defined by the lower and upper limits and outside the limits.

When processing the results of physical experiments, the device is designed to detect and count the number of events within a given range, and events outside the range.

The technical result of the invention is to expand the functionality in terms of the ability to determine the number of single bits in a given range between the lower and upper limits and the number of single bits outside the range.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved in that the two-threshold comparator of the range of binary bits contains an N-bit input bus D, an input bus of the lower threshold (boundaries) GL and an input bus of the upper threshold (boundaries) GM containing M bits each, where M =] log ₂ (N + 1) [(greater integer), the output QL bus of the number of one bits to the lower limit, the output QC bus of the number of single bits within the range and the output QM bus of the number of one bits above the upper limit, containing also M bits each, the FL flag of single bits to the lower limit, the FC flag of 1 bits within the range, the FM flag of 1 bits above the upper limit, as well as the internal UL bus of the lowest ordered ones, the internal UC bus of the ordered ones within the range, the internal UM bus of the highest ordered ones, containing M bits each,

decoder of the lower boundary 1, decoder of the upper boundary 2, the first group 3 ₁ , 3 ₂ , ..., 3 _N-1 and the second group 4 ₁ , 4 ₂ , ..., 4 _N-1 each of which contains (N-1) OR elements , group 5 ₁ , 5 ₂ , ..., 5 _N of N elements OR-NOT, the first group 6 ₁ , 6 ₂ , ..., 6 _N , the second group 7 ₁ , 7 ₂ , ..., 7 _N and the third group 8 ₁ , 8 ₂ , ..., 8 _N , each of which contains N elements AND, the first 9 ₁ , the second 9 ₂ and the third 9 ₃ blocks of counting ones, as well as the first 10 ₁ , the second 10 ₂ and the third 10 ₃ OR elements,

moreover, the input bus of the lower boundary GL is connected to the inputs of the decoder of the lower boundary 1, the outputs of which, starting from the first to the (N-1) -th output, are connected to the first inputs of the corresponding (N-1) -th elements of the first group 3 ₁ , 3 ₂ , ..., 3 _N-1 of (N-1) OR elements, while the second inputs of (N-2) elements 3 ₁ , 3 ₂ , ..., 3 _N-2 from the first group of OR elements, starting from the first to ( N-2) elements, connected to the outputs of the corresponding subsequent (N-2) elements 3 ₂ , 3 ₃ , ..., 3 _N-1 from the first group of OR elements, starting from the second to (N-1) elements, and the second input of the last (N-1) th element 3 _N-1 from the first group of elements OR is connected to the last N-th output of the decoder of the lower boundary 1,

in addition, the outputs of all (N-1) OR elements of the first group 3 ₁ , 3 ₂ , ..., 3 _N-1 are the corresponding (N-1) bits of the internal UL bus of lower ordered ones, in which the most significant N-th bit is connected to The Nth output of the decoder of the lower boundary 1,

moreover, the input bus of the upper boundary GM is connected to the inputs of the decoder of the upper boundary 2, the outputs of which, starting from the second to the Nth output, are connected to the second inputs of the corresponding (N-1) th elements of the second group of elements 4 ₁ , 4 ₂ , ... 4 _N-1 of (N-1) elements OR, with the first inputs of (N-2) elements 4 ₂ , 4 ₃ , ..., 4 _N-1 from the second OR group, starting from the second to (N-1) elements, connected to the outputs of the corresponding previous (N-2) elements 4 ₁ , 4 ₂ , ..., 4 _N-2 from the second group of OR elements, starting from the first to (N-2) elements, and the first input of the first element 4 ₁ from the second group elements OR is connected to the first output of the decoder of the upper boundary 2,

in addition, the outputs of all (N-1) elements OR of the second group 4 ₁ , 4 ₂ , ..., 4 _N-1 are the corresponding (N-1) bits of the internal bus UM of the highest ordered units, starting from the second to the Nth bit, and the least significant first bit of the UM bus of the most significant ordered units is connected to the first output of the decoder of the upper bound 2,

moreover, the same-name bits of the internal bus UL of the lowest ordered units and the internal bus UM of the highest ordered units are connected, respectively, to the first and second inputs of the corresponding like-named elements of the group 5 ₁ , 5 ₂ , ..., 5 _N of N OR-NOT elements, the outputs of which are

the corresponding N bits of the internal bus UC of ordered units within the range, which are connected to the second inputs of the corresponding like-named elements of the second group 7 ₁ , 7 ₂ , ..., 7 _N of N elements And,

In addition, N bits of the internal UL bus of the lowest ordered units are connected to the second inputs of the corresponding elements of the same name of the first group 6 ₁ , 6 ₂ , ..., 6 _N of N elements AND, and N bits of the internal bus UM of the highest ordered units are connected to the second inputs of the corresponding elements of the same name the third group 8 ₁ , 8 ₂ , ..., 8 _N of N elements And,

moreover, the first inputs of the same elements of the first group 6 ₁ , 6 ₂ , ..., 6 _N , the second group 7 ₁ , 7 ₂ , ..., 7 _N and the third group 8 ₁ , 8 ₂ , ..., 8 _N each of the N elements And are connected between themselves, and also connected to the corresponding N bits of the input bus D of the same name,

in addition, the outputs of the elements of the first group 6 ₁ , 6 ₂ , ..., 6 _N , the second group 7 ₁ , 7 ₂ , ..., 7 _N and the third group 8 ₁ , 8 ₂ , ..., 8 _N , each of N elements And, are connected respectively with the inputs of the first 9 ₁ , the second 9 ₂ and the third 9 ₃ units for counting units, the outputs of which are connected respectively to the first 10 ₁ , the second 10 ₂ and the third 10 ₃ OR elements,

moreover, the outputs of the first 9 ₁ , second 9 ₂ and third 9 ₃ units of counting units are the corresponding bits, respectively, of the output bus QL of the number of single bits to the lower limit, the output bus QC of the number of single bits within the range and the output bus QM of the number of single bits above the upper limit,

the outputs of the first 10 ₁ , the second 10 ₂ and the third 10 ₃ OR elements are respectively the FL flag of 1 bits to the lower bound, the FC flag of 1 bits within the range and the FM flag of 1 bits above the upper bound.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a functional diagram of the proposed two-threshold binary bit range comparator. Table 1 shows test examples with the number of bits of input data N = 8.

FIG. 1, in table 1 and in the text, the following designations are introduced:

D - N bit input bus;

D1, D2, ..., D8 (DN) - input bus bits (for N = 8);

GL - M bit lower threshold (border) of the range,

where M =] log ₂ (N + 1) [(larger integer);

GML - M bit upper threshold (border) of the range;

QL - M bit output bus of the number of single bits to the lower limit;

QM - M bit output bus of the number of single bits above the upper limit;

QC - M bit output bus of the number of single bits within the range;

FL - flag of single bits to the lower limit;

FM - flag of single bits above the upper limit;

FC - flag of single bits within the range;

UL - N bit internal bus of lower ordered units;

UM - N bit internal bus of the highest ordered units;

UC - N bit internal bus of ordered units within the range;

SL - N-bit internal bus of single bits in the least significant bits;

SM - N bit internal bus of single bits in the most significant bits;

SC - N bit internal bus of single bits within the range;

1 - decoder of the lower boundary;

2 - decoder of the upper boundary;

3 ₁ , 3 ₂ , ..., 3 _N-1 - the first group of (N-1) OR elements (OR);

4 ₁ , 4 ₂ ,…, 4 _N-1 - the second group of (N-1) elements OR (OR);

5 ₁ , 5 ₂ ,…, 5 _N - a group of N elements OR NOT (NOR);

6 ₁ , 6 ₂ ,…, 6 _N - the first group of N elements AND (AND);

7 ₁ , 7 ₂ ,…, 7N - the second group of N elements AND (AND);

8 ₁ , 8 ₂ ,…, 8 _N - the first group of N elements AND (AND);

9 ₁ , 9 ₂ , 9 ₃ - the first, second and third blocks of counting units;

10 ₁ , 10 ₂ , 10 ₃ - the first, second and third elements of OR (OR).

The proposed two-threshold binary bit range comparator contains an N-bit input bus D, an input low-threshold bus (boundaries) GL and an input high-threshold bus (boundaries) GM containing M bits each, where M =] log ₂ (N + 1) [(greater integer ), the QL output bus of the number of single bits to the lower limit, the QC output bus of the number of single bits within the range and the QM output bus of the number of single bits above the upper limit, also containing M bits each, the FL flag of single bits to the lower limit, the FC flag of single bits inside range, the FM flag of single bits above the upper limit, as well as the internal UL bus of lower ordered ones, the internal UC bus of ordered units within the range, the internal UM bus of the upper ordered ones, containing M bits each.

In addition, the two-threshold binary bit range comparator contains a lower bound decoder 1, an upper bound decoder 2, a first group 3 ₁ , 3 ₂ , ..., 3 _N-1 and a second group 4 ₁ , 4 ₂ , ..., 4 _N-1 , each of which contains (N-1) OR elements, group 5 ₁ , 5 ₂ , ..., 5 _N of N OR-NOT elements, the first group 6 ₁ , 6 ₂ , ..., 6 _N , the second group 7 ₁ , 7 ₂ , ... , 7 _N and the third group 8 ₁ , 8 ₂ , ..., 8 _N , each of which contains N elements And, the first 9 ₁ , the second 9 ₂ and the third 9 ₃ blocks of counting ones, as well as the first 10 ₁ , the second 10 ₂ and third 10 ₃ elements OR.

Moreover, the input bus of the lower boundary GL is connected to the inputs of the decoder of the lower boundary 1, the outputs of which, starting from the first to the (N-1) -th output, are connected to the first inputs of the corresponding (N-1) -th elements of the first group of the same name 3 ₁ , 3 ₂ , ..., 3 _N-1 of (N-1) OR elements. In this case, the second inputs of (N-2) elements 3 ₁ , 3 ₂ , ..., 3 _N-2 from the first group of OR elements, starting from the first to (N-2) elements, are connected to the outputs of the corresponding subsequent (N-2) elements 3 ₂ , 3 ₃ , ..., 3 _N-1 from the first group of OR elements, starting from the second to (N-1) elements. The second input of the last (N-1) th element 3 _N-1 from the first group of OR elements is connected to the last N-th output of the decoder of the lower boundary 1.

In addition, the outputs of all (N-1) OR elements of the first group 3 ₁ , 3 ₂ , ..., 3 _N-1 are the corresponding (N-1) bits of the internal UL bus of lower ordered ones, in which the most significant N-th bit is connected to N-th output of the lower bound decoder 1.

Moreover, the input bus of the upper boundary GM is connected to the inputs of the decoder of the upper boundary 2, the outputs of which, starting from the second to the Nth output, are connected to the second inputs of the corresponding (N-1) th elements of the second group of elements 4 ₁ , 4 ₂ , ..., 4 _N-1 of (N-1) OR elements. In this case, the first inputs of (N-2) elements 4 ₂ , 4 ₃ , ..., 4 _N-1 from the second group OR, starting from the second to (N-1) elements, are connected to the outputs of the corresponding previous (N-2) elements 4 ₁ , 4 ₂ , ..., 4 _N-2 from the second group of OR elements, starting from the first to (N-2) elements. The first input of the first element 4 ₁ from the second group of OR elements is connected to the first output of the decoder of the upper boundary 2.

In addition, the outputs of all (N-1) OR elements of the second group 4 ₁ , 4 ₂ , ..., 4 _N-1 are the corresponding (N-1) bits of the internal bus UM of the highest ordered units, starting from the second to the Nth bit. The least significant first bit of the UM bus of the most significant ordered units is connected to the first output of the decoder of the upper bound 2.

Moreover, the bits of the same name of the internal bus UL of the lower ordered units and the internal bus UM of the higher ordered units are connected, respectively, to the first and second inputs of the corresponding similar elements of the group 5 ₁ , 5 ₂ , ..., 5 _N of N OR-NOT elements, the outputs of which are

the corresponding like-named N bits of the internal bus UC of ordered units within the range, which are connected to the second inputs of the corresponding like-named elements of the second group 7 ₁ , 7 ₂ , ..., 7 _N of N elements.

In addition, N bits of the internal UL bus of the lowest ordered units are connected to the second inputs of the corresponding like elements of the first group 6 ₁ , 6 ₂ , ..., 6 _N of N elements And. N bits of the internal bus UM of the highest ordered units are connected to the second inputs of the corresponding like elements of the third groups 8 ₁ , 8 ₂ , ..., 8 _N of N elements I.

Moreover, the first inputs of the same-named elements of the first group 6 ₁ , 6 ₂ , ..., 6 _N , the second group 7 ₁ , 7 ₂ , ..., 7 _N and the third group 8 ₁ , 8 ₂ , ..., 8 _N , each of which contains N elements And they are interconnected, and also connected to the corresponding N bits of the input bus D of the same name.

In addition, the outputs of the elements of the first group 6 ₁ , 6 ₂ , ..., 6 _N , the second group 7 ₁ , 7 ₂ , ..., 7 _N and the third group 8 ₁ , 8 ₂ , ..., 8 _N , each of which contains N elements AND , connected respectively to the inputs of the first 9 ₁ , second 9 ₂ and third 9 ₃ units for counting units, the outputs of which are connected respectively to the first 10 ₁ , the second 10 ₂ and the third 10 ₃ OR elements.

Moreover, the outputs of the first 9 ₁ , second 9 ₂ and third 9 ₃ units of counting units are the corresponding bits, respectively, of the output bus QL of the number of single bits to the lower limit, the output bus QC of the number of single bits within the range and the output bus QM of the number of single bits above the upper limit.

The outputs of the first 10 ₁ , second 10 ₂ and third 10 ₃ OR elements are respectively the FL flag of 1s to the lower bound, the FC flag of 1s within the range, and the FM flag of 1s above the upper bound.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows.

The proposed device allows detecting single bits on the input data bus D inside and outside the specified range limits. At the outputs of the device, numbers are formed that correspond to the number of single digits within the QC range, as well as to the number of single digits up to the lower limit (threshold) of QL and above the upper limit of QM. At the same time, the flags of the presence of single bits (events) in the corresponding fields of the input data bus are set: the FC flag is within the range, the FL flag is up to the lower range limit, the FM flag is above the upper range limit.

All N binary bits of the input bus D - D1, D2, ..., DN - arrive at the inputs of the device. At the same time, the corresponding values of the M-bit binary codes (where M =] log ₂ (N + 1) [(greater integer)) of the lower limit (threshold) GL and the upper limit (threshold) QM of the given range are supplied to the inputs of the decoders of boundaries 1 and 2. In this case, the N binary bits of the input bus D are divided into three groups (fields): the lower group - the least significant bits from the first to the GL-th bit correspond to the bits to the lower boundary (threshold), the middle group - the bits from the (GL + 1) -th to (GM-1) -th digits correspond to the digits within the range between the lower and upper limits, the senior group - the digits from the GM-th to the N-th bit correspond to the digits above the range (above the upper GM limit).

At the outputs of the decoders, unitary codes "1 from N" are formed, in the absence of a zero output. A single value from the output of the decoder of the lower boundary 1, corresponding to the lower boundary GL, is transmitted to the input of the corresponding element 3 _{GL of the} first group of OR elements 3 ₁ , 3 ₂ , ..., 3 _(N-1) , and then sequentially transmitted along the chain of OR elements towards low-order bits and an ordered sequence of single values (unitary positional series) are set at the outputs of the corresponding low-order elements of the first OR group, starting from the first element to the GL-th element. A single value from the output of the decoder of the upper boundary 2, corresponding to the upper boundary of GM, is transmitted to the input of the corresponding element 4 _{(GL-1) of the} second group of elements OR 4 ₁ , 4 ₂ , ..., 4 _(N-1) , and then sequentially transmitted along the chain OR elements in the direction of the most significant bits and an ordered sequence of single values (unitary positional series) is set at the outputs of the corresponding senior elements of the second OR group, starting from the (GM-1) th element to the (N-1) th element. Further, the values from the outputs of the first group of OR elements 3 ₁ , 3 ₂ , ..., 3 _(N-1) enter the internal UL bus of the lowest ordered ones, and the values from the outputs of the second group of OR elements 4 ₁ , 4 ₂ , ..., 4 _{(N -1)} arrive at the internal UM bus of the highest ordered units.

Further, the values of the corresponding bits from the UL buses of the lowest and UM of the highest ordered units arrive respectively at the first and second inputs of the same elements of a group of N elements OR NOT 5 ₁ , 5 ₂ , ..., 5 _N. In this case, zero values are set at the two inputs of a group of OR-NOT elements, starting from element 5 _{(GL + 1)} to element 5 _(GM-1) , and therefore unit values will be set at the outputs of these elements, which are fed to the internal UC bus of ordered units within the range.

Further, the values from the internal buses of low-order UL, within the range of UC and high-order UM of ordered units are fed to the second inputs of the same elements, respectively, of the first 6 ₁ , 6 ₂ , ..., 6 _N , the second 7 ₁ , 7 ₂ , ..., 7 _N and the third 8 ₁ , 8 ₂ , ..., 8 _N groups of elements And, in each of which the first inputs are connected to the corresponding bits of the same name of the input bus D. At the outputs of the elements of the first 6 ₁ , 6 ₂ , ..., 6 _N , the second 7 ₁ , 7 ₂ , ... , 7 _N and the third 8 ₁ , 8 ₂ , ..., 8 _N groups of elements AND unit values are formed corresponding to the same pairs of unit values from buses of ordered units and input data D, which are fed to the corresponding internal buses of unit bits in the least significant bits of SL, inside range SC and high digits SM.

Further, the values from the internal buses of single bits in the low-order bits of SL, within the range of SC and high-order bits of SM, are respectively fed to the inputs of the first 9 ₁ , the second 9 ₂ and the third 9 ₃ units for counting ones, at the outputs of which number codes are generated corresponding to the number of single bits (events ) in the input data fields, which are transmitted to the external output buses, according to the number of single bits (events) up to the lower QL limit, within the QC range and above the upper QM limit.

The values from the outputs of the first 9 ₁ , the second 9 ₂ and the third 9 ₃ units of counting units are also transmitted to the inputs of the first 10 ₁ , the second 10 ₂ and the third 10 ₃ OR elements, at the outputs of which unit values are formed in the presence of events in the corresponding fields of the input data D. Outputs of the first 10 ₁ , the second 10 ₂ and the third 10 ₃ OR elements are the corresponding flags of single events: to the lower limit of FL, within the FC range and above the upper limit of FM.

The proposed device works as follows.

The input bus of the D bus simultaneously receives N bits - D1, D2, ..., DN. The values from N bits of the input bus D are fed to the first inputs of the same elements of the first 6 ₁ , 6 ₂ , ..., 6 _N , the second 7 ₁ , 7 ₂ , ..., 7 _N and the third 8 ₁ , 8 ₂ , ..., 8 _N groups of elements I. At the same time, the corresponding values of M-bit binary codes (where M =] log ₂ (N + 1) [(greater integer)) of the lower boundary (threshold) GL and the upper boundary (threshold) GM of the given range.

At the outputs of the decoders, unitary codes "1 from N" are formed, in the absence of a zero output. In accordance with the values of the lower GL and upper GM boundaries (thresholds) at the outputs of the first group of elements OR 3 ₁ , 3 ₂ , ..., 3 _(GL) , the second group of elements OR 4 _{(GL + 1)} , ..., 4 _{(GM-1 )} and the third group of elements OR 4 _(GM-1) , ..., 4 _(N-1) , the corresponding ordered sequences of single values (unitary positional rows) are formed, which are transmitted to the corresponding internal buses of low UL, within the range of UC and high UM ordered units ...

Further, to the outputs of the first 6 ₁ , 6 ₂ , ..., 6 _N , the second 7 ₁ , 7 ₂ , ..., 7 _N and the third 8 ₁ , 8 ₂ , ..., 8 _N groups of elements And the corresponding unit values are transmitted from N bits of the input bus D in accordance with the ordered sequences of the ones on the corresponding internal buses of lower UL, within the range of UC and upper UM ordered ones. Further, the first 9 ₁ , the second 9 ₂ and the third 9 ₃ units count units from the corresponding internal buses of the unit bits (events) in the least significant bits of the SL, within the range of SC and the most significant bits of SM. The values from the outputs of the first 9 ₁ , the second 9 ₂ and the third 9 ₃ units of counting units are transmitted to the output buses of the number of single events to the lower limit of QL, within the QC range and above the upper limit of QM.

At the same time, single flag values are generated for fields (groups) up to the lower FL boundary, within the FC range and above the upper FM boundary in the presence of single bits (events) in the corresponding fields of the input data D, or zero flag values in the absence of corresponding single bits (events).

Table 1 shows test examples of counting single bit values in the fields (groups) of the input data D with the number of digits N = 8, in accordance with the specified lower GL and upper GM boundaries (thresholds) of the investigated range and the formation of the corresponding flags to the lower FL boundary, inside band FC and above the upper limit of FM. Table 1 in parentheses indicates the representation of values in binary code (2) or decimal code (10).

In all test cases, the input D bus is set to 1110 1101.

In test # 1, the values of the lower GL = 2 and upper GM = 6 range boundaries are set. Therefore, the corresponding sequences of unit values (unitary positional rows) are formed on the internal buses of the lower UL = 0000 OOP, within the range UC = 0001 1100 and upper UM = 1110 0000 ordered units. Further, from the input bus D, values are transmitted to the internal buses of single bits (events) in the least significant bits of SL = 0000 0001, within the range SC = 0000 1100 and in the most significant bits of SM = 1110 0000, which are counted, respectively, in the first 9 ₁ , the second 9 ₂ and the third 9 ₃ units counting units and on the output buses the values of the codes of the number of single events are formed up to the lower limit QL = 1, within the range QC = 2 and above the upper limit QM = 3, and since single events are present in all fields (groups) of input data D, then the corresponding single flag values are formed up to the lower limit FL = 1, within the range FC = 1 and above the upper limit FM = 1.

In test # 2, a zero value GL = 0 of the lower limit and a value of GM = 6 of the upper limit of the range are set. Since the value of the lower limit is zero, then all zero values UL = 0000 0000 are formed on the internal UL bus of the lower ordered units, and the values on the internal buses within the range UC = 0001 1111 and higher = 1110 0000 ordered units, along which further from the input on the D bus, the corresponding bit values are transmitted to the internal buses of single events in the least significant bits of SL = 0000 0000, within the range SC = 0000 1101 and the most significant bits of SM = 1110 0000, which are counted, respectively, in the first 9 ₁ , second 9 ₂ and third 9 ₃ blocks counting units and on the output buses the values of the codes of the number of single bits (events) to the lower limit QL = 0 are formed, within the range QC = 3 and above the upper limit QM = 3, according to which, respectively, the zero value of the flag to the lower limit FL = 0 and single flag values within the range FC = 1 and above the upper limit FM = 1.

In test # 3, the value GL = 3 of the lower limit and the zero value of GM = 0 of the upper limit of the range are set. Since the value of the upper limit is zero, all zero values UM = 0000 0000 are formed on the internal UM bus of the upper ordered units, and the values on the internal buses of the lower ones UL = 0000 0111 and within the range UC = 1111 1000 ordered units, along which further from the input bus D, the corresponding values are transferred to the internal buses of single bits (events) in the least significant bits of SL = 0000 0101 and within the range SC = 1110 1000, and zero values in the most significant bits of SM = 0000 0000, which are counted respectively in the first 9 ₁ , the second 9 ₂ and the third 9 ₃ units counting units and on the output buses the values of the codes of the number of single bits (events) are formed to the lower limit QL = 2, within the range QC = 4 and above the upper limit QM = 0, according to which the unit values of the flag are formed respectively to the lower limit FL = 1 and the flag within the range FC = 1 and the zero value of the flag above the upper limit FM = 0.

Test # 4 is set to zero values GL = 0 of the lower limit and GM = 0 of the upper limit of the range, i.e. all N bits of the input D bus are range bits - there are no lower and higher groups (fields). Therefore, zero values are generated on the internal buses of lower UL = 0000 0000 and upper UM = 0000 0000 bits and all unit values within the range UC = 1111 1111 ordered units. Further, from the input bus D, the detected single bits are transmitted only to the internal bus of single bits (events) within the SC = 1110 1101 range and zero values are set on the buses of single bits (events) in the low-order bits SL = 0000 0000 and in the high-order bits SM = 0000 0000 Further, as a result of counting, respectively, in the first 9 ₁ , the second 9 ₂ and the third 9 ₃ units for counting units on the output buses, the values of the codes of the number of single bits (events) are formed up to the lower limit QL = 0, within the range QC = 6 and above the upper limit QM = 0, according to which, respectively, a single flag value within the FC = 1 range and zero flag values up to the lower limit FL = 0 and above the upper limit FM = 0 are formed.

The above information allows us to conclude that the proposed device solves the problem and corresponds to the claimed technical result - it detects single bits and determines the number of single bits in a given range between the inner and upper limits, the number of single bits outside the range and sets the appropriate flags.

Claims (13)

The two-threshold binary bit range comparator contains an N-bit input line D, an input line of the low threshold (boundaries) GL and an input line of the high threshold (boundaries) GM, each containing M bits, where M =] log ₂ (N + 1) [(greater integer), the QL output bus of the number of single bits to the lower limit, the QC output bus of the number of single bits within the range and the QM output bus of the number of single bits above the upper limit, also containing M bits each, the FL flag of single bits to the lower limit, the FC flag of single bits within the range, the FM flag of single bits above the upper limit, as well as the internal UL bus of the lowest ordered ones, the internal UC bus of the ordered ones within the range, the internal UM bus of the highest ordered ones, containing M bits each, decoder of the lower boundary 1, decoder of the upper boundary 2, the first group 3 ₁ , 3 ₂ , ..., 3 _N-1 and the second group 4 ₁ , 4 ₂ , ..., 4 _N-1 , each of which contains (N-1) elements OR, group 5 ₁ , 5 ₂ , ..., 5 _N of N elements OR-NOT, the first group 6 ₁ , 6 ₂ , ..., 6 _N , the second group 7 ₁ , 7 ₂ , ..., 7 _N and the third group 8 ₁ , 8 ₂ , ..., 8 _N , each of which contains N elements AND, the first 9 ₁ , the second 9 ₂ and the third 9 ₃ blocks of counting ones, as well as the first 10 ₁ , the second 10 ₂ and the third 10 ₃ elements OR, moreover, the input bus of the lower boundary GL is connected to the inputs of the decoder of the lower boundary 1, the outputs of which, starting from the first to the (N-1) -th output, are connected to the first inputs of the corresponding (N-1) -th elements of the first group 3 ₁ , 3 ₂ , ..., 3 _N-1 of (N-1) OR elements, while the second inputs of (N-2) elements 3 ₁ , 3 ₂ , ..., 3 _N-2 from the first group of OR elements, starting from the first to ( N-2) elements, connected to the outputs of the corresponding subsequent (N-2) elements 3 ₂ , 3 ₃ , ..., 3 _N-1 from the first group of OR elements, starting from the second to (N-1) elements, and the second input of the last (N-1) th element 3 _N-1 from the first group of elements OR is connected to the last N-th output of the decoder of the lower boundary 1, in addition, the outputs of all (N-1) OR elements of the first group 3 ₁ , 3 ₂ , ..., 3 _N-1 are the corresponding (N-1) bits of the internal UL bus of lower ordered ones, in which the most significant N-th bit is connected with the Nth output of the decoder of the lower boundary 1, moreover, the input bus of the upper boundary GM is connected to the inputs of the decoder of the upper boundary 2, the outputs of which, starting from the second to the Nth output, are connected to the second inputs of the corresponding (N-1) th elements of the second group of elements 4 ₁ , 4 ₂ , ..., 4 _N-1 of (N-1) elements OR, with the first inputs of (N-2) elements 4 ₂ , 4 ₃ , ..., 4 _N-1 from the second group OR, starting from the second to (N-1) elements , connected to the outputs of the corresponding previous (N-2) elements 4 ₁ , 4 ₂ , ..., 4 _N-2 from the second group of OR elements, starting from the first to (N-2) elements, and the first input of the first element 4 ₁ from the second group of elements OR is connected to the first output of the decoder of the upper boundary 2, in addition, the outputs of all (N-1) elements OR of the second group 4 ₁ , 4 ₂ , ..., 4 _N-1 are the corresponding (N-1) bits of the internal bus UM of the highest ordered ones, starting from the second to the Nth bit, and the least significant first bit of the UM bus of the most significant ordered units is connected to the first output of the decoder of the upper boundary 2, moreover, the same-name bits of the internal bus UL of the lowest ordered units and the internal bus UM of the highest ordered units are connected, respectively, to the first and second inputs of the corresponding like-named elements of the group 5 ₁ , 5 ₂ , ..., 5 _N of N OR-NOT elements, the outputs of which are the corresponding N bits of the internal bus UC of ordered units within the range, which are connected to the second inputs of the corresponding like-named elements of the second group 7 ₁ , 7 ₂ , ..., 7 _N of N elements And, in addition, N bits of the internal UL bus of the lower ordered units are connected to the second inputs of the corresponding like-named elements of the first group 6 ₁ , 6 ₂ , ..., 6 _N of N elements AND, and N bits of the internal bus UM of the higher ordered units are connected to the second inputs of the corresponding like-named elements of the third group 8 ₁ , 8 ₂ , ..., 8 _N of N elements And, moreover, the first inputs of the same-named elements of the first group 6 ₁ , 6 ₂ , ..., 6 _N , the second group 7 ₁ , 7 ₂ , ..., 7 _N and the third group 8 ₁ , 8 ₂ , ..., 8 _N , each of N elements And, connected to each other, and also connected to the corresponding N bits of the input bus D of the same name, in addition, the outputs of the elements of the first group 6 ₁ , 6 ₂ , ..., 6 _N , the second group 7 ₁ , 7 ₂ , ..., 7 _N and the third group 8 ₁ , 8 ₂ , ..., 8 _N , each of N elements And, connected respectively to the inputs of the first 9 ₁ , the second 9 ₂ and the third 9 ₃ units for counting units, the outputs of which are connected respectively to the first 10 _{1, the} second 10 ₂ and the third 10 ₃ OR elements, moreover, the outputs of the first 9 ₁ , second 9 ₂ and third 9 ₃ units of counting units are the corresponding bits, respectively, of the output bus QL of the number of single bits to the lower limit, the output bus QC of the number of single bits within the range and the output bus QM of the number of single bits above the upper limit, the outputs of the first 10 ₁ , the second 10 ₂ and the third 10 ₃ OR elements are respectively the FL flag of 1 bits to the lower bound, the FC flag of 1 bits within the range and the FM flag of 1 bits above the upper bound.

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