RU2819111C1 - Device for detecting given k-bit groups of single bits in data units - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: present technical solution relates to computer engineering. Device has an external N-bit input data bus ID of data units G, an external M-bit bus for setting the capacity of groups IU (where M≤N, K≤M), a group of external outputs of the number of groups in the QK unit, a group of external outputs of the initial digits of the groups in the QB unit, first group of (N-M+1)-th detection units 1₁, 1₂, …, 1_(N-M+1), first groups 2₁, 2₂, …, 2_M, from M OR elements with inverse input of the first group of detection units 1₁, 1₂, …, 1_(N-M+1), second group of (M-1)-th detection units 3₁, 3₂, …, 3_(M-1), second groups of I OR elements with inverse input 4₁, 4₂, …, 4_(M-1) corresponding like I-th detection units of second group 31, 3₂, …, 3_(M-1), (where I=1, … (M-1)), first group of (N-M+1)-th AND elements, 5₁, 5₂, …, 5_(N-M+1), second group of (M-1)-th AND elements with inverse inputs 6₁, 6₂, …, 6_(M-1), third group of (N-1)-th AND elements with inverse input 7₁, 7₃,…, 7_N and unit counting units 8, as well as internal N-bit bus of initial digits of BB groups.

EFFECT: providing the possibility of detecting groups of single bits of a given capacity, determining the number of given groups and their arrangement in data units.

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Description

TECHNICAL FIELD

The invention relates to the field of computer technology, in particular to data processing devices, and can be used to construct functional units for analyzing the properties of generators of pseudo-random sequences of binary numbers, filtering events, processing signals, images and the results of physical experiments.

BACKGROUND ART

A device for detecting groups of bits (RU No. 2780985 C1, IPC G06F 7/74, G06F 7/02, application 12/01/2021, published 10/04/2022, Bullet No. 28) is known, contains an external m-bit data input ID, external m-bit input of a given pattern IG, group of external data outputs QB, first RS start-stop flip-flop TSS 1, second D-flip-flop TR2 delay 2, CTG group counter 3, output buffer OB 4, first R1 data register 5, second R2 data register 6, a group of m comparators 7 ₁ , 7 ₂ , ..., 7 _m , a group of (m-1) AND elements 8 ₂ , 8 ₃ , ..., 8 _m , OR element 9 and AND element 10, and also entered external inputs for asynchronous setting to the zero state CLR, device start START, device stop STOP and clock C, internal 2m-bit data bus BD, internal m-bit buffer data bus IOB, internal match flag FE, external exchange control bus EO, external flag “Buffer full” FF and “Buffer empty” flag FZ.

The disadvantage of this device is that at each clock cycle it detects groups of bits corresponding only to a given pattern.

The closest device for the same purpose to the claimed invention in terms of the set of features is, taken as a prototype, a device for detecting groups of single bits and maximum groups in data blocks (RU No. 280039 C1, IPC G06F 7/74, application 03/09/2023, publ. 07/17/2023, Bulletin No. 20), contains an external input data bus IBD, a group of external outputs for the number of groups in the QB block, a group of external outputs for the maximum group QM and a group of external outputs Q1, Q2, Q3, Q4 for the number of single groups in the input sequence, first 1 ₁ , 1 ₂ , …, 1 ₈ , second 2 ₁ , 2 ₂ , …, 2 ₇ and third 3 ₁ , 3 ₂ , …, 3 ₆ groups of AND elements with inverse inputs, group of AND elements 4 ₁ , 4 ₂ , ..., 4s, OR element 5, adder group 6 ₁ , 6 ₂ , 6 ₃ , 6 ₄ , register group 7 ₁ , 7 ₂ , 7 ₃ , 7 ₄ , unit counting block group 8 ₁ , 8 ₂ , 8 ₃ , group of elements OR 9 ₁ , 9 ₂ , 9 ₃ , priority encoder 10, first OB and second OM output buffers, as well as external inputs of synchronous setting to the zero state IR and clock IC, group of internal buses B ₁ , B ₂ , B ₃ and B ₄ , internal flag FB4, external exchange control buses EO, external flags “Buffer full” FF and “Buffer empty” FZ.

The disadvantage of this device is that it detects only 1, 2, 3, ≥4 bit groups in 8-bit data blocks.

OBJECTIVE OF THE INVENTION

The objective of the invention is to develop hardware for studying the properties of generators of pseudo-random sequences of binary numbers, as well as for processing the results of physical experiments.

When analyzing generators of pseudo-random sequences of binary numbers, the device is designed to identify groups (rows) of consecutive unit bits of a given bit depth and count their number.

When processing the results of physical experiments, the device is designed to identify events of a given dimension, determine their number and place them in data blocks.

The technical result of the invention is to expand the arsenal of tools for the same purpose, in terms of providing the ability to detect groups of unit bits of a given bit depth, determine the number of specified groups and their placement in data blocks.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved in that the device for detecting specified K-bit groups of unit bits in data blocks contains an external N-bit input data bus ID data blocks G, an external M-bit bus for setting the width of groups IU (where M≤N, K ≤M), a group of external outputs of the number of groups in the QK block, a group of external outputs of the initial digits of groups in the QB block, the first group of the (N-M+1)-th detection blocks 1 ₁ , 1 ₂ , …, 1 _{(n-m +1)} , first groups 2 ₁ , 2 ₂ , …, 2m from M elements OR with inverse input of the first group of detection blocks 1 ₁ , 1 ₂ , …, 1 _(N-M+1) , second group from (M-1 )-th detection blocks 3 ₁ , 3 ₂ , …, 3 _(M-1) , second groups of I elements OR with inverse input 4 ₁ , 4 ₂ , …, 4( _M-1 ), corresponding 1st blocks of the same name detecting the second group 3 ₁ , 3 ₂ , 3 _(M-1) , (where I=1, ... (M-1)), the first group of (N-M+1) elements AND 5 ₁ , 5 ₂ , 5 _(N-M+1) , second group of (M-1) elements AND with inverse inputs 6 ₁ , 6 ₂ , …, 6 _(M-1) , third group of (N-1) elements And with an inverse input 7 ₂ , 7 ₃ , ..., 7 _N and a unit counting unit 8, and an internal N-bit bus of the initial digits of explosive groups has been introduced,

Moreover, the bits of the external input data bus ID in groups of M bits, each of which begins with the j-ro bit (j=1, ..., (N-M+1)), are connected to the second direct inputs of the OR elements with the inverse input of the first groups 2 ₁ , 2 ₂ , …, 2m of the corresponding j-th detection block 1j from the first group 1 ₁ , 1 ₂ , 1 _(N-M+1) , and the first inverse inputs of the OR elements with the inverse input of the first groups 2 ₁ , 2 ₂ , ..., 2m are connected to the M bits of the same name, starting from the first to the M-th bit, of the external bus for setting the capacity of the IU groups, while the outputs of the OR elements with the inverse input of the first groups 2 ₁ , 2 ₂ , 2m of the j-th detection unit 1j from the first groups 1 ₁ , 1 ₂ , …, 1 _(N-M+1) are connected to the corresponding inputs of the 5j element AND from the first group 5 ₁ , 5 ₂ , …, 5 _(N-M+1) ,

wherein the bits of the external input data bus ID in groups of I bits, each of which starts from the Nth bit to the (N-M+2) th bit (I=1, ..., (M-1)), are connected to the second direct lines inputs of OR elements with inverse input of second groups 4₁, 4₂, … 4_(M-1) corresponding I-th detection block 3_I from the second group 3₁, 3₂, …, 3_(M-1), and the first inverse inputs of the OR elements with the inverse input of the second groups 4₁, 4₂, …, 4_(M-1) connected to the bits of the external bus for setting the capacity of the IU groups in groups of I bits, starting from the first to the (M-1)th bit corresponding to the Ith detection block 3₁ from the second group 3₁, 3₂, …, 3_(M-1), while the outputs of OR elements with inverse inputs of the second groups are 4₁, 4₂, …, 4_(M-1) corresponding I-th detection block 3_I from the second group 3₁, 3₂, …, 3_(M-1) connected to the corresponding direct inputs of the first element AND with inverse inputs from the second group 6₁, 6₂, …, 6_(M-1), the inverse inputs of which are connected to the bits of the external bus for setting the capacity of the IU groups in groups of (M-I) bits, each of which starts from the M-th bit to the second bit,

in addition, the outputs of AND elements from the first group 5 ₂ , 5 ₃ , ..., 5 _(N-M+1) , starting from the second to the (N-M+1)th element, are connected to the direct inputs of the first M And elements of the same name with inverse input from the third group 7 ₂ , 7 ₃ , …, 7 _(N-M+1) , and the outputs of AND elements with inverse inputs from the second group 6 _(M-1) , 6 _(M-2) , …, 6 ₁ , starting from the (M-1)th element to the first element, are connected, respectively, to the direct inputs of the elements AND with the inverse input from the third group 7 _(N-M+2) , ..., 7 _N ,

in this case, the first inverse inputs (N-2) of elements And from the third group 7 ₃ , 7 ₄ , ..., 7 _N , starting from the third element 7 ₃ to the N-th element 7 _N , are connected to the direct inputs of the corresponding previous ones (N-2 ) elements AND from the third group 7 ₂ , 7 ₃ , …, 7 _(N-1) , starting from the second element 7 ₂ to the (N-1)th element 7 _(N-1) , and the first inverse input of the second element 7 ₂ is connected to the output of the first element AND from the first group 5 ₁ ,

in addition, the outputs of all (N-1) AND elements with an inverse input from the third group 7 ₂ , 7 ₃ , ..., 7 _N are the corresponding (N-1) bits of the same name, starting from the second bit to the Nth bit, the internal bus initial bits of explosive groups, in which the first bit is connected to the output of the first element AND from the first group 5 ₁ , and all N bits of the bus of initial bits of explosive groups are the corresponding bits of the group of external outputs of the initial bits of groups in the QB block and are also connected to the inputs of the units counting block 8, the outputs of which are the corresponding bits of the external output group of the number of groups in the QK block.

BRIEF DESCRIPTION OF THE DRAWINGS

In fig. Figure 1 shows a diagram of the proposed device. In fig. Figure 2 shows a timing diagram of the device operation for N=8 bit depth of input G blocks and the IU bus setting the bit depth of detected groups M=4.

In fig. 1, 2 and the following notations are used in the text:

AND - element AND,

BB - internal N-bit bus of initial digits of groups,

G (G1, G2, …, G10) - input N-bit data blocks,

ID - external N-bit input bus of data blocks G,

IU - external M-bit input bus for setting the number of groups, where M≤N,

K is the depth of detected groups, where K≤M,

M - maximum capacity of detected groups, where M≤N,

N is the width of the input data block,

OR - OR element,

QK - group of external outputs of the number of groups in the block,

QB - group of external outputs of the initial digits of groups in the block,

1 ₁ , 1 ₂ , …, 1 _(N-M+1) - the first group of (N-M+1) detection blocks,

2 ₁ , 2 ₂ , …, 2 _M - the first groups of M elements OR with the inverse input of the first

groups of detection blocks 1 ₁ , 1 ₂ , …, 1 _(N-M+1) ,

3 ₁ , 3 ₂ , …, 3 _(M-1) - the second group of (M-1) detection blocks,

4 ₁ , 4 ₂ , 4 _(M-1) - second groups of I OR elements with inverse input,

corresponding I-th detection blocks of the second group 3 ₁ , 3 ₂ , …, 3 _(M-1) ,

where I=1, … (M-1),

5 ₁ , 5 ₂ , …, 5 _(N-M+1) - the first group of the (N-M+1)th elements AND,

6 ₁ , 6 ₂ , …, 6 _(M-1) - the second group of (M-1)th AND elements with inverse inputs,

7 ₂ , 7 ₃ , …, 7 _N - the third group of (N-1) elements AND with an inverse input,

8 - unit counting block.

The proposed device contains an external N-bit input data bus ID data blocks G, an external M-bit bus for setting the capacity of groups IU (where M≤N, K≤M), a group of external outputs for the number of groups in the QK block, a group of external outputs of the initial digits of groups in block QB, the first group of (N-M+1) detection blocks 1 ₁ , 1 ₂ , 1 _(N-M+1) , the first groups 2 ₁ , 2 ₂ , …, 2 _M of M elements OR with inverse input of the first group of detection blocks 1 ₁ , 1 ₂ , …, 1 _(N-M+1) , the second group of (M-1) detection blocks 3 ₁ , 3 ₂ , …, 3( _M-1 ), the second groups of I elements OR with inverse input 4 ₁ , 4 ₂ , …, 4 _(M-1) , corresponding identical I-th detection blocks of the second group 3 ₁ , 3 ₂ , …, 3 _(M-1) , (where I =1, ..., (M-1)), the first group of (N-M+1) elements AND 5 ₁ , 5 ₂ , 5 _(N-M+1) , the second group of (M-1)- th elements AND with inverse inputs 6 ₁ , 6 ₂ ,..., 6 _(M-1) , the third group of (N-1)th elements AND with inverse input 7 ₂ , 7 ₃ ,..., 7 _N and a unit counting block 8, and also introduced an internal N-bit bus of the initial digits of explosive groups.

The bits of the external input data bus ID in groups of M bits, each of which begins with the j-th bit (j=1, ..., (N-M+1)), are connected to the second direct inputs of the elements OR with the inverse input of the first groups 2 ₁ , 2 ₂ ,…, 2 _M of the corresponding j-th detection block 1j from the first group 1 ₁ , 1 ₂ , 1(N-M+1). The first inverse inputs of the OR elements with the inverse input of the first groups 2 ₁ , 2 ₂ , ..., 2 _M are connected to the same M bits, starting from the first to the M bit, of the external bus for setting the capacity of the IU groups. The outputs of the OR elements with the inverse input of the first groups 2 ₁ , 2 ₂ , 2 _M of the j-th detection block 1j from the first group 1 ₁ , 1 ₂ , …, 1 _(N-M+1) are connected to the corresponding inputs of the 5j-th AND element from the first group 5 ₁ , 5 ₂ , …, 5 _(N-M+1) .

The bits of the external input data bus ID in groups of I bits, each of which starts from the Nth bit to the (N-M+2) th bit (I=1, ..., (M-1)), are connected to the second direct inputs OR elements with inverse input of the second groups 4 ₁ , 4 ₂ , …, 4 _(M-1) of the corresponding I detection block 3 _I from the second group 3 ₁ , 3 ₂ , …, 3 _(M-1) . The first inverse inputs of the OR elements with the inverse input of the second groups 4 ₁ , 4 ₂ , ..., 4 _(M-1) are connected to the bits of the external bus for setting the capacity of the IU groups in groups of I bits, starting from the first to the (M-1)th bit , the corresponding I-th detection block 3 _I from the second group 3 ₁ , 3 ₂ , …, 3 _(M-1) . The outputs of OR elements with inverse inputs of the second groups 4 ₁ , 4 ₂ , …, 4 _(M-1) of the corresponding I detection block 3 _I from the second group 3 ₁ , 3 ₂ , …, 3 _(M-1) are connected to the corresponding direct inputs of the I-th element AND with inverse inputs from the second group 6 ₁ , 6 ₂ , ..., 6 _(M-1) , the inverse inputs of which are connected to the bits of the external bus for setting the capacity of the IU groups in groups of (M-1) bits, each of which starts from the Mth digit to the second digit.

Outputs of elements AND from the first group 5₂, 5₃, …, 5_(N-M+1), starting from the second to the (N-M+1)th element, are connected to the direct inputs of the first M elements of the same name AND with an inverse input from the third group 7₂, 7₃, …, 7_(N-M+1). Outputs of AND elements with inverse inputs from the second group 6_(M-1), 6_(M-2), …, 6₁, starting from the (M-1)th element to the first element, are connected, respectively, to the direct inputs of the elements AND to the inverse input from the third group 7_(N-M+2), ..., 7_N.

The first inverse inputs (N-2) of the AND elements from the third group 7₃, 7₄, ..., 7_N, starting from the third element 7₃up to Nth element 7_N, connected to the direct inputs of the corresponding previous (N-2) elements AND from the third group 7₂, 7₃, …, 7_(N-1), starting from the second element 7₂ to the (N-1)th element 7_(N-1), and the first inverse input of the second element is 7₂ connected to the output of the first AND element from the first group 5₁.

The outputs of all (N-1) AND elements with an inverse input from the third group 7 ₂ , 7 ₃ , ..., 7 _N are the corresponding (N-1) bits of the same name, starting from the second bit to the Nth bit, the internal bus of the initial bits of the groups An explosive whose first digit is connected to the output of the first element AND from the first group 5 ₁ . All N bits of the bus of the initial bits of the BB groups are the corresponding bits of the group of external outputs of the initial bits of the groups in the QB block and are also connected to the inputs of the units counting block 8, the outputs of which are the corresponding bits of the group of external outputs of the number of groups in the QK block.

DETAILED DESCRIPTION OF THE INVENTION

The operating principle of the proposed device is as follows.

The proposed device makes it possible to detect in N-bit blocks of input data G unit groups (rows) containing ≥K (K or more) unit bits from a given bit depth M (where K≤M, M≤N), determine the number of such groups and their location in blocks of data.

Input data blocks G are fed sequentially at each clock cycle to the external input data bus ID. The bit capacity K of detected unit groups is set on the external M bit bus IU in the form of a unitary K-bit row of unit bits, starting from the first bit, for example, for K=3 the value is set on the bus IU[4-1]=0111 for detected three or more bit unit groups with N=8 and M=4.

In the first group 1₁, 1₂, …, 1_(N-M+1) and the second group 3₁, 3₂, …, 3_(M-1) detection blocks on OR elements with inverse input of the first 2₁, 2₂, 2_M and second 4₁, 4₂, …, 4_I groups, the most significant bits from the ID input data bus are masked, corresponding to the zero bits from the bus for specifying the width of the IU groups. In this case, single values are formed at the outputs of the corresponding masked OR elements with an inverse input, and the corresponding bit values from the ID input data bus for a given bit depth of the detected IU groups are transferred to the outputs of the non-masked OR elements with an inverse input. Moreover, in the first group 1₁, 1₂, …, 1_(N-M+1) detection blocks, M bit groups are distinguished, and in the second group there are 3₁, 3₂, …, 3_(M-1)detection blocks corresponding allocation of I bit groups, where I=1, ... (M-1).

Next, in the first group of (N-M+1) elements AND 5 ₁ , 5 ₂ , ..., 5 _(N-M+1) a check is made for the presence of single groups containing K single bits. In the second group

6 ₁ , 6 ₂ , 6 _(M-1) from the (M-1)th elements And with inverse inputs, a check is made for the presence of unit groups containing up to I unit bits, respectively, where 1 = 1, ... (M-1 ). When identifying single groups corresponding to a given value of K on the IU bus, at the outputs of the corresponding elements And the first 5 ₁ , 5 ₂ , 5 ( _N-M+1 ) and the second 6 ₁ , 6 ₂ , ..., 6 _(M-1) groups single values are formed.

If there are unit groups containing more than a specified number of >K in the input blocks G on the ID bus, several desired unit groups will be identified on the IU bus (unit values will be set at the outputs of neighboring elements And the first 5 ₁ , 5 ₂ , ..., 5( _{N-M +1} ) and/or the second 6 ₁ , 6 ₂ , …, 6( _M-1 ) groups. Masking of adjacent unit groups belonging to the same group in the input block ID is carried out in the third group 7 ₂ , 7 ₃ , …, 7 _N elements. And with an inverse input. In this case, a single value is maintained at the outputs of the elements corresponding to the initial digits of the identified unit groups.

The values from the outputs of the third group of elements AND 7 ₂ , 7 ₃ , ..., 7 _N are the corresponding bits of the internal N bit bus BB of the initial bits of the groups and then go to the group of inputs of the unit counting block 8, in which the number of identified unit groups in the current block is counted input data ID.

Next, the values from the output of the unit counting block 8 are transferred to the group of external outputs of the number of groups in the QK block, and the values of the bits from the bus of the initial bits of the BB groups are the corresponding bits of the group of external outputs of the initial bits of the groups in the QB block.

The proposed device works as follows.

In fig. Figure 2 shows a time diagram for identifying single groups in the input N=8 bit ten data blocks G1, G2, G10, with a maximum bit capacity of M=4 and setting the bit depth of K=1, 2, 3, 4 detected groups. In this case, the first group contains five detection blocks 1₁, 1₂, …, 1₅, in the second group there are three detection blocks 3₁, 3₂, 3₃, four OR elements with inverse input in the first groups 2₁, 2₂, …, 2₄, from one to three OR elements with inverse input in the second groups 4₁, 4₂, 4₃, five elements And in the first group 5₁, 5₂, …, 5₅, three AND elements with inverse inputs 6₁, 6₂, 6₃ and seven AND elements with inverse input of the third group 7₁, 7₃, ..., 7₈.

In cycles 1-3, groups containing two or more single bits K=2 (IU[4-1]=0011) are detected in three input data blocks G1, G2, G3.

In clock 1, the code IO[8-1]=1101 1011 of the first block G1, containing three two-bit unit groups, is set on the external 8-bit input data bus. For a given bit capacity K=2 (IU[4-1]=0011) in the first group 1 ₁ , 1 ₂ , ..., 1 ₅ and the second group 3 ₁ , 3 ₂ , 3 ₃ detection blocks on OR elements with an inverse input of the first group 2 ₁ , 2 ₂ , 2 ₄ and the second group 4 ₁ , 4 ₂ , 4 ₃ groups mask the two most significant bits from the ID bus. Next, in the first group 5 ₁ , 5 ₂ , ..., 5 ₅ AND elements and the second group 6 ₁ , 6 ₂ , 6 ₃ of AND elements with inverse inputs, unit groups containing two unit bits are identified and unit values are generated at the corresponding outputs - for input code ID[8-1]=1101 1011 the values 5[5-1]=01001 and 6[1-3]=010 are formed, corresponding to the initial bits of the three identified unit groups containing K=2 unit bits each, which are without masking through the third group 7 ₁ , 7 ₃ , …, 7 ₈ AND elements with an inverse input are transmitted to the internal BB bus and then to the group of external outputs QB of the initial digits of the groups in the block QB[8-1]=01001001. In addition, in the unit counting block 8, unit groups are counted and a binary code is generated for the number of unit groups in the QK=3 block transmitted to the group of external outputs.

In clock 2, the code ID[8-1]=1011 1011 of the second block G2 is set on the external 8-bit input data bus, containing one-bit, three-bit and two-bit unit groups. For a given ID code, at the outputs of the first group 5 ₁ , 5 ₂ , ..., 5 ₅ AND elements and the second group 6 ₁ , 6 ₂ , 6 ₃ from the AND elements with inverse inputs, the values 5[5-1]=11001 and 6[ are generated 1-3]=000, corresponding to the initial bits of the identified unit groups containing K=2 unit bits. In this case, the unit values set at the outputs of the adjacent fourth and fifth elements 5[5-4]=11 correspond to one group (row) of three unit bits in the input block ID. Therefore, in the third group 7 ₂ , 7 ₃ , ..., 7 ₈ elements And with an inverse input, the single value from the output of the fifth element 5[5] = 1 is masked and on the internal bus BB and then in the group of external outputs QB the initial digits of the groups in the block are set code QB[8-1]=0000 1001, corresponding to two unit groups containing two or more unit bits K=2 (IU[4-1]=0011). In addition, in the unit counting block 8, unit groups are counted in the input block G2 and a binary code is generated for the number of unit groups in the QK=2 block.

In clock 3, the code ID[8-1]=1110 1111 of the third block G3 is set on the external 8-bit input data bus, containing three-bit and four-bit unit groups. For a given ID code, at the outputs of the first group 5 ₁ , 5 ₂ , 5 ₅ AND elements and the second group 6 ₁ , 6 ₂ , 6 ₃ from AND elements with inverse inputs, the values 5[5-1]=00111 and 6[1- 3]=011, corresponding to the initial bits of the identified unit groups containing K=2 unit bits. In this case, the unit values set at the outputs of the adjacent first, second and third elements 5[3-1]=111 correspond to one group (row) of four unit bits, and those set at the outputs of the adjacent second and third elements 6[2-3] =11, correspond to one group (row) of three one bits in the input block ID. Therefore, in the third group of 7 ₂ , 7 ₃ , 7 ₈ elements And with an inverse input, single values are masked from the outputs of elements 5 [3-2] = 11 and from the output of element 6 [2] = 1, and then on the internal bus BB and in the group of external outputs QB of the initial bits of the groups in the block is set to code QB[8-1]=0010 0001, corresponding to two unit groups containing two or more unit bits K=2 (IU [4-1]=0011). Also, in the unit counting block 8, unit groups are counted in the input block G3 and a binary code for the number of unit groups is generated in the QK=2 block.

In cycles 4-6, groups containing three or more single bits K=3 (IU[4-1]=0111) are detected in the input data blocks G4, G5, G6.

In clock 4, the code ID[8-1]=0101 1101 of the fourth G4 block is set on the external 8-bit input data bus, containing two one-bit and one three-bit unit groups. For a given ID code, only at the output of the third element of the first group 5 ₁ , 5 ₂ , ..., 5 ₅ elements And a single value 5 [3] = 1 is formed, corresponding to the initial third digit of the identified unit group containing K = 3 single bits. Therefore, further in the group of external outputs QB of the initial digits of the groups in the block, the code QB[8-1]=0000 0100 is set, and in the unit counting block 8, unit groups are counted in the input block G4 and a binary code for the number of groups in the block QK=1 is generated.

In clock 5, the code ID[8-1]=1111 0111 of the fifth block G5 is set on the external 8-bit input data bus, containing three-bit and four-bit unit groups. For a given ID code, a single value is generated at the outputs of the first AND element 5[1]=T, the fifth AND element 5[5]=1 and the third AND element with inverse input 6[3]=1. In this case, single values from the outputs of AND elements 5[5]=1 and 6[3]=1 correspond to adjacent bits in the input data on the ID bus and belong to one group (row) of four single bits. Therefore, in the third group 7 ₂ , 7 ₃ , ..., 7 ₈ elements And with an inverse input, a single value from the output of element 6[3] = 1 is masked, and then on the internal bus BB and in the group of external outputs QB the initial digits of the groups in the block are set code QB[8-1]=0001 0001, corresponding to two unit groups containing three or more unit bits K=3 (UI[4-1]=0111). Also, in the unit counting block 8, unit groups are counted in the input block G5 and a binary code for the number of groups is generated in the QK=2 block.

In clock 6, the code ID[8-1]=1110 0111 of the sixth G6 block is set on the external 8-bit input data bus, containing two three-bit unit groups. For a given ID code, single values are generated at the outputs of the first AND element 5[1]=1 and the third AND element with inverse input 6[3]=1, which generates the code on the internal BB bus and in the group of external outputs QB of the initial digits of the groups in In the block, the code QB[8-1]=0010 0001 is set, and in the unit counting block 8, unit groups are counted in the input block G6 and a binary code for the number of groups is generated in the block QK=2.

In cycles 7-8, groups containing four or more single bits K=4 (IU[4-1]=1111) are detected in the input data blocks G7, G8.

In clock 7, the code ID[8-1]=1111 1011 of the seventh G7 block is set on the external 8-bit input data bus, containing five-bit and two-bit unit groups. For a given ID code, single values are formed at the outputs of the adjacent fourth and fifth elements AND 5[5-4]=11, which correspond to one group (row) of five single bits. Therefore, in the third group 7 ₂ , 7 ₃ , ..., 7 ₈ elements And with an inverse input, a single value from the output of the element 5[5] = 1 is masked, and then in the group of external outputs QB of the initial digits of the groups in the block the code QB[8- 1]=0000 1000, corresponding to one unit group containing four or more unit bits K=4 (IU[4-1]=1111). Also in the unit counting block 8, unit groups are counted in the input block G7 and a binary code for the number of groups in the QK=1 block is generated.

In clock 8, the code ID[8-1]=1011 1111 of the eighth G8 block is set on the external 8-bit input data bus, containing one-bit and six-bit unit groups. For a given ID code, single values are formed at the outputs of the adjacent first, second and third elements AND 5[3-1]=111, which correspond to one group (row) of six single bits. Therefore, in the third group 7 ₂ , 7 ₃ , …, 7 ₈ elements AND with an inverse input, a single value from the outputs of elements 5[3-2]=11 is masked, and then in the group of external outputs QB of the initial digits of the groups in the block the code QB[ is set 8-1]=0000 0001, corresponding to one unit group containing four or more unit bits K=4 (IU[4-1]=1111). Also in the unit counting block 8, unit groups are counted in the input block G7 and a binary code for the number of groups in the QK=1 block is generated.

In cycles 9-10, groups containing one or more single bits K=1 (IU[4-1]=0001) in the input data blocks G9, G10 are detected.

In clock 9, the code ID[8-1]=1011 1011 of the ninth G9 block is set on the external 8-bit input data bus, containing one-bit, two-bit and three-bit unit groups. For a given ID code, single values are formed at the outputs of the adjacent first and second elements AND 5[2-1]=11, which correspond to one group (row) of two single bits, and at the outputs of the adjacent fourth and fifth elements AND 5[5-4 ]=11 and the third AND element with an inverse input 6[3]=1, which correspond to one group (row) of three unit bits, and also a single value is formed on the first AND element 6[1]=1, corresponding to a single-bit group. Therefore, in the third group 7 ₂ , 7 ₃ , …, 7 ₈ elements And with an inverse input, single values from the outputs of elements 5[2]=1, 5[5]=1, 6[3]=1 are masked, and then in the group external outputs QB of the initial bits of groups in the block, the code QB[8-1]=1000 1001 is set, corresponding to three unit groups containing one or more unit bits K=1 (IU[4-1]=0001). Also in the unit counting block 8, unit groups are counted in the input block G9 and a binary code for the number of groups is generated in the QK=3 block.

In clock 10, the code ID[8-1]=0101 1010 of the tenth G10 block is set on the external 8-bit input data bus, containing two one-bit and one two-bit unit groups. For a given ID code, single values are formed at the outputs of the second element AND 5[2]=1, adjacent fourth and fifth elements AND 5[5-4]=11, which correspond to one group (row) of two single bits, and also a single the value on the second element AND is 6[2]=1. Therefore, in the third group 7 ₂ , 7 ₃ , ..., 7 ₈ elements And with an inverse input, a single value from the output of the element 5[5] = 1 is masked, and then in the group of external outputs QB of the initial digits of the groups in the block the code QB[8- 1]=0100 1010, corresponding to three unit groups containing one or more unit bits K=1 (IU[4-1]=0001). Also, in the unit counting block 8, unit groups are counted in the input block G10 and a binary code for the number of groups is generated in the QK=3 block.

Thus, for N bit input data blocks, unit groups of a given K bit depth from M bits are identified, such groups are counted and their location in the input blocks is carried out.

The proposed device can be used for hardware implementation of statistical tests developed by the Information Technology Laboratory of the National Institute of Standards and Technology (NIST, USA), the purpose of which is to determine the measure of randomness of binary sequences generated by random number generators. In particular, the proposed device counts the number of unit groups of a given K dimension in N-bit input blocks.

When processing the results of physical experiments, the proposed device ensures the identification of events of a given dimension, determination of their number and placement in input blocks.

The above information allows us to conclude that the proposed device solves the problem, has regularity of nodes and connections, and corresponds to the claimed technical result - expanding the arsenal of means for the same purpose in terms of ensuring the possibility of detecting groups of single bits of a given bit depth, determining the number of given groups and their placement in blocks of data.

Claims (6)

The device for detecting specified K-bit groups of unit bits in data blocks contains an external N-bit input data bus ID data blocks G, an external M-bit bus for setting the width of groups IU (where M≤N, K≤M), a group of external outputs of the number of groups in block QK, group of external outputs of initial bits of groups in block QB, first group of (N-M+1)-th detection blocks 1 ₁ , 1 ₂ , 1 _(N-M+1) , first groups 2 ₁ , 2 ₂ , …, 2 _(M-1) from M elements OR with inverse input of the first group of detection blocks 1 ₁ , 1 ₂ , …, 1 _(N-M+1) , the second group from the (M-1)th detection blocks 3 ₁ , 3 ₂ , …, 3 _(M-1) , second groups of I elements OR with inverse input 4 ₁ , 4 ₂ , …, 4 _(M-1) , corresponding identical I-th detection blocks of the second group 3 ₁ , 3 ₂ , …, 3 _(M-1) , (where I=1, ... (M-1)), the first group of (N-M+1) elements AND 5 ₁ , 5 ₂ , …, 5 _(N-M+1) , the second group of (M-1)th AND elements with inverse inputs 6 ₁ , 6 ₂ , ..., 6 _(M-1) , the third group of (N-1)th AND elements with an inverse input 7 ₁ , 7 ₂ , ..., 7 _N and a unit counting unit 8, and an internal N bit bus of the initial digits of explosive groups has been introduced, Moreover, the bits of the external input data bus ID in groups of M bits, each of which starts with the j-th bit (j=1, ..., (N-M+1)), are connected to the second direct inputs of the OR elements with the inverse input of the first groups 2 ₁ , 2 ₂ , …, 2 _M of the corresponding j-th detection block 1j from the first group 1 ₁ , 1 ₂ , …, 1 _(N-M+1 ), and the first inverse inputs of the OR elements with the inverse input of the first groups 2 ₁ , 2 ₂ , …, 2 _M are connected to the M bits of the same name, starting from the first to the M bit, of the external bus for setting the capacity of the IU groups, while the outputs of the OR elements are with the inverse input of the first groups 2 ₁ , 2 ₂ , …, 2 _M j th detection block 1j from the first group 1 ₁ , 1 ₂ , …, 1 _(N-M+1) are connected to the corresponding inputs of the 5j element And from the first group 5 ₁ , 5 ₂ , …, 5 _{(N-M+ 1)} , wherein the bits of the external input data bus ID in groups of I bits, each of which starts from the Nth bit to the (N-M+2) th bit (I=1, ..., (M-1)), are connected to the second direct lines inputs of OR elements with an inverse input of the second groups 4 ₁ , 4 ₂ , …, 4 _(M-1) of the corresponding I-th detection block 3 ₁ from the second group 3 ₁ , 3 ₂ , …, 3 _(M-1) , and the first inverse inputs of OR elements with the inverse input of the second groups 4 ₁ , 4 ₂ , ..., 4( _M-1 ) are connected to the bits of the external bus for setting the capacity of the IU groups in groups of I bits, starting from the first to the (M-1)th bit of the corresponding I-th detection block 3 _I from the second group 3 ₁ , 3 ₂ , …, 3( _M-1 ), while the outputs of the OR elements with inverse inputs of the second groups 4 ₁ , 4 ₂ , …, 4( _M-1 ) of the corresponding The I-th detection block 3 _I from the second group 3 ₁ , 3 ₂ , …, 3( _M-1 ) is connected to the corresponding direct inputs of the I-th element AND with the inverse inputs from the second group 6 ₁ , 6 ₂ , …, 6( _{M -1} ), the inverse inputs of which are connected to the bits of the external bus for setting the capacity of the IU groups in groups of (M-1) bits, each of which starts from the M-th bit to the second bit, in addition, the outputs of AND elements from the first group 5 ₂ , 5 ₃ , ..., 5 _(N-M+1) , starting from the second to the (N-M+1)th element, are connected to the direct inputs of the first M And elements of the same name with inverse input from the third group 7 ₂ , 7 ₃ , …, 7 _(N-M+1) , and the outputs of AND elements with inverse inputs from the second group 6 _(M-1) , 6( _M-2 ), …, 6 ₁ , starting from the (M-1)th element to the first element, are connected, respectively, to the direct inputs of the elements AND to the inverse input from the third group 7 _(N-M+2) , ..., 7 _N , in this case, the first inverse inputs (N-2) of elements And from the third group 7 ₃ , 7 ₄ , ..., 7 _N , starting from the third element 7 ₃ to the N-th element 7 _N , are connected to the direct inputs of the corresponding previous ones (N-2 ) elements AND from the third group 7 ₂ , 7 ₃ , …, 7 _(N-1) , starting from the second element 7 ₂ to the (N-1)th element 7 _(N-1) , and the first inverse input of the second element 7 ₂ is connected to the output of the first element AND from the first group 5 ₁ , in addition, the outputs of all (N-1) AND elements with an inverse input from the third group 7 ₂ , 7 ₃ , ..., 7 _N are the corresponding (N-1) bits of the same name, starting from the second bit to the Nth bit, the internal bus initial bits of explosive groups, in which the first bit is connected to the output of the first element AND from the first group 5 ₁ , and all N bits of the bus of initial bits of explosive groups are the corresponding bits of the group of external outputs of the initial bits of groups in the QB block and are also connected to the inputs of the units counting block 8, the outputs of which are the corresponding bits of the external output group of the number of groups in the QK block.

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