RU2787294C1 - Device for detecting overlapping bit patterns in a binary sequence - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention relates to the field of computer technology. The device contains an external data input ID, a group of external inputs of the template IS, containing K bits, a group of external inputs IK for setting the bit depth of the input template IS, containing m bits, a group of external data outputs QB, a group of external outputs of the number of templates QS, and also contains an RS flip-flop start-stop TSS 1, the first bit counter STB 2, the output buffer OB 3, the second subtractive counter of bits of the STK template 4, the AND element 5, the input data shift register RD 6, the DC decoder 7, a group of (K-1) elements OR 81 , 82, 8(K-1), the first group of K-elements AND, the second group of K-elements AND, comparator COMP 11 and the third counter of the number of patterns CTS 12, as well as external inputs of the clock signal IC, device start START, device stop STOP and internal BDC bit decoding bus.

EFFECT: detecting IK bit groups in the input N-bit binary number corresponding to the IK bit given group pattern IS, which contains a given sequence of 1's and 0's.

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Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer technology, in particular to data processing devices, and can be used to build automation tools and functional units of control systems, as well as to analyze the properties of generators of pseudo-random sequences of binary numbers and to process the results of physical experiments.

PRIOR ART

A serial-type device for detecting groups of zero and one bits and determining their number is known (RU No. 2680759, IPC G06F 7/74, declared 16.02.2018, published 26.02.2019, Bull. No. 6), containing an external data input DI, a group of external QO data output group, QG group number external output group, QZ zero number external output group, QU number of ones external output group, QZU difference of ones and zeros external output group, TSS 1 first start-stop RS-trigger, unit detector unit and zeros 2, the third D-flip-flop for enabling the count of groups TSE 7, the third element AND 8, the first group counter CG 9, the second bit counter CB 10, the output buffer OB 11, the fourth 12, the fifth 13 and the sixth 14 elements AND, the third counter of zeros CZ 15, the fourth counter of units CU 16, the fifth reversible zero-one counter CZU 17 and the block of the difference code converter 18, and the block of the detector of ones and zeros 2 consists of the first 3 and second 4 AND elements with one inverse input, the OR element 5 and the second TU bit control D-flip-flop 6 and contains three outputs, and the difference code converter block 18 contains a group of (M-2) OR elements 19, a group of (M-1) AND elements 20 and a group of (M-1) elements EXCLUSIVE OR 21, where M=[log ₂ N]+1 (smaller integer), and N is the dimension of the length of the input data sequence, with the first group counter CG 9, the second bit counter CB 10, the output buffer OB 11, the third zero counter CZ 15 and the fourth unit counter CU 16 have a capacity of M, and the fifth reversible counter of zero-ones CZU 17 has a capacity of (M + 1), and external flags of result readiness FE, “Buffer full” FF, “Buffer empty” FZ and a flag "zeros more than ones" F01. At the same time, in the output buffer OB 11, in even addresses, starting from the zero address, the number of zero bits in groups is indicated, and in odd addresses, starting from the first address, the number of single bits in groups is indicated.

This device detects groups of single and zero bits, determines the total number and by groups of single and zero bits, determines the ratio of the difference between the number of single and zero bits in the input data sequence of dimension N. The disadvantage of this device is the identification of groups of bits of arbitrary dimension and the lack of means to set the dimension of unit and zero groups.

A device for detecting groups in a binary sequence is known (RU No. 2728957, IPC G06F 7/74, H03K 21/00 declared on 01/15/2020, published on 08/03/2020, Bull. No. 22), containing an external data input DI, a group of external data outputs QO , group of external outputs of the number of groups QG, group of external outputs of the number of zeros QZ, group of external outputs of the number of ones QU, group of external outputs "difference of ones and zeros" QZU, groups of external outputs of the number of ones in the maximum group MU, number of zeros in the maximum group MZ, group numbers of the maximum group of ones NGMU, group numbers of the maximum group of zeros NGMZ, numbers of the beginning of the maximum group of ones bits NMU and numbers of the beginning of the maximum group of zero bits NMZ, the first RS-trigger start-stop TSS 1, the detector block of ones and zeros 2, the third D- group count enable trigger TSE 7, third element AND 8, first adder SMG 9, second bit counter CB 10, output buffer OB 11, fourth 12, fifth 13 and sixth 14 elements AND, third zero counter CZ 15, fourth counter CU 16, fifth reversible zero-one counter CZU 17 and difference code converter unit 18, first counter CNB 22, first register RNM 23, second adder SNM 24, second 25, third 26, fourth 27, fifth 28, sixth 29, seventh 32 and eighth 35 registers, the first comparator 30 for comparing the number of single bits, the seventh element And 31, the second comparator 33 for comparing the number of zero bits, the eighth element And with one inverse input 34, and also external flags for the result being ready FE, "Buffer full" FF, "Buffer empty" FZ and "zeroes greater than ones" flag F01.

This device detects the maximum groups of single and zero bits and determines the total number of groups, group numbers and the beginning of groups in a binary sequence. The reasons hindering the achievement of the technical result indicated below include the lack of means for setting the dimension of unit and zero groups.

The closest device for the same purpose to the claimed invention in terms of the totality of features is, taken as a prototype, a device for detecting single groups of bits in a binary sequence RU No. Bull. No. 2) containing an external data input DI, a group of external data outputs QB, a group of external outputs of the number of groups QG, the first RS start-stop trigger TSS 1, the first bit counter CTB 2, the first bit number register of the RGB group 3, the first element AND 4 , first element OR 5 with one inverted input, second one-bit flip-flop TR1 6, second element AND 7 with one inverted input, second CTU counter 8, lower limit equal block 9, upper limit equal block 10, third lower limit trigger TRL 11 , the fourth trigger of the upper limit TRM 12, the third 13 and the fourth 14 elements AND with two inverse inputs, the second element OR 15, the output buffer OB 16 and the third counter of the number of groups CTG 17, as well as the external inputs of the asynchronous setting to the zero state CLR, start device START, device stops STOP and clock C, external input buses of the lower limit GL and upper limit GM of the range of single bits, external exchange control bus EO, external flag "Buffer full" FF and flag d "Buffer empty" FZ

This device identifies single groups of a given dimension, determines the number of groups and their location in the input data sequence. The disadvantage of this device is the lack of means for detecting given patterns containing a set of groups (rows) of both zero and single bits.

OBJECT OF THE INVENTION

The objective of the invention is to develop hardware for studying the properties of generators of pseudo-random sequences of binary numbers, as well as for processing the results of physical experiments.

When analyzing generators of pseudo-random sequences of binary numbers, the device is designed to identify given patterns from a set of groups (rows) of zero and one bits.

When processing the results of physical experiments, the device is designed to identify non-periodic events (regions) - given durations of events and intervals between them, as well as event coordinates.

The technical result of the invention is the expansion of functionality in terms of the ability to set the values of the templates and their capacity, determine the number of identified templates and their location in the input data sequence.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved in that the device for detecting overlapping bit patterns in a binary sequence contains an external data input ID, a group of external inputs of the IS template containing K bits, a group of external inputs IK for setting the bit depth of the input template IS, containing m bits (where m=]log ₂ (K+1)[greater integer), QB external data output group, QS template number external output group,

and also contains the RS trigger start-stop TSS 1, the first bit counter STB 2, the output buffer OB 3, the second subtracting counter of bits of the STK 4 template, the AND element 5, the input data shift register RD 6, the decoder DC 7, a group of (K -1) OR elements 8 ₁ , 8 ₂ , ..., 8 _(K-1) , the first group of K elements AND 9 ₁ , 9 ₂ , ..., 9 _k , the second group of K elements AND 10 ₁ , 10 ₂ , ... , 10 _k , comparator COMP 11 and the third counter of the number of patterns CTS 12,

as well as external inputs of the clock signal IC, device start START, device stop STOP and internal bit decoding bus BDC, bus of the first compare operand VA, bus of the second compare operand BB, internal equality flag FEQ and internal write flag FW, external exchange control bus EO , external "Buffer full" flag FF and "Buffer empty" flag FZ,

moreover, the external clock input of the IC device is connected to the synchronization inputs C of the RS start-stop flip-flop TSS 1, the first bit counter CTB 2, the output buffer OB 3, the second subtracting counter of bits of the pattern STK 4, the input data shift register RD 6 and the third counter of the number of patterns CTS 12,

the external start input of the START device is connected to the input S of the synchronous setting to a single state of the RS start-stop trigger TSS 1, to the input L of the permission to write the second subtracting counter of the bits of the STK 4 template, to the inputs R of the synchronous setting to the zero state of the first counter bit STV 2, output buffer OB 3, input data shift register RD 6 and third pattern counter CTS 12,

the external stop input of the STOP device is connected to the input R of the synchronous set to zero state of the RS start-stop trigger TSS 1,

moreover, the direct output of the RS-trigger start-stop TSS 1 is connected to the inputs CE to enable the operation of the first bit counter CTB 2 and the input data shift register RD 6,

the external data input ID is connected to the input SI of the serial input of the shift register of the input data RD 6, the group K of the outputs of which is connected to the first inputs of the corresponding elements of the same name of the first group of K elements AND 9 ₁ , 9 ₂ , ..., 9 _k , the outputs of which are the corresponding ones of the same name bits of the internal bus of the first comparison operand VA, which is connected to the first group of inputs of the comparator COMP 11,

K bits of the group of external inputs of the IS template are connected to the first inputs of the corresponding elements of the same name of the second group of K elements And 10 ₁ , 10 ₂ , ..., 10 _k , the outputs of which are the corresponding identical bits of the internal bus of the second comparison operand BB, which is connected to the second group of inputs comparator COMP 11, the output of which is an internal equality flag FEQ and is connected to the second input of the AND element 5,

moreover, the group of external inputs IK of setting the bit depth of the input template IS is connected to the corresponding group of D-inputs of the second counter of bits of the STK 4 template and the address inputs of the decoder DC 7, in which the outputs, from the first output to the (K-1)-th output, are connected to the first inputs of the corresponding elements of the same name of the group of (K-1) elements OR 8 ₁ , 8 ₂ , ..., 8 _(K-1) , the outputs of which are the corresponding digits of the same name, from the first digit to the (K-1) th digit, the internal bus decoding of BDC bits, in which the K-th bit is connected to the K-th output of the decoder DC 7, and K bits of the internal bus for decoding BDC bits are connected to the second inputs of the corresponding elements of the same name of the first group from K elements AND 9 ₁ , 9 ₂ , ..., 9 _k and the second group of K elements AND 10 ₁ , 10 ₂ , ..., 10 _k , as well as the outputs of the elements of the group 8 ₁ , 8 ₂ , ..., 8 _(K-1) from (K-1) elements OR, starting from the output (K-1)-th element 8 _(K-1) to the second element 8 ₂ connected to the second inputs of the corresponding p previous elements OR of the group 8 ₁ , 8 ₂ , …, 8 _(K-1) , starting from the (K-2)-th element 8 _(K-2) to the first element 8 ₁ , and the second input (K-1)- th element 8 _(K-1) is connected to the K-th output of the decoder DC 7,

in addition, the direct output of the loan VO of the subtracting counter of the digits of the STK 4 template is connected to the inverse input of the operation enable CE of the counter of the digits of the STK 4 template and to the first input of the AND 5 element, the output of which is the internal recording flag FW and is connected to the inputs of the CE of the operation of the output buffer OB 3 and a third counter for the number of templates CTS 12,

moreover, the group of outputs of the first counter bit CTB 2 is connected to the group of information D-inputs of the output buffer OB 3, which is also connected to the external bus EO exchange control, and the corresponding outputs of the output buffer OB 3 are a group of external data outputs QB and external flags "Buffer full" FF and "Buffer empty" FZ, and the CTS pattern number counter output group 12 is the QS pattern number external output group.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. 1 shows a diagram of the proposed device. In FIG. 2 and FIG. 3 shows the timing diagrams of the device.

In FIG. 1-3 and the following notation is used in the text:

BUF - buffer with FIFO service discipline,

VA - internal bus of the first comparison operand,

BB - internal bus of the second comparison operand,

VO - counter loan output,

BDC - internal bit decoding bus,

C - clock input,

CE - work enable input,

COMP - comparison circuit (comparator),

ST - counter,

STV - counter of bits (digits),

STK - subtractive counter of pattern digits,

CTS - counter of the number of templates,

D - information inputs,

DC - decoder,

IC - external clock input,

ID - external data input,

IK - a group of external inputs for setting the bit width of the input template IS, containing m bits (where m=]log ₂ (K+1)[larger integer),

IS - a group of external template inputs containing K bits,

EO - external exchange control bus with OB output buffer,

FEQ - internal equality flag,

FW - internal write flag,

FF - external flag "Buffer full",

FZ - external flag "Buffer is empty",

K - bit depth of the template,

L - write permission input,

N - dimension (length) of the input data sequence,

OB - output buffer,

QS - group of external outputs of the number of templates,

QB - group of external data outputs,

RD - input data shift register,

RG - register,

R - input of synchronous setting to zero state,

S - input of synchronous setting to a single state,

SI - serial input of register RD,

START - external start input,

STOP - external stop input,

T - trigger,

TSS - start-stop trigger,

1 - RS trigger start-stop TSS,

2 - the first counter bit CTB,

3 - OB output buffer,

4 - the second subtractive counter of the digits of the STK template,

5 - element AND (AND),

6 - input data shift register RD,

7 - DC decoder,

8 ₁ , 8 ₂ , ..., 8 _(K-1) - a group of (K-1) elements OR (OR),

9 ₁ , 9 ₂ , ..., 9 _k - the first group of K elements AND (AND),

10 ₁ , 10 ₂ , ..., 10 _k - the second group of K elements AND (AND),

11 - comparator (COMP),

12 - the third counter of the number of CTS templates.

The proposed device contains an external data input ID, a group of external inputs of the template IS, containing K bits, a group of external inputs IK for setting the bit depth of the input template IS, containing m bits (where m=]log ₂ (K+1)[larger integer), a group of external data outputs QB, a group of external outputs for the number of templates QS, and also contains an RS-start-stop trigger TSS 1, the first bit counter STB 2, the output buffer OB 3, the second subtracting counter of bits of the template STK 4, the AND element 5, the input data shift register RD 6, decoder DC 7, a group of (K-1) elements OR 8 ₁ , 8 ₂ , ..., 8 _(K-1) , the first group of K elements AND 9 ₁ , 9 ₂ , ..., 9 _k , the second group of K elements AND 10 ₁ , 10 ₂ , ..., 10 _k , comparator COMP 11 and the third counter of the number of templates CTS 12.

The proposed device also includes external inputs of the clock signal IC, the start of the START device, the stop of the STOP device and the internal bit decoding bus BDC, the bus of the first compare operand VA, the bus of the second compare operand BB, the internal equality flag FEQ and the internal write flag FW, the external control bus EO exchange, external flag "Buffer full" FF and flag "Buffer empty" FZ.

The first bit counter STB 2 is designed to determine the number of the current bit (bit) of the input ID data sequence of dimension N. The second subtractive counter STC 4 is designed to count the first IC bits (bits) of the input data sequence ID and prohibit during this period (when VO(STK) =0) forming a single value of the internal write flag FW. The input data shift register RD 6 is designed to convert the input data sequence ID into parallel K-bit groups. The output buffer OB 3 is designed to accumulate the numbers of the most significant bits (digits) of the identified groups corresponding to a given template IS from the input data sequence ID.

The external clock input of the IC device is connected to the synchronization inputs C of the RS start-stop flip-flop TSS 1, the first bit counter CTB 2, the output buffer OB 3, the second subtractive counter of the pattern bits CTC 4, the input data shift register RD 6 and the third counter of the number of patterns CTS 12.

The external start input of the START device is connected to the input S of the synchronous setting to a single state of the RS-trigger start-stop TSS 1, to the input L of the permission to write the second subtracting counter of the bits of the STK 4 template, to the inputs R of the synchronous setting to the zero state of the first counter bit STV 2, output buffer OB 3, the input data shift register RD 6 and the third counter of the number of patterns CTS 12.

The external STOP input of the device is connected to the R input of the synchronous set to zero state of the RS start-stop flip-flop TSS 1.

The RS-trigger start-stop TSS 1 is designed to highlight the cycle of operation of the proposed device, between the START and STOP signals, for the input data sequence ID of dimension N. Moreover, the direct output of the RS-trigger start-stop TSS 1 is connected to the inputs CE to enable the operation of the first bit counter STV 2 and input shift register RD 6.

The external data input ID is connected to the input SI of the serial input of the shift register of the input data RD 6, the group K of the outputs of which is connected to the first inputs of the corresponding elements of the same name of the first group of K elements AND 9 ₁ , 9 ₂ , ..., 9 _k , the outputs of which are the corresponding names of the same name bits of the internal bus of the first comparison operand VA, which is connected to the first group of inputs of the comparator COMP 11.

K bits of the group of external inputs of the IS template are connected to the first inputs of the corresponding elements of the same name of the second group of K elements And 10 ₁ , 10 ₂ , ..., 10 _k , the outputs of which are the corresponding identical bits of the internal bus of the second comparison operand BB, which is connected to the second group of inputs comparator COMP 11, the output of which is an internal equality flag FEQ and is connected to the second input of the AND element 5.

The group of external inputs IK for setting the capacity of the input template IS is connected to the corresponding group of D-inputs of the second counter of bits of the STK 4 template and the address inputs of the decoder DC 7, whose outputs, from the first output to the (K-1)-th output, are connected to the first inputs corresponding elements of the same name of the group of (K-1) elements OR 8 ₁ , 8 ₂ , ..., 8 _(K-1) , the outputs of which are the corresponding digits of the same name, from the first digit to the (K-1)-th digit, the internal decryption bus BDC bits, in which the K-th bit is connected to the K-th output of the decoder DC 7.

To the bits of the internal decoding bus of the BDC bits are connected to the second inputs of the corresponding elements of the same name of the first group of K elements AND 9 ₁ , 9 ₂ , ..., 9 _k and the second group of K elements And 10 ₁ , 10 ₂ , ..., 10 _k . The outputs of the elements of the group 8 ₁ , 8 ₂ , ..., 8 _(K-1) from (K-1) elements OR, starting from the output of the (K-1)-th element 8(k-1) to the second element 8 ₂ , are connected with the second inputs of the corresponding previous elements OR of the group 8 ₁ , 8 ₂ , ..., 8 _(K-1) , starting from the (K-2)-th element 8 _(K-2) to the first element 8 ₁ , and the second input (K -1)-th element 8 _(k-1) is connected to the K-th output of the decoder DC 7.

The direct output of the loan VO of the subtracting counter of the digits of the STK 4 template is connected to the inverse input of the operation enable CE of the counter of the digits of the STK 4 template and to the first input of the element AND 5, the output of which is the internal recording flag FW and is connected to the inputs of the CE of the operation of the output buffer OB 3 and the third CTS 12 pattern counter.

The group of outputs of the first counter bit CTB 2 is connected to the group of information D-inputs of the output buffer OB 3, which is also connected to the external bus EO exchange control, and the corresponding outputs of the output buffer OB 3 are a group of external data outputs QB and external flags "Buffer full" FF and "Buffer empty" FZ. The pattern counter output group CTS 12 is a group of external outputs for the number of patterns QS.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows.

The proposed device allows you to detect IK-bit groups in the input N-bit binary number corresponding to the IK bit given group pattern IS, which contains a given sequence of 1 and zero bits. The device allows you to quickly change (set) the bit depth IK≤K and the values of the bits of the template IS. The device counts the number of groups corresponding to the given code of the IS template and determines the numbers of the highest digits of the identified input groups in the input N-bit binary number, which are written to the output buffer OB 3. In this case, the digits of the identified neighboring input groups that match the given IS template may overlap .

The bits of the input data sequence of dimension N are sequentially received at the external data input ID bit by bit, which are then transferred to the input of the serial input SI of the shift K of the bit register RD 6. On the shift register RD 6, a shift is made by one bit towards the higher bits from the 1st rank to the Kth rank. In this case, the bits of the code of the input binary sequence ID are converted into parallel K-bit codes at the outputs of the register RD 6.

The external data input ID bits begin to arrive in the next cycle after the START=1 signal and then arrive in each IC cycle. After entering the last N-th digit of the input binary number, a single stop signal STOP=l is set.

The device starts working after a single signal START=1 is applied, at which, along the edge of the clock signal IC, the code "IK" of the current bit width of the specified template IS is loaded into the subtractive counter of bits of the STK 4 template, the value of which is set on the external input K bit bus IS. On the following IK clock signals IC, a shift is made in the register RD 6, the bits (digits) of the input sequence ID are counted in the counter bits of the CTB and the subtraction in the counter of bits of the STK 4 template is performed until a single value is set at the output of the loan VO = 1 of the counter STK 4.

At the same time, the code "IK" of the current bit depth of the given template IS is transmitted to the inputs of the decoder DC 7. At the outputs of the decoder 7, unitary codes "1 from K" are formed, which are transmitted to the corresponding inputs of the group 8 ₁ , 8 ₂ , ..., 8 _(K-1) from (K-1) OR elements. A single value set at the output of the DC 7 decoder corresponding to the IK code is then sequentially transmitted along a chain of OR elements 8 ₁ , 8 ₂ , ..., 8 _(K-1) towards the lower digits. At the same time, an ordered sequence of single values is established on the internal decoding bus of the BDC bits, starting from the first bit to the IK-th bit (for IK≤K) and zero values from the (IK+1)-th bit to the most significant K-th bit (unitary positional row 00…011…1). Further, the values of the bits from the internal bus BDC arrive at the second inputs of the corresponding elements of the same name AND of the first group 9 ₁ , 9 ₂ , ..., 9 _k and the second group 10 ₁ , 10 ₂ , ..., 10 _k . In this case, with single values of bits in the first group of elements AND 9 ₁ , 9 ₂ , ..., 9 _k , IK bits of the input data sequence ID from the outputs of register RD 6 are transmitted to the internal bus of the first comparison operand VA, and in the second group of elements AND 10 ₁ , 10 ₂ , ..., 10 _k to the internal bus of the second comparison operand BB are transferred IK bits of a given template IS. At the same time, zero values are formed on the buses VA and BB from the (IK+1)-th digit to the most significant K-th digit.

Next, the comparator COMP 11 compares the codes from the internal tires of the first VA and the second BB operands, and if they match, a single value of the internal equality flag FEQ=1 is generated. Further, with a single value at the output of the loan VO=1 of the second subtractive counter of bits of the STK 4 template, a single value of the internal write flag FW=1 is formed at the output of the AND 5 element, according to which the number of the most significant bit of the identified group is recorded from the input data sequence ID corresponding to given template IS, from the outputs of the first bit counter STB 2 to the output buffer OB 3 and increase the counter of the number of detected patterns CTS 12.

Since in the proposed device detection is performed for overlapping patterns, the following clock signals IC in the data register RD 6 during the shift writes one next bit of the input data sequence ID and then the comparison with the pattern IS on the comparator COMP 11 is again carried out and the formation of unity or zero values internal equality flag FEQ and internal write flag FW.

The proposed device works as follows.

In FIG. 2 and FIG. 3 shows the timing diagrams of the operation of the device for searching for groups in the input N=12 bit binary number corresponding to K=4 bit templates IS and the code m=]log ₂ (4+1)[=3 for the bit depth of the template IK. In FIG. 2, the given template contains IK=3 (011) bits and bit values IS=0101. In FIG. 3, the given pattern contains IK=4 (100) bits and bit values IS=0101.

Before starting work, the corresponding preset values for the templates are set on the group of external inputs of the IS template, containing K=4 bits, and on the group of external inputs for setting the capacity of the input template IS, containing m bits, which are stored on external inputs during the entire time of operation of the device - tasks input N=12 bit binary number.

The operation of the device for each input sequence starts after a single signal START=1. At the same time, on the edge of the clock signal IC (cycle 2 in Fig. 2-3), the RS-trigger 1 start-stop TSS=1 is set to a single state, the first bit counter STB 2 and the third counter of the number of templates CTS 12 are set to zero, the the initial zero address in the output buffer OB 3 and the bit width IK of the IS template (in Fig. 2 IK=3 (011), in Fig. 3 IK=4 (100)) is written to the subtracting second counter of bits of the STK 4 template, at the output of the borrow VO which is set to zero value VO(STK)=0.

At the same time, the code IK=011 (Fig. 2) of the current bit depth of the given template IS is transmitted to the inputs of the decoder DC 7. At the outputs of the decoder 7, unitary codes "1 from K=4" are formed, which are transmitted to the corresponding second inputs of the group 8 ₁ , 8 ₂ , ..., 8 _(K-1) of (K-1) OR elements and then the generated code is transmitted to the internal bus for decoding the BDC bits. For the code IK=011 on the BDC bus, the value of the unitary positional series BDC=0111 will be set, according to which, on the next cycles, only three least significant bits are allowed to be transferred to the internal bus of the first operand for comparing VA from the outputs of register RD 6 and to the internal bus of the second operand for comparing BB with external inputs of the given IS template. In this case, the code BB=0101 is set on the bus of the second comparison operand BB.

A single value from the output of the RS-trigger 1 start-stop TSS=1 is fed to the inputs for enabling the operation of the CE of the first counter of the STB 2 bits and the data register RD 6, in which further, at the next cycles, the bits are counted in the first counter of the STB 2 bits and the input data is received ID to the input data shift register RD 6.

In cycle 3, a single value ID=1 from the data input, specified in cycle 2, is written to the input data shift register RD 6 and the code RD=0001 is set at the outputs, which is then transmitted to the internal bus of the first comparison operand BA=0001, compared with the code on the internal bus of the second operand BB and the zero value of the internal equality flag FEQ=0 is set at the output of the comparator COMP 11. At the same time, the value of the first 2 counter of bits STV=1 is increased by one and the value of the counter 4 bits of the STK=2 template is reduced by one, while maintaining zero value at the output of the loan VO(STK)=0. Also in cycle 3, the next second bit is set to zero at the data input ID=0.

In cycle 4, the elements of the device work similarly and the following codes are set: the first 2 counter bits STV=2, the second counter of bits of the STC=1 template, the internal bus of the first comparison operand BA=0010, the internal equality flag FEQ=0 and at the output of the loan VO (STC )=0. Also in cycle 4, a single value of the next third bit is set at the data input ID=1.

In cycle 5, the elements of the device work similarly and the following codes are set: the first 2 counter bits STV=3, the second counter of bits of the STK=0 template, the internal bus of the first comparison operand VA=0101. In this case, since the value of the counter of bits of the STK template = 0, then a single value is set at the output of the loan VO(STK) = 1, which is transmitted to the inverse input CE of enabling the operation of the counter of bits of the STK template and prohibits counting on the following cycles. In addition, since the values of the code of the first comparison operand BA=0101 and the second operand BB=0101 are the same, i.e. the first group in the input sequence corresponding to the given template IS=0101 is detected, then a single value of the internal equality flag FEQ=1 is generated at the output of the comparator COMP 11. Further, with a single value at the output of the loan VO=1 of the second counter of bits of the STK 4 template, a single value is formed internal write flag FW=1 at the output of element AND 5, according to which in cycle 6 the operation of the output buffer OB 3 is allowed, into which the code OB(0)=3 is written at the zero address from the output of the counter bit STV=3, which corresponds to the number of the third bit input sequence, as well as allowing the account (increase by one) in the third counter 12 of the number of patterns CTS=1.

In cycles 5, 6 and 7, the next three bits of the input sequence are fed to the data input ID=101, which also matches the given pattern IS=0101. Therefore, in cycle 8, single values of the internal equality flag FEQ=1 are formed at the output of comparator COMP 11 and the internal write flag FW=1 at the output of element AND 5, according to which, in cycle 9, the work of the output buffer OB 3 is allowed, into which the code is written at the first address OB(1)=6 from the output of the counter bit STV=6, which corresponds to the number of the sixth bit of the input sequence (the most significant bit of the second identified group), and is also allowed to count in the third counter 12 of the number of templates CTS=2.

In cycles 8 and 9, the next two bits (the seventh and eighth bits) of the input sequence are fed to the data input ID=01. Since groups of bits corresponding to a given pattern with overlapping bits from neighboring groups are detected in the device, then with a single value of the sixth bit, a three-bit group code 101 is formed in the three least significant bits of the data register RD 6 corresponding to the given pattern IS=101. Therefore, in cycle 10, single values of the internal equality flag FEQ=1 are formed at the output of comparator COMP 11 and the internal write flag FW=1 at the output of element AND 5, which is used in cycle 11 to write to the second address of the output buffer OB(2)=8 and increasing the third counter 12 of the number of patterns CTS=3.

Groups are searched in a similar way on cycles 10-12, on cycle 13 the formation of single values of the internal equality flag FEQ=1 and the internal write flag FW=1, and then on cycle 14, writing to the third address of the output buffer OB(3)=11, corresponding to the highest eleventh bit for the fourth detected group, and increasing the third counter 12 of the number of patterns CTS=4.

Thus, for the input N=12 bit binary number shown in FIG. 2, four groups were identified corresponding to a given three-bit IK=3 template IS=101, for which the numbers (3, 6, 8, 11) of the most significant bits of the identified groups in input sequence and on the group of external outputs of the number of templates QS set the code from the output of the third counter 12 of the number of templates CTS=4.

For the sequence of input data ID shown in FIG. 3, groups are searched for IK=100 bits of the given template IS=0101. At the same time, in cycle 2, the code STK=4 is written to the counter 4 bits of the STK template, for which the unit value of the loan output is set in cycle 6 VO(STK)=1. At the same time, for the code IK=100 on the BDC bus, the value of the unitary positional series BDC=1111 will be set, according to which, on the next cycles, it is allowed to transfer four least significant bits to the internal bus of the first operand for comparing VA from the outputs of register RD 6 and to the internal bus of the second operand for comparing BB with external inputs of the given IS template. In this case, the code BB=0101 is set on the bus of the second comparison operand BB.

The first single value of the internal equality flag FEQ=1 at the output of the comparator COMP 11 is formed at cycle 5, since after the transfer of the first three bits of the input sequence on the bus of the first operand of comparison BA from the outputs of the register RD 6, the code BA=0101 is set corresponding to the bits of the specified template IS= 0101. But at the same time, at the output of the loan VO of the subtracting second counter of bits of the STK template 4, a zero value of VO(STK)=0 is set. Therefore, a zero value of the internal write flag FW=0 is generated at the output of the element And 5 and it is forbidden to write to the output buffer OB 12 and count the groups in the third counter 12 of the number of CTS templates.

In cycles 5 and 6, data input ID=01 receives the values of the fourth (0) and fifth (1) bits for which, taking into account the values of the previous second (0) and third bits (1), a four-bit group code is formed on the bus of the first comparison operand BA= 0101 from the outputs of the register RD 6 corresponding to the given template IS=0101. In this case, single values of the internal equality flag FEQ=1 and the internal write flag FW=1 are formed, since at the output of the loan VO of the subtractive counter of bits of the STK template 4, a single value VO(STK)=1 is set. Therefore, in cycle 8, the code is written to the zero address of the output buffer of the code OB(0)=5 from the output of the second counter of bits STV=5, which corresponds to the number of the most significant fifth bit of the identified group of the input sequence, and the counting in the third counter 12 of the number of CTS templates is also allowed =1.

The next group, corresponding to the given pattern IS=0101, was detected for 7-10 bits of the input sequence, for which a single value of the internal write flag FW=1 is formed in cycle 12 and then in cycle 13 the code is written to the first address of the output buffer of the code OB (1 )=10 from the output of the counter bit CTS=10, which corresponds to the number of the tenth bit of the input sequence, and allowed to count in the third counter 12 of the number of patterns CTS=2.

When searching for the next group, the input data takes into account the overlap of bits from neighboring groups - the zero value of the ninth bit and the unit value of the tenth bit, which arrived at the input ID=01 in cycles 10 and 11. Therefore, after the next code ID=01 arrives in cycles 12 and 13, in cycle 14, a single value of the internal write flag FW=1 is formed, and then in cycle 15, the code is written to the second address of the output buffer of the code OB(2)=12 from the output of the bit counter STB=12, which corresponds to the number of the twelfth bit (most significant bit third group) of the input sequence, and allowed to count in the third counter 12 of the number of templates CTS=3.

At the same time, in cycle 14, a single signal STOP=1 is received, according to which the RS-trigger 1 start-stop TSS=0 switches to the zero state.

Processing of the next input N bit binary number begins after a single signal START=1.

Reading the results to a group of external data outputs QB from the output buffer VO 3 is controlled by the external control bus EO. When implementing the output buffer VO 3 in the form of a dual-port FIFO memory, the exchange can be performed in the process of group detection, taking into account the values of the flags "Buffer empty" FZ and "Buffer full" FF. The value of the code for the group of external outputs of the number of templates QS is transmitted from the outputs of the third counter of the number of templates CTS 12.

The proposed device can be used for hardware implementation of statistical tests developed by the Information Technology Laboratory of the National Institute of Standards and Technology (NIST, USA), the purpose of which is to determine the measure of randomness of binary sequences generated by random number generators. In particular, the proposed device implements a match test for overlapping given patterns of dimension K bits with groups of input data also dimensioned to K bits and counts the number of predetermined patterns found in the original sequence. In this case, regardless of the match or non-match to the template, the analyzed neighboring groups from the input data are shifted one bit forward. The goal is to identify random or pseudo-random number generators that generate too often given non-periodic patterns.

When processing the results of physical experiments, the proposed device provides the identification of non-periodic events (templates - a given group of sequences of single bits (events duration) and zero bits (intervals between them)) and event coordinates.

The above information allows us to conclude that the proposed device solves the problem and corresponds to the claimed technical result - the implementation of the possibility of setting the values of the templates and their capacity, determining the number of identified templates and their location in the input data sequence.

Claims (12)

The device for detecting overlapping bit patterns in a binary sequence contains an external data input ID, a group of external inputs of the template IS containing K bits, a group of external inputs IK for setting the bit depth of the input template IS containing m bits (where m=]log ₂ (K+1) [greater integer), QB external data output group, QS pattern number external output group, and also contains the RS trigger start-stop TSS 1, the first bit counter STB 2, the output buffer OB 3, the second subtracting counter of bits of the STK 4 template, the AND element 5, the input data shift register RD 6, the decoder DC 7, a group of (K -1) OR elements 8 ₁ , 8 ₂ , ..., 8 _(k-1) , the first group of K elements AND 9 ₁ , 9 ₂ , ..., 9 _k , the second group of K elements AND 10 ₁ , 10 ₂ , ... , 10 _k , comparator COMP 11 and the third counter of the number of patterns CTS 12, as well as external inputs of the clock signal IC, device start START, device stop STOP and internal bit decoding bus BDC, bus of the first compare operand VA, bus of the second compare operand BB, internal equality flag FEQ and internal write flag FW, external exchange control bus EO , external "Buffer full" flag FF and "Buffer empty" flag FZ, moreover, the external clock input of the IC device is connected to the synchronization inputs C of the RS start-stop flip-flop TSS 1, the first bit counter CTB 2, the output buffer OB 3, the second subtracting counter of bits of the pattern STK 4, the input data shift register RD 6 and the third counter of the number of patterns CTS 12, the external start input of the START device is connected to the input S of the synchronous setting to a single state of the RS start-stop trigger TSS 1, to the input L of the permission to write the second subtracting counter of the bits of the STK 4 template, to the inputs R of the synchronous setting to the zero state of the first counter bit STV 2, output buffer OB 3, input data shift register RD 6 and third pattern counter CTS 12, the external stop input of the STOP device is connected to the input R of the synchronous set to zero state of the RS start-stop trigger TSS 1, moreover, the direct output of the RS-trigger start-stop TSS 1 is connected to the inputs CE to enable the operation of the first bit counter CTB 2 and the input data shift register RD 6, the external data input ID is connected to the input SI of the serial input of the shift register of the input data RD 6, the group K of the outputs of which is connected to the first inputs of the corresponding elements of the same name of the first group of K elements AND 9 ₁ , 9 ₂ , ..., 9 _k , the outputs of which are the corresponding ones of the same name bits of the internal bus of the first comparison operand VA, which is connected to the first group of inputs of the comparator COMP 11, K bits of the group of external inputs of the IS template are connected to the first inputs of the corresponding elements of the same name of the second group of K elements And 10 ₁ , 10 ₂ , ..., 10 _k , the outputs of which are the corresponding identical bits of the internal bus of the second comparison operand BB, which is connected to the second group of inputs comparator COMP 11, the output of which is an internal equality flag FEQ and is connected to the second input of the AND element 5, moreover, the group of external inputs IK of setting the bit depth of the input template IS is connected to the corresponding group of D-inputs of the second counter of bits of the STK 4 template and the address inputs of the decoder DC 7, in which the outputs, from the first output to the (K-1)-th output, are connected to the first inputs of the corresponding elements of the same name of the group of (K-1) elements OR 8 ₁ , 8 ₂ , ..., 8 _(k-1) , the outputs of which are the corresponding digits of the same name, from the first digit to the (K-1) th digit, the internal bus decoding of BDC bits, in which the K-th bit is connected to the K-th output of the decoder DC 7, and K bits of the internal bus for decoding BDC bits are connected to the second inputs of the corresponding elements of the same name of the first group from K elements AND 9 ₁ , 9 ₂ , ..., 9 _k and the second group of K elements AND 10 ₁ , 10 ₂ , ..., 10 _k , as well as the outputs of the elements of the group 8 ₁ , 8 ₂ , ..., 8 _(k-1) from (K-1) elements OR, starting from the output (K-1)-th element 8 _(k-1) to the second element 8 ₂ connected to the second inputs of the corresponding p previous elements OR of the group 8 ₁ , 8 ₂ , …, 8 _(k-1) , starting from the (K-2)-th element 8 _(k-2) to the first element 8 ₁ , and the second input (K-1)- th element 8 _(k-1) is connected to the K-th output of the decoder DC 7, in addition, the direct output of the loan VO of the subtractive counter of bits of the STK 4 template is connected to the inverse input of the operation enable CE of the bit counter of the STK 4 template and to the first input of the AND element 5, the output of which is the internal recording flag FW and is connected to the inputs of the CE of the operation of the output buffer OB 3 and the third counter of the number of templates CTS 12, moreover, the group of outputs of the first counter bit CTB 2 is connected to the group of information D-inputs of the output buffer OB 3, which is also connected to the external bus EO exchange control, and the corresponding outputs of the output buffer OB 3 are a group of external data outputs QB and external flags "Buffer full" FF and "Buffer empty" FZ, and the CTS pattern number counter output group 12 is the QS pattern number external output group.

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