RU2798197C1 - Parallel-serial structure device for detecting non-overlapping bit patterns - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention can be used to build functional units for analysing the properties of generators of pseudo-random sequences of binary numbers, filtering events, processing signals, images and results of physical experiments. The device comprises an external m-bit data input ID and an m-bit input of a given template IG, a group of external data outputs QB and the number of detected templates QK, the first RS start-stop trigger TSS, the second delay D-trigger TR2, the group counter CTG, the output buffer OB, the first R1 data register, the second R2 data register, a group of m comparators, a group of m AND elements, a group of (m-1) OR elements, a unit counter, an AND element, a NOR element, a CTC pattern counter, and a mask register RM.

EFFECT: identifying non-overlapping patterns containing specified groups (sequence) of single and zero bits and their location in the input data groups.

1 cl, 3 dwg

Description

FIELD OF TECHNOLOGY

The invention relates to the field of computer technology, in particular to data processing devices, and can be used to build functional units for analyzing the properties of generators of pseudo-random sequences of binary numbers, filtering events, processing signals, images and results of physical experiments.

PRIOR ART

A serial type device for detecting groups of zero and one bits and determining their number is known (RU No. 2680759 C1, IPC G06F 7/74, declared 16.02.2018, publ. 26.02.2019, Bull. No. 6) in which for input data sequences with a dimension N inputs to the external data input DI, binary codes are formed at the corresponding external outputs of the device groups, corresponding to the number of groups QG, the number of zero bits QZ, the number of single bits QU, the difference between the number of single and zero bits QZU, the number of bits by groups QO from the output buffer OB 11, while in even addresses, starting from the zero address, the number of zero bits in groups is indicated, and in odd addresses, starting from the first address, the number of single bits in groups is indicated, and the ready flag FE is formed, the flag "more than zeros units" F01, "Buffer full" flag FF and "Buffer empty" flag FZ.

The disadvantages of this device is the sequential one-bit input of input data and the definition of groups of zero and one bits of arbitrary dimension, rather than given patterns from a set of one and zero bits.

A parallel-serial structure device for detecting groups of zero and one bits and determining their number is known (RU No. 2711054 C1, IPC G06F 7/74, declared 08/06/2019, publ. 01/14/2020, Bull. No. 2), containing M bits D1 , …, DM of an input data set of N bit binary number, consisting of L sets of M bits in the set, where N=L*M, N external outputs of groups of bits QG1, …, QGN, group of external outputs of the total number of groups QK, external left (first) bit output QLB, external output group of the number of 1 bits QU, external output group of the number of zero bits QZ, group detection module FK 1, first enable TEB trigger 2, left (first) bit TLB trigger 3, XOR element » 4, AND element with one inverse input 5, the first group shift module SF_1 6, the first adder SMG bits in a group 7, the subtractor SB 8, the second group shift module SF_2 9, the second adder SM_K of the number of groups 10, the third adder SM_U of the number of one bits 11, trigger TPO start-stop 12, group bit register RG_G 13, group number register RG_K 14, number of ones bit register RG_U 15, third group shift module SF_3 16, fourth adder SM_N complement 17, fifth adder SM_Z number of zero bits 18, second receive enable flip-flop TEQ 19, first output buffer register of group codes 20, second output buffer register of total number of groups 21, output trigger of the left (first) bit of input data 22, third output buffer register of the number of ones bits 23, fourth output buffer register of the number of zero bits 24, external inputs C clock signals 25, R synchronous set to zero state 26, start operation START, stop STOP and internal decrement flag FD.

The disadvantage of this device is the identification of individual groups of zero and one bits of arbitrary dimension, and not given patterns from the totality of one and zero bits.

The closest device for the same purpose to the claimed invention in terms of the totality of features is, adopted as a prototype, a device for detecting groups of bits (RU No. No. 28), containing an external m-bit data input ID, an external m-bit input of a given pattern IG, a group of external data outputs QB, the first RS start-stop trigger TSS 1, the second delay D-trigger TR2 2, the CTG group counter 3, output buffer OB 4, first R1 data register 5, second R2 data register 6, group of m comparators 7 ₁ , 7 ₂ , …, 7 _m , group of (m-1) AND elements 8 ₂ , 8 ₃ , …, 8 _m , OR element 9 and AND element 10, as well as external inputs for asynchronous setting to zero state CLR, device start START, device stop STOP and clock C, internal 2m-bit data bus BD, internal m-bit data bus IOB buffer, internal match flag FE, external exchange control bus EO, external buffer full flag FF and buffer empty flag FZ.

The disadvantage of this device is the detection of overlapping patterns containing a given group (sequence) of single and zero bits and their location in the input data.

OBJECT OF THE INVENTION

The objective of the invention is the development of group structure hardware for studying the properties of generators of pseudo-random sequences of binary numbers, as well as for processing the results of physical experiments and images.

When analyzing generators of pseudo-random sequences of binary numbers, the device is designed to identify given non-overlapping patterns from a set of groups (rows) of zero and one bits.

When processing the results of physical experiments, the device is designed to identify non-periodic events (regions) - given durations of events and intervals between them, as well as event coordinates.

The technical result of the invention is the expansion of the arsenal of tools for the same purpose, in terms of the possibility of identifying non-overlapping patterns containing specified groups (sequence) of single and zero bits and their location in groups of input data.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved in that the parallel-serial structure device for detecting non-overlapping bit patterns contains an external m-bit data input ID, an external m-bit input of a given template IG, a group of external data outputs QB, a group of external outputs of the number of detected patterns QK, first RS start-stop flip-flop TSS 1, second D-flip-flop TR2 delay 2, group counter CTG 3, output buffer OB 4, first R1 data register 5, second R2 data register 6, group of m comparators 7 ₁ , 7 ₂ , …,7 _m , a group of m elements AND 8 ₁ , 8 ₂ , …, 8 _m , a group of (m-1) elements OR 9 ₁ , 9 ₂ , …, 9 _(m-1) , unit count block 10, AND element 11, OR NOT element 12, STK pattern counter 13 and mask register RM 14,

and also introduced external inputs of asynchronous setting to the zero state CLR, start device START, stop device STOP and clock input C, internal 2m-bit data bus BD, internal bus v of the bit binary code of the beginning of the pattern in the group BB (where v =] log2 m [(greater integer)), internal m-bit line code of the single position row BC, internal m-bit bus mask BM, internal match flag FE, external exchange control bus EO, external flag "Buffer full" FF and flag "Buffer empty" FZ,

moreover, the external input of the asynchronous zeroing CLR is connected to the corresponding inputs of the asynchronous zeroing CLR of the first RS start-stop flip-flop TSS 1 and the second delay D-latch TR2,

The external clock input of device C is connected to the clock inputs C of the first RS start-stop flip-flop TSS 1, the second D-flip-flop TR2 of the delay 2, the CTG group counter 3, the output buffer OB 4, the first R1 data register 5, the second R2 data register 6, template counter STK 13 and mask register RM 14,

the external start input of the START device is connected to the input S of the synchronous setting to a single state of the first RS start-stop trigger TSS 1 and to the inputs R of the synchronous setting to the zero state of the CTG counter of groups 3, the output buffer OB 4, the first R1 data register 5, the second R2 data register 6, pattern counter STK 13 and mask register RM 14,

the external stop input of the STOP device is connected to the input R of the synchronous set to zero state of the first RS start-stop trigger TSS 1,

moreover, the direct output of the first RS-trigger start-stop TSS 1 is connected to the D-input of the second trigger TR2 delay 2, with the inputs CE of enabling the operation of the first R1 data register 5, the second R2 data register 6, the mask register RM 14 and the third inputs of the first (m -1) elements AND groups 8 ₁ , 8 ₂ , …, 8 _(m-1) ,

the output of the second D-flip-flop TR2 of the delay is connected to the input CE of enabling the operation of the CTG counter of groups 3 and the first input of the element AND 11, the output of which is connected to the input of the CE of the permission to write to the output buffer OB 4 and the permission of the account of the CE of the counter of the CTC templates 13, the outputs of which are a group external outputs of the number of detected QK templates,

moreover, the external m-bit input of the given template IG is connected to the first groups of inputs of all m comparators of the group 7 ₁ , 7 ₂ , …, 7 _m , the outputs of which are connected to the second inputs of the corresponding elements of the same name AND of the group 8 ₁ , 8 ₂ , …, 8 _m ,

the external m-bit data input ID is connected to the group of information D-inputs of the first R1 data register 5, the outputs of which are the corresponding bits, starting from the first to the m-th bit, of the internal data bus BD, and is also connected to the group of information D-inputs of the second R2 data register 6, the outputs of which are the corresponding bits from the (m+1)th to the 2mth bit, of the internal data bus BD,

moreover, the bits of the internal data bus BD in groups of m bits, each of which begins with the (i+1)-th bit (i=l,…, m), are connected to the second groups of inputs of the corresponding i-th comparators of the group 7 ₁ , 7 ₂ , …,7 _m,

the outputs of the first (m-1) elements AND of the group 8 ₁ , 8 ₂ , ..., 8 _(m-1) are connected to the first inputs of the same elements OR of the group 9 ₁ , 9 ₂ , ..., 9 _(m-1) , and the output of the last m-th element AND 8 _m is connected to the second input of the last element 9 _(m-1) , and is also the m-th bit of the internal bus code of the unit positional row VS, in which the bits, starting from the first to (m-1)-th discharge, are the outputs of the same name (m-1) elements OR group 9 ₁ , 9 ₂ , ..., 9 _(m-1) ,

in addition, the second inputs of the first (m-2) elements of the OR group 9 ₁ , 9 ₂ , …, 9 _(m-2) , starting from the first to the (m-2)-th elements, are connected to the outputs of the corresponding subsequent (m-2 ) OR elements of the group 9 ₂ , 9 ₃ , …, 9 _(m-1) , starting from the second to the (m-1)-th element,

moreover, all m bits of the internal bus code of a single positional row BC are connected to the corresponding inputs of the units counting block 10, to the group of information D-inputs of the mask register RM 14 and to the inputs of the OR-NOT element 12, the direct output of which is an internal match flag FE and is connected to the second input of the AND element 11, and the inverse output of the OR NOT element 12 is connected to the input S of the synchronous setting to the single state of the mask register RM 14,

in addition, the outputs of the mask register RM 14 are the corresponding bits of the same name of the internal m bit bus of the VM mask, which are connected to the first inputs of the same m elements And groups 8 ₁ , 8 ₂ , ..., 8 _m ,

moreover, the outputs of the units counting block 10 are the corresponding bits of the internal bus of the binary code of the beginning of the template in the group BB, which is connected to the second group of information D-inputs of the output buffer OB 4, in which the first group of information D-inputs is connected to the outputs of the counter CTG groups 3,

in addition, the output buffer OB 4 is also connected to the external exchange control bus EO, and the corresponding outputs of the output buffer OB 4 are a group of external data outputs QB and external flags "Buffer full" FF and "Buffer empty" FZ.

BRIEF DESCRIPTION OF THE DRAWINGS

In FIG. 1 shows a diagram of the proposed device. In FIG. 2 shows the template search scheme. In FIG. 3 shows the timing diagram of the device.

In FIG. 1-3 and the following notation is used in the text:

BB - internal bus v bit binary code of the beginning of the pattern in the group,

where v=]log2 m[(greater integer),

ВС - internal m-bit bus code of a single positional row,

BD - internal 2m bit data bus,

VM - internal m-bit mask bus,

BUF - buffer with FIFO service discipline,

C - clock input,

CE - work enable input,

CLR - input of asynchronous setting to the zero state,

CTG - group counter,

CTK - pattern counter,

D - information inputs,

FF - external flag "Buffer full",

FZ - external flag "Buffer is empty",

FE - internal match flag,

G1, G2, …, GL - input groups,

ID - external m bit data input,

IG - external m bit input of a given pattern,

L - number of input groups L=N/m,

m - bit depth of input data,

N - dimension (length) of the input data sequence,

OB - output buffer,

QB - group of external data outputs,

QK - a group of external outputs of the number of detected patterns,

R - input of synchronous setting to zero state,

RG - register,

RM - mask register,

S - input of synchronous setting to a single state,

START - external start input,

STOP - external stop input,

T - trigger,

TR2 - delay trigger,

TSS - start-stop trigger,

1 - the first RS-trigger start-stop TSS,

2 - second D-trigger delay TR2,

3 - CTG group counter,

4 - OB output buffer,

5 - first data register R1,

6 - second data register R2,

7 ₁ , 7 ₂ , …,7 _m - group of m comparators (COMP),

8 ₁ , 8 ₂ , …, 8 _m - group of m elements AND (AND),

9 ₁ , 9 ₂ , …, 9 _(m-1) - a group of (m-1) elements OR (OR),

10 - unit count block,

11 - element AND (AND),

12 - element OR-NOT (NOR),

13 - STK template counter,

14 - RM mask register.

The proposed device contains an external contains an external m-bit data input ID, an external m-bit input of a given pattern IG, a group of external data outputs QB, a group of external outputs of the number of detected patterns QK, the first RS start-stop trigger TSS 1, the second delay D-trigger TR2 2, counter CTG groups 3, output buffer OB 4, first R1 data register 5, second R2 data register 6, group of m comparators, 7 ₁ , 7 ₂ , …,7 _m , group of m elements AND 8 ₁ , 8 ₂ , …, 8 _m , a group of (m-1) OR elements 9 ₁ , 9 ₂ , …, 9 _(m-1) , unit count block 10, AND element 11, OR-NOT element 12, STK pattern counter 13 and mask register RM 14.

The proposed device also includes external inputs for asynchronous setting to the zero state CLR, device start START, device stop STOP and clock input C, an internal 2m-bit data bus BD, an internal bus v of the bit binary code of the beginning of the template in the BB group (where v =] log2 m[(greater integer)), internal m-bit line code of the single position row BC, internal m-bit bus mask BM, internal match flag FE, external exchange control bus EO, external flag "Buffer full" FF and flag "Buffer empty" FZ.

The external asynchronous zeroing input CLR is connected to the corresponding asynchronous zeroing inputs CLR of the first RS start-stop flip-flop TSS 1 and the second delay D-latch TR2.

The external clock input of device C is connected to the clock inputs C of the first RS start-stop flip-flop TSS 1, the second delay D-flip-flop TR2 2, the CTG group counter 3, the output buffer OB 4, the first R1 data register 5, the second R2 data register 6, pattern counter STK 13 and mask register RM 14.

The external start input of the START device is connected to the input S of the synchronous setting to a single state of the first RS start-stop trigger TSS 1 and to the inputs R of the synchronous setting to the zero state of the CTG counter of groups 3, the output buffer OB 4, the first R1 data register 5, the second R2 data register 6, pattern counter STK 13 and mask register RM 14.

The external STOP input of the device is connected to the R input of the synchronous set to zero state of the first RS start-stop flip-flop TSS 1.

The first RS-trigger start-stop TSS 1 is designed to highlight the cycle of operation of the proposed device, between the START and STOP signals, for the input data sequence DI of dimension N, containing L groups of dimension m. Moreover, the direct output of the first RS-trigger start-stop TSS 1 is connected with the D-input of the second trigger TR2 of delay 2, with the inputs CE of enabling the operation of the first R1 data register 5, the second R2 data register 6, the mask register RM 14 and the third inputs of the first (m-1) elements of the AND group 8 ₁ , 8 ₂ , ... .8 _(m-1)

The output of the second D-flip-flop TR2 of the delay is connected to the input CE of enabling the operation of the CTG counter of groups 3 and the first input of the element AND 11, the output of which is connected to the input of the CE of the permission to write to the output buffer OB 4 and the permission of the account of the CE of the counter of the CTC templates 13, the outputs of which are a group external outputs the number of identified QK templates.

Counter CTG groups 3 is designed to count and store the number of the current input data group. The second D-flip-flop TR2 of delay 2 delays by one cycle the resolution of the count of current groups in the CTG counter of groups 3 and writing to the output buffer OB 4.

The external m bit input of the given template IG is connected to the first groups of inputs of all m comparators of the group 7 ₁ , 7 ₂ , …, 7 _m , the outputs of which are connected to the second inputs of the corresponding elements of the same name AND of the group 8 ₁ , 8 ₂ , …, 8 _m .

The external m-bit data input ID is connected to the group of information D-inputs of the first R1 data register 5, the outputs of which are the corresponding bits, starting from the first to the m-th bit, of the internal data bus BD, and is also connected to the group of information D-inputs of the second R2 data register 6, the outputs of which are the corresponding bits, starting from the (m+1)th to the 2mth bit, of the internal data bus BD.

The bits of the internal data bus BD in groups of m bits, each of which starts with the (i+1)-th bit (i=1, ..., m), are connected to the second groups of inputs of the corresponding i-th comparators of the group 7 ₁ , 7 ₂ , …,7 _m .

The outputs of the first (m-1) elements AND of the group 8 ₁ , 8 ₂ , …, 8 _(m-1) are connected to the first inputs of the elements of the same name OR of the group 9 ₁ , 9 ₂ , …, 9 _(m-1) , and the output of the last m-th element AND 8 _m is connected to the second input of the last element 9 _(m-1) , and is also the m-th bit of the internal bus code of the unit positional row VS, in which the bits, starting from the first to (m-1)-th discharge, are the outputs of the same (m-1) elements of the OR group 9 ₁ , 9 ₂ , ..., 9 _(m-1 ).

In addition, the second inputs of the first (v-2) elements of the OR group 9 ₁ , 9 ₂ , ..., 9 _(m-2) , starting from the first to the (m-2)-th elements, are connected to the outputs of the corresponding subsequent (m-2 ) elements of the OR group 9 ₂ , 9 ₃ , …, 9 _(m-1) , starting from the second to the (m-1)-th element.

Moreover, all m bits of the internal bus code of a single positional row BC are connected to the corresponding inputs of the units counting block 10, to the group of information D-inputs of the mask register RM 14 and to the inputs of the OR-NOT element 12, the direct output of which is an internal match flag FE and is connected to the second input of the AND element 11. The inverse output of the OR NOT element 12 is connected to the input S of the synchronous setting to the single state of the mask register RM 14.

In addition, the outputs of the mask register RM 14 are the corresponding same-name bits of the internal m-bit bus of the VM mask, which are connected to the first inputs of the same-name m elements And groups 8 ₁ , 8 ₂ , ..., 8 _m .

The outputs of the units counting block 10 are the corresponding bits of the internal bus of the binary code of the beginning of the template in the group BB, which is connected to the second group of information D-inputs of the output buffer OB 4, in which the first group of information D-inputs is connected to the outputs of the counter CTG groups 3.

The output buffer OB 4 is designed to accumulate the numbers of input groups and the location code of the bits of the beginning of the identified groups corresponding to the template code IG. The output buffer OB 4 is also connected to the external bus exchange control EO, and the corresponding outputs of the output buffer OB 4 are a group of external data outputs QB and external flags "Buffer full" FF and "Buffer empty" FZ.

DETAILED DESCRIPTION OF THE INVENTION

The principle of operation of the proposed device is as follows.

The proposed device allows you to detect m-bit groups in the input N-bit binary number corresponding to the m-bit given pattern of groups IG, which contains a given sequence of one and zero bits, to form and write to the output buffer OB 4 the numbers of the input groups and the binary code of the bit of the beginning identified groups corresponding to the template code. In this case, the digits of the identified adjacent input groups that match the given template IG cannot overlap.

The input N bit unsigned binary number is divided into L=N/m groups of m bits in each group. Groups of input data G1, G2, ..., GL sequentially arrive at the inputs of the device. In this case, m binary digits of each of the L groups are fed in parallel to the corresponding data inputs ID. During operation of the device, the specified m-bit sequence of one and zero bits must be set at the external inputs of the IG template.

The operation of the device starts with a single signal START=1 and ends with a single stop signal STOP=l, which arrives on the next cycle after the code of the last L-th group. Groups of input data come in every clock cycle.

Search (identification, detection, analysis) is carried out for each two consecutive input groups with a total capacity of 2 tons. In this case, each input group G1, G2, ..., GL first enters the first R1 data register 5, and then on the next cycle is overwritten in the second R2 data register 6 with simultaneous loading of the next adjacent group into the first R1 data register 5. The second TR2 flip-flop 2 delays the start of the analysis by one clock cycle to load the second group and hold by one cycle to be able to write the result to the output buffer OB 4 after the stop signal STOP= 1.

At each cycle for two adjacent groups, a search for a given pattern of IG groups is performed on m comparators from the group 7 ₁ , 7 ₂ , …, 7 _m , the first groups of inputs of which receive the m-bit code of the given pattern IG, and the second groups of inputs the corresponding m-bit codes shifted by one digit from the internal 2m-bit data bus BD, the digits of which are the outputs of the first R1 data register 5 and the second R2 data register 6. Simultaneously, the input groups G1, G2, ..., GL are counted on the counter CTG groups 3.

At the outputs of the group of comparators 7 ₁ , 7 ₂ , …, 7 _m, single values are formed when the corresponding m-bit groups from the internal 2m-bit data bus BD coincide with the code of the specified group pattern IG and an m-bit code for the location of the bits of the beginning of the detected patterns is formed ( overlapping and non-overlapping) in the current input group, the number of which is set in the CTG counter of groups 3.

Further, based on the zero values of the bits of the VM mask bus from the outputs of the mask register RM 14, in the group of elements AND 8 ₁ , 8 ₂ , ..., 8 _m , the identified overlapping patterns are excluded. Further, in the group of OR elements 9 ₁ , 9 ₂ , ..., 9 _(m-1 ) a single value corresponding to the identified groups is transmitted sequentially from the highest digit towards the lower digits along the chain of OR elements and single values are set at the corresponding outputs of the OR elements of group 9 ₁ , 9 ₂ , …, 9 _(m-1 ), which then go to the internal bus of the aircraft. Thus, an ordered sequence of single values (unitary positional series 00…011..1) is established on the internal bus of the aircraft, starting from the first digit, the sum of units of which corresponds to the number of the highest (left) detected template.

Further, the values from the internal bus BC of the code of a single positional series are fed to the inputs of the unit counting block 10, the OR NOT element 12 and the mask register RM 14. group, which is then transmitted to the second group of information D-inputs, simultaneously with the number of the input group from the counter CTG 3, which are transmitted to the first group of information D-inputs of the output buffer OB 4.

If there is at least one single value in the bits on the internal bus BC, at the direct output of the OR-NOT element 12, a single value of the match flag FE=1 is formed, which is transmitted to the AND element 11 and which is then allowed to write to the output buffer OB 4 and count the identified templates in the STK 14 counter.

At the same time, the values from the internal bus BC of the code of a single positional row are written to the mask register RM 14 and then transferred to the internal mask bus VM. In this case, the zero values of the digits exclude the identified overlapping patterns in the group of elements AND 8 ₁ , 8 ₂ , …, 8 _m .

In addition, in the absence of single values on the internal bus BC, a single value is formed at the inverse output of the OR-NOT element 12, which is transmitted to the input S of the synchronous setting of the mask register RM 14, according to which all bits of the mask register RM 14 are set to a single state, according to which on the next cycle, it is allowed to transfer single values of all outputs of the group of m comparators 7 ₁ , 7 ₂ , …, 7 _m in the group of elements AND 8 ₁ , 8 ₂ , …, 8 _m

In addition, in the group of (m-1)-th elements AND 8 ₂ , 8 ₃ , …, 8 _m , the transfer of comparison results from (m-1) comparators 7 ₂ , 7 ₃ , …, 7 _m is prohibited, except for the first comparator 7 ₁ , on the last cycle of operation after the STOP signal. Element AND 11 allows the transfer of the value of the match flag FE to the input CE of the write permission to the output buffer OB 4 and the template count in the counter STK 14.

The proposed device works as follows.

When a signal is applied to the CLR input of the asynchronous setting to zero, the first RS start-stop flip-flop TSS=0 and the second delay D-flip-flop TR2=0 are set.

The clock signals from input C are constantly supplied to the synchronization inputs C of the first RS start-stop flip-flop TSS 1, the second D-flip-flop TR2 of delay 2, the CTG group counter 3, the output buffer OB 4, the first R1 data register 5, the second R2 data register 6 , the STK 13 template counter and the RM 14 mask register, the modes of operation of which are set by the signals at the corresponding control inputs, and are executed on the edges of the clock signals C.

In FIG. 2 shows a search scheme for a given m=4 bit pattern IG=1011 in N=32 bit binary number containing L=8 four-bit groups G1, G2, ..., G8. In FIG. 2 as a result of detection, eight templates were identified, of which two were excluded in the proposed device as overlapping (groups G1-G2 and G5-G6, G6-G7). In this case, the ninth group G9 is not analyzed by the device, since it arrives simultaneously with the STOP signal. In FIG. 3 shows a timing diagram of the operation of the proposed device for the input data shown in FIG. 2.

The device starts working after a single signal START=1 (step 1 in Fig. 3). In this case, synchronously on the edge of the next clock signal C (cycle 2), the first RS-trigger 1 start-stop TSS=1 is set to a single state and the CTG counter of groups 3, the first R1 data register 5, the second R2 data register 6, are set to the zero state, counter templates STK 13 and mask register RM 14 and set the initial zero address in the output buffer OB 4.

A single value from the output of the first RS-trigger 1 start-stop TSS=1 is fed to the information D-input of the second delay trigger TR2 and allows, on the next cycles, to receive groups of input data in the first R1 data register 5 from the external data input ID and write data from the first R1 data register 5 to the second R2 data register. Meanwhile, in FIG. 2 and FIG. The 3 MSBs in the ID groups, in the IG pattern, in the first R1 and second R2 registers, on the COMP comparators and internal buses are shown on the left.

In cycle 2, the code 1011 is set at the input of the IG template, which is then held during device operation, and the code 1011 of the first group G1 also enters the data input ID, which is written in cycle 3 to the first R1 data register 5. Simultaneously, in cycle 3, to single the state is switched by the second delay trigger TR2, which allows the counter CTG of groups 3 to work in the counting mode on the following cycles, on which the code of the number of the input current group is set, and allows the transfer of the value of the match flag FE through the AND element 11 to the input CE of the write permission to the output buffer OB 4. At the same time, in cycle 2, zero values are set at the outputs of all comparators from the group 7 ₁ , 7 ₂ , …, 7 _m , by which zero values are further formed on the internal buses BC, VM and BB, as well as the zero value of the coincidence flag FE=0 .

In cycle 3, the value in counter 3 of groups CTG=1 is incremented. In addition, in cycle 3, since the match flag FE=0 is set to zero, all bits of the mask register RM 14 are set to a single state, which are then transferred to the internal mask bus VM=1111 and enable the operation of the group of elements AND 8 ₂ , 8 ₃ , …, _8m .

At the same time, in cycle 3, code 0110 of the second group G2 enters the ID data input, which is written in cycle 4 to the first R1 data register 5, and at the same time, code 1011 from the outputs of the first R1 data register 5 is written to the second R2 data register 6. At the same time, on the internal The 2m-bit data bus BD is set to 8-bit code 1011 0110.

Then, in groups of m digits, starting from the left most significant digit and shifting the beginning of the groups by one digit towards the least significant digits, the codes enter the second groups of inputs of the corresponding comparators 7 ₁ , 7 ₂ , …, 7 _m , and the first groups of inputs of which receive m -bit code of the given template IG=1011. In this case, single values are formed at the outputs of two comparators 7 ₁ , 7 ₄ and the code COMP=1001 is set, which means a match with the template in two groups (see Fig. 2 and Fig. 3), starting from the senior fourth and junior first digits of the first input group G1. Further, this code 1001, with a single value of the first RS-trigger 1 start-stop TSS=1 and single values on the mask bus BM=1111, is transmitted through a group of elements AND 8 ₁ , 8 ₂ , ..., 8 _m to a group of elements OR 9 ₁ , 9 ₂ , …, 9 _(m-1) and further on the internal bus VS the ordered single positional row ВС=1111 is set, since the single value from the left most significant bit is sequentially transmitted along the chain of the group of elements OR 9 ₁ , 9 ₂ , …, 9 _(m-1) . Next, in the unit count unit 10, the unit positional series BC=1111 is converted into a binary code BB=4 corresponding to the left most significant digit of the identified template. In this case, the identified overlapping pattern with the beginning from the first digit is excluded.

At the same time, a single value of the match flag FE=1 is generated. Further, a single value is set at the output of the element AND 11, since the second delay D-flip-flop TR2=1 is set to a single state, and then writing to the output buffer OB 4 is allowed, into which the code OB (0) = is written in cycle 5 at the zero address 1_4 corresponding to the number of the first group G1 from the group counter 3 CTG=1 and the code of the fourth digit of the location of the beginning of the senior (left) detected pattern in the current first group G1, which comes from the internal bus BB=4. Also in step 5 is the account of the identified patterns on the counter 14 STK=1.

In addition, since all bits of the identified template are located in the first group G1, then on the next cycle, comparisons are allowed to be checked starting from the fourth bit. Therefore, in the mask register RM 14, permission is again set for all bits BM=1111.

At the same time, in cycle 4, code 1100 of the third group G3 enters the ID data input, which is written in cycle 5 to the first R1 data register 5, and at the same time, code 0110 from the outputs of the first R1 data register 5 is written to the second R2 data register 6. Simultaneously, in cycle 5 increments the value in group counter 3 CTG=2. Therefore, the code 0110 1100 is set on the internal 2m-bit data bus BD. In this case, a match with the pattern IG=1011 will be detected only in one group on the second comparator lz and the code COMP=0010 is set. Therefore, further with a single value of the first RS-trigger 1 start-stop TSS=1 and single values on the mask bus BM=1111, through a group of elements AND 8 ₁ , 8 ₂ , …, 8 _m , a group of elements OR 9 ₁ , 9 ₂ , ..., 9 _(m-1) and further on the internal bus BC the ordered single position row BC=0011 is set. Next, in the unit counting unit 10, the unit positional series BC=0011 is converted into a binary code BB=2 corresponding to the second digit of the identified pattern.

Further, with a single value of the match flag FE=1 in cycle 6, the code OB(1)=2_2 is written to the output buffer OB 4 at the first address, corresponding to the input second group G2 CTG=2 and the second bit of the beginning of the group corresponding to the given template IG=1011, which comes from the internal bus BB=2. Also in step 6 is the account of the identified patterns on the counter 14 STK=2.

In addition, since two digits of the detected template are located in the second group G2, and two digits in the third group G3, then on the next cycle, comparisons are allowed to be checked starting from the second digit. Therefore, in the mask register RM 14, permission is set for two bits BM=0011.

At the same time, in cycle 5, code 1101 of the fourth group G4 enters the data input ID, which is written in cycle 6 to the first R1 data register 5, and at the same time code 1100 from the outputs of the first R1 data register 5 is written to the second R2 data register 6, and also increases by unit value in counter 3 groups CTG=3. Therefore, further, code 1100 1101 is set on the internal 2m-bit data bus BD. At the same time, zero values are set at the outputs of all comparators 7 ₁ , 7 ₂ , …, 7 _m , code COMP=0000, since no match was found with the template IG=1011 . Therefore, a zero value of the match flag FE=0 is also formed, and in cycle 7 there is no entry in the output buffer OB 4.

At the same time, in cycle 7, by the zero value of the match flag FE=0, all bits of the mask register RM 14 are set to a single state, which are then transferred to the internal bus of the mask VM=1111 and allow the operation of the group of elements AND 8 ₁ , 8 ₂ , …, 8 _m .

In cycle 6, code 1101 of the fifth group G5 enters the data input ID, which is written in cycle 7 to the first R1 data register 5, and at the same time the code 1101 from the outputs of the first R1 data register 5 is written to the second R2 data register 6, and also increases by one the value in the counter 3 of groups CTG=4 and then on the internal 2m-bit data bus BD the code 1101 1101 is set. In this case, in the group of comparators 7 ₁ , 7 ₂ , …, 7 _m , a match with the template IG=1011 will be detected only in one group on the third comparator 7 ₃ and the code COMP=0100 is set, according to which the ordered single position row BC=0111 is set on the internal bus BC. Next, in the unit counting unit 10, the unit positional series BC=0111 is converted into a binary code BB=3 corresponding to the third digit of the identified template.

Further, with a single value of the match flag FE=1 in cycle 8, the code OB(2)=4_3 is written to the output buffer OB 4 at the second address, corresponding to the input fourth group G4 CTG=4 and the third digit of the beginning of the group corresponding to the given template IG=1011, which enters the internal bus BB=3. Also in step 8 is the account of the identified patterns on the counter 14 STK=3.

Further, in cycles 9 and 10, similarly to the considered algorithm, with single values of the coincidence flag FE=1, the recording is performed for the identified input fifth G5 and sixth G6 groups of the corresponding codes at the third OB(3)=5_3 and fourth OB(4)=6_1 addresses to the output buffer OB 4.

At the same time, in cycle 9, code 1011 of the eighth group G8 enters the ID data input, which is written in cycle 10 to the first R1 data register 5, and at the same time code 0110 from the outputs of the first R1 data register 5 is written to the second R2 data register 6, and also increases by unit value in counter 3 groups CTG=7. Further, code 0110 1011 is set on the internal 2m-bit data bus BD. At the same time, zero values are set at the outputs of all comparators 7 ₁ , 7 ₂ , …, 7 _m , code COMP=0000, since no matches with the pattern IG=1011 were found. Therefore, a zero value of the match flag FE=0 is also formed and in cycle 11 there is no entry in the output buffer OB 4. At the same time, in cycle 11, all bits of the mask register RM 14 are set to a single state, which are then transferred to the internal mask bus VM=1111 and allow operation groups of elements AND 8 ₁ , 8 ₂ , …, 8 _m .

At the same time, in cycle 10, a single signal STOP=1 is received, according to which, along the edge of the clock signal C in cycle 11, the first RS-trigger 1 start-stop TSS=0 is set to zero. In this case, the code 0110 from the data input ID for the ninth group G9 is written in cycle 11 to the first R1 data register 5, and at the same time the code 1011 for the eighth group G8 from the outputs of the first R1 data register 5 is written to the second R2 data register 6, and also increases by unit value in counter 3 groups CTG=8. In this case, in the group of comparators 7 ₁ , 7 ₂ , …, 7 _m , a match with the template IG=1011 will be detected in two groups on the first and fourth comparators 7 ₁ and 7 ₄ and the code COMP=1001 is generated at the outputs of the comparators. But since in cycle 11 the zero state is set in the first RS-trigger 1 start-stop TSS=0, it is forbidden to transfer values in the first (m-1) elements of the group AND 8 ₁ , 8 ₂ , …, 8 _(m-1) , i.e. detection is allowed only in the fourth comparator COMP 7 ₄ . Next, an ordered single positional row BC=1111 is installed on the internal bus BC, which is transferred to the units counting block 10, in which the single positional series BC=1111 is converted into a binary code BB=4 corresponding to the fourth digit of the detected template.

Further, with a single value of the match flag FE=1 in cycle 12, the code OB(5)=8_4 is written to the output buffer OB 4 at the fifth address, corresponding to the input eighth group G8 CTG=8 and the second bit of the beginning of the group corresponding to the specified template IG=1011, which comes from the internal bus BB=4. Also in cycle 12 is the account of the identified patterns on the counter 14 STK=6, which is transmitted to the group of external outputs of the number of identified patterns QK.

Thus, for the input N=32 bit binary number shown in FIG. 2 in the output buffer OB 4 are written at six addresses OB(0), ..., OB(5) numbers of input groups and codes of bit numbers corresponding to the location of the beginning of the templates in the groups corresponding to the given template IG=1011.

Reading the results to a group of external data outputs QB from the output buffer VO 4 is controlled by an external control bus EO. When implementing the output buffer VO 11 in the form of a dual-port FIFO memory, the exchange can be performed in the process of detecting groups, taking into account the values of the flags "Buffer empty" FZ and "Buffer full" FF.

Processing of the next input N bit binary number begins after a single signal START=1.

The proposed device can be used for hardware implementation of statistical tests developed by the Information Technology Laboratory of the National Institute of Standards and Technology (NIST, USA), the purpose of which is to determine the measure of randomness of binary sequences generated by random number generators. In particular, the proposed device implements a test for matching non-overlapping given patterns of m bits with groups from the input data also of m bits. In this case, if the pattern is not found, then the neighboring analyzed groups from the input data are shifted one bit forward, and if the pattern is found, then the neighboring group is moved to the bit following the found pattern. The goal is to identify random or pseudo-random number generators that generate too often given non-periodic patterns.

When processing the results of physical experiments, the proposed device provides the identification of non-periodic events (templates - a given group of sequences of single bits (events duration) and zero bits (intervals between them)) and event coordinates.

The above information allows us to conclude that the proposed device solves the problem and corresponds to the claimed technical result - the identification of non-overlapping patterns containing specified groups (sequences) of single and zero bits and their location in the input data groups.

Claims (17)

A device of a parallel-serial structure for detecting non-overlapping bit patterns contains an external m-bit data input ID, an external m-bit input of a given pattern IG, a group of external data outputs QB, a group of external outputs for the number of detected patterns QK, the first RS start-stop trigger TSS 1, second D-flip-flop TR2 delay 2, CTG group counter 3, output buffer OB 4, first R1 data register 5, second R2 data register 6, group of m comparators 7 ₁ , 7 ₂ , …, 7 _m , group of m elements AND 8 ₁ , 8 ₂ , …, 8 _m , a group of (m-1) elements OR 9 ₁ , 9 ₂ , …, 9 _(m-1) , unit count block 10, element AND 11, element OR-NOT 12, STK pattern counter 13 and RM mask register 14, and also introduced external inputs of asynchronous setting to zero state CLR, start device START, stop device STOP and clock input C, internal 2m-bit data bus BD, internal bus v-bit binary code of the beginning of the pattern in the group BB (where v =] log2 m[(greater integer)), internal m-bit line code line BC, internal m-bit line mask BM, internal match flag FE, external exchange control bus EO, external buffer full flag FF and buffer empty flag » FZ, moreover, the external input of the asynchronous zeroing CLR is connected to the corresponding inputs of the asynchronous zeroing CLR of the first RS start-stop flip-flop TSS 1 and the second delay D-latch TR2, The external clock input of device C is connected to the clock inputs C of the first RS start-stop flip-flop TSS 1, the second D-flip-flop TR2 of the delay 2, the CTG group counter 3, the output buffer OB 4, the first R1 data register 5, the second R2 data register 6, template counter STK 13 and mask register RM 14, the external start input of the START device is connected to the input S of the synchronous setting to a single state of the first RS start-stop trigger TSS 1 and to the inputs R of the synchronous setting to the zero state of the CTG counter of groups 3, the output buffer OB 4, the first R1 of the data register 5, the second R2 data register 6, pattern counter STK 13 and mask register RM 14, the external stop input of the STOP device is connected to the input R of the synchronous set to zero state of the first RS start-stop trigger TSS 1, moreover, the direct output of the first RS-trigger start-stop TSS 1 is connected to the D-input of the second trigger TR2 delay 2, with the inputs CE of enabling the operation of the first R1 data register 5, the second R2 data register 6, the mask register RM 14 and the third inputs of the first (m -1) elements AND groups 8 ₁ , 8 ₂ , …, 8 _(m-1) , the output of the second D-flip-flop TR2 of the delay is connected to the input CE of enabling the operation of the CTG counter of groups 3 and the first input of the element AND 11, the output of which is connected to the input of the CE of the permission to write to the output buffer OB 4 and the permission of the account of the CE of the counter of the CTC templates 13, the outputs of which are a group external outputs of the number of detected QK templates, moreover, the external m-bit input of the given template IG is connected to the first groups of inputs of all m comparators of the group 7 ₁ , 7 ₂ , …, 7 _m , the outputs of which are connected to the second inputs of the corresponding elements of the same name AND of the group 8 ₁ , 8 ₂ , …, 8 _m , the external m-bit data input ID is connected to the group of information D-inputs of the first R1 data register 5, the outputs of which are the corresponding bits, starting from the first to the m-th bit, of the internal data bus BD, and is also connected to the group of information D-inputs of the second R2 of data register 6, whose outputs are the corresponding bits from the (m+1)th to the 2mth bit, of the internal data bus BD, moreover, the bits of the internal data bus BD in groups of m bits, each of which begins with the (i+1)-th bit (i=1, ..., m), are connected to the second groups of inputs of the corresponding i-th comparators of the group 7 ₁ , 7 ₂ , …, 7 _m , the outputs of the first (m-1) elements AND of the group 8 ₁ , 8 ₂ , ..., 8 _(m-1) are connected to the first inputs of the same elements OR of the group 9 ₁ , 9 ₂ , ..., 9 _(m-1) , and the output of the last m-th element AND 8 _m is connected to the second input of the last element 9 _(m-1) , and is also the m-th bit of the internal bus code of the unit positional row VS, in which the bits, starting from the first to (m-1)-th discharge, are the outputs of the same name (m-1) elements OR group 9 ₁ , 9 ₂ , ..., 9 _(m-1) , in addition, the second inputs of the first (m-2) elements of the OR group 9 ₁ , 9 ₂ , …, 9 _(m-2) , starting from the first to the (m-2)-th elements, are connected to the outputs of the corresponding subsequent (m-2 ) OR elements of the group 9 ₂ , 9 ₃ , …, 9 _(m-1) , starting from the second to the (m-1)-th element, moreover, all m bits of the internal bus code of a single positional row BC are connected to the corresponding inputs of the units counting block 10, to the group of information D-inputs of the mask register RM 14 and to the inputs of the OR-NOT element 12, the direct output of which is an internal match flag FE and is connected to the second input of the AND element 11, and the inverse output of the OR NOT element 12 is connected to the input S of the synchronous setting to the single state of the mask register RM 14, in addition, the outputs of the mask register RM 14 are the corresponding bits of the same name of the internal m-bit bus of the VM mask, which are connected to the first inputs of the same m elements And groups 8 ₁ , 8 ₂ , ..., 8 _m , moreover, the outputs of the units counting block 10 are the corresponding bits of the internal bus of the binary code of the beginning of the template in the group BB, which is connected to the second group of information D-inputs of the output buffer OB 4, in which the first group of information D-inputs is connected to the outputs of the counter CTG groups 3, in addition, the output buffer OB 4 is also connected to the external exchange control bus EO, and the corresponding outputs of the output buffer OB 4 are a group of external data outputs QB and external flags "Buffer full" FF and "Buffer empty" FZ.

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