JPH0413851Y2 - - Google Patents

Description

[Detailed explanation of the invention] [Field of industrial application] This invention is aimed at estimating the law under which the pulse interval changes when the pulse interval changes in radar waves etc. The present invention relates to the pulse train correlation circuit used.

[Conventional technology]

Prior art in this field is Japanese Patent Application No. 53-84791 (Japanese Patent Application Laid-open No. 84791/1983) filed by the same applicant as the applicant
No. 55-11665) "Pulse Train Correlation Circuit" (hereinafter referred to as "earlier application"). FIG. 2 is an explanatory diagram showing the shape of the input pulse train to be processed, and the horizontal axis is the time t.
The number above the pulse is the pulse number, and the arrival time of the pulse with this pulse number is t ₁ ,
Pulse interval τ _{1 =} t ₂ − t ₁ , τ _{2 =} t ₃ − _{t 2} ,
It is represented by... Further, the frame period T is a period in which the same pattern of pulse intervals is repeated, and for example, t _n+i+1 −t _n+i =t _i+1 −t _i =τ _i . In the simplest pattern, all pulse intervals are equal, but for purposes such as avoiding interference, pulse trains with unequal intervals may be used, such as staggered pulse trains and jitter pulse trains.

The purpose of the correlation circuit is to perform autocorrelation processing on the input pulse train to obtain a first clue as to what law the input pulse train is generated under. FIG. 3 shows a pulse train correlation circuit disclosed in the earlier application, in which I is a pulse interval measuring circuit, R _1-1 ,...R _1-2o are the first register group, R _2-1 ,...R _{2 -2o} is the second register group,
S ₁ ,...S _2o is a subtraction circuit group, AV is an average calculation circuit,
C is a comparison circuit, CTL is a control circuit, T ₀ is an input terminal,
T ₁ ,...T _o are output terminals.

Next, the operation will be explained. The pulse interval measuring circuit I sequentially measures the pulse intervals τ ₁ , τ ₂ , ... of the pulse train input from the input terminal T ₀ , and assuming that the first measured value is τ ₁ , this is stored in the register R _{1 -1} , _R2-1 , and then store the measured pulse interval _τ2 , the contents ( _τ1 ) of registers _R1-1 , _R2-1 are stored in registers _R1-2 , _R2. After shifting to _-2 , τ ₂ is stored in registers R _1-1 and R _2-1 . By repeating such shifts and inputs, 2n pulse intervals τ ₁ , τ ₂ ...τ _2o become registers R _1-2o ,
R _1-(2o-1) ,...R ₁ and register R _2-2o , R _2-(2o-1) ,...
Input to _R2 .

Next, correlation processing is performed on the input 2n pulse intervals. As a first operation, the contents of the second register group R _2-1 to R _2-2o are shifted to the right by one register. That is, the content of R _2-2o (τ ₁ )
disappears, the content (τ ₂ ) of R _2-(2o-1) enters R _2-2o ,
In this way, the content of R _2-1 (τ _2o ) is entered into R _2-2 , and 0 is entered into R _2-1 . In this state, subtraction is performed using (2n-1) subtraction circuits S _2o to S ₂ excluding S ₁ , and the result is d _1,1 = |τ ₁ −τ ₂ |, d _1,2 = |
Average value of τ ₂ −τ ₃ |,...d _1,(2o-1) = |τ _(2o-1) −τ _2o |
d _1a =1/(2n-1) (d _1,1 +d _1,2 +...d _1,(2o-1) ) is obtained by the average calculation circuit AV and stored in register R _3-1 .

As the second stage operation, the second register group R _2-1
~R Shift the contents of _2-2o one more register to the right. As a result, registers R _2-1 , R _2-2 , R _2-3 ...
The contents of R _2-(2o-1) and R _2-2o are 0, 0, τ _2o ...τ ₄ , τ ₃ , and the (2n-2) outputs of the subtraction circuits S _2o to _{S 3} are each d _{2 ,1} = |τ ₁ −τ ₃ |, d _2,2 = |τ ₂ −τ ₄ |,...
d _2,(2o-2) = |τ _(2o-2) −τ _2o |, and the average value d _2a =
1/(2n-2) ( _d2,1 + _d2,2 +...+ _d2,(2o-2) ). Shift the contents d _1a of register R _3-1 to register R _3-2 and store d _2a in register R _3-1 . In this way,
Find the average of the absolute values of the subtraction until the second register group is shifted to the right by a total of n registers, and d _1a ,
The n values of d _2a ,...d _oa are stored in registers R _3-o , R _3-(o-1) ,
...Stored in R _3-2 and R _3-1 . The contents of this third register group R _3-1 , R _3-2 , ... R _3-o represent the correlation of pulse intervals, and the characteristics of the unevenly spaced pulse train can be determined by comparison in the comparator circuit C. can.

For example, comparator circuit C is the third register group.
The contents of R _3-1 , R _3-2 , ... R _3-o are compared in magnitude, the register holding the minimum value is detected, and the result is output to the output terminal. The amount of data shifted within the second register group R _2-1 , R _2-2 ,...R _2-2o when subtraction is performed to obtain the data input to the register holding the minimum value is incorrect. It should be equal to the frame period of equally spaced pulses.

[Problem that the invention attempts to solve]

Since the pulse correlation circuit of the earlier application is configured as described above, the number of calculations is large, and the pulse interval is the object of calculation and is represented as a multi-bit digital code. There was a problem with slow data processing speed.
Another problem is that performing parallel processing to improve processing speed requires complex and large-scale circuits.

This invention was made to solve the above-mentioned problems, and the purpose is to obtain a pulse train correlation circuit whose circuit configuration can be simplified.

[Means for solving problems]

In this invention, for the purpose of detecting the frame period of an irregularly spaced pulse train (T in Figure 2), it is not necessary to accurately calculate the autocorrelation function of the pulse intervals, and the state of change in the pulse intervals is the same. It is possible to determine that the parts where Taking advantage of the fact that it is possible to express the outline of the state of change in the pulse interval using a 1-bit sign (sign indicating whether it is 0 or negative), we can calculate the sign (sign of the difference between successive pulse intervals) If it is positive or 0, it is represented by a logical ``0'' bit, and if it is negative, it is represented by a logical ``1'' bit. Also, this sign is tentatively called an increase/decrease sign.)
The frame period was determined by extracting only the pulses, arranging them in the order of arrival of the pulses, and detecting mutually identical (or most similar) bit patterns in this arrangement.

[Effect]

Instead of using the pulse interval difference, only the sign of the pulse interval difference, that is, the increase/decrease sign (1 bit) is used, so the number of arithmetic circuits and registers is significantly reduced, the number of operations is reduced, and the processing speed is improved.
Furthermore, the amount of information to be stored is greatly reduced as one bit of data is stored, thereby reducing the number of registers and simplifying the circuit configuration.

〔Example〕

The drawings will be explained below. FIG. 1 is a block diagram showing an embodiment of this invention, in which T ₀ , I,
CTL, T ₁ , T ₂ , ...T _o indicate the same or equivalent parts as the same symbols in Fig. 3, RG _k and RG _k-1 are pulse interval registers, OP is an arithmetic circuit PR _o -PR ₁ is an n-bit CTL in the direction indicated by the arrow SV in the shift register.
is shifted one bit at a time under the control of
SR _o , SR _o-1 , ...SR ₂ , SR ₁ are each p-bit shift registers (this shift register has a total of n bits).
This is a shift register group including shift registers. ), the n shift registers are simultaneously shifted one bit at a time under the control of CTL in the direction indicated by arrow SH. In addition, these shift registers SR _o ,
SR _o-1 ,...SR ₂ , SR ₁ inputs are shift register PR _o
−PR is the respective output from the parallel output terminal of ₁ . Also, PC is a code matching circuit, and CO is a comparison circuit.

Assuming that the pulse train shown in Figure 2 is input, the first
The operation of the circuit shown in the figure will be explained. When the first pulse is input and then the second pulse is input, the pulse interval measuring circuit I measures τ ₁ and stores it in the register RG _k . Next, when the third pulse is input, circuit I measures τ ₂ and stores the contents of register RG _k (τ ₁ ) in the register.
After moving to RG _k-1 , τ ₂ is stored in register RG _k . The arithmetic circuit OP subtracts τ ₂ - _{τ 1} and only the sign of the subtraction result (this increase/decrease sign is S _1. S ₁
is one bit of logic "0" or "1") is input into the first bit position (PR _o ) of the shift register PR _o -PR ₁ . In this case, the shift register group
SR _o to SR ₁ are not shifted. The start of shifting of this shift register group will be described later.

Under the control of CTL, I, RG _k , RG _k-1 , and OP repeat the same operation, and the shift register PR _o - PR ₁ is shifted one bit at a time, and at the point where the input of the (n+1)th pulse ends, PR S ₁ for ₁ , S ₂ for PR ₂
(S ₂ is the sign of τ ₃ − τ ₂ , the same applies hereafter), ...PR _o-1 has
S _o is input to S _o-1 and PR _o . When all the inputs to the n bits of the shift registers PR _o -PR ₁ are completed in this way, shifting of the shift register group SR _o -SR ₁ is started, and the leftmost bits of each of the bits PR _o ,
PR _o-1 ,...PR ₂ , Contents of PR _{1 So} , _So-1 ,... S ₂ , S ₁
is input.

Next, S _o+1 is input to PR _o , S _o is shifted and input to PR _o-1 , S ₃ is shifted and input to PR ₂ , and S ₂ is shifted to PR ₁ . When input is input, shift register group SR _o ~ SR ₁ becomes 1 bit arrow all at once.
They are shifted in the direction of SH, and S _o+1 , S _o , . . . S ₃ and S ₂ are input to the leftmost bits, respectively.

If you start shifting the shift register group SR _o ~ SR ₁ and repeat data input from OP p times,
The contents of the p-bit shift registers SR ₁ to _{SR o} are (S ₁ , S ₂ , ...S _p ) for SR ₁ and (S 2 , ...S p ) for SR ₂ , respectively _.
(S ₂ , S ₃ ,...S _p+1 ), SR _o-1 is (S _o-1 , S _o ,...
S _o+p-2 ), SR _o becomes (S _o , S _o+1 ,...S _o+p-1 ).
At this time, shifting of shift register groups SR ₁ to _{SR o} is stopped.

One of the contents of SR ₁ to SR _o is temporarily set as a reference pattern. (For example, since the content of SR ₁ is the first pattern measured, the content of SR ₁ is used as the reference pattern).

The code matching circuit PC is a reference pattern (contents of SR ₁ )
In contrast, the number of logical matches of the bits of the bit patterns of the contents of other SR ₂ to _{SR o} is counted and sent to the comparator circuit CO. The comparator circuit CO determines the frame period by determining that the maximum number of bit logic matches (if all bits match, the number of bit logic matches is p) is the point with the same phase as SR ₁ . I can do it.

Note that the shift register PR _o −PR ₁ and the shift register group SR _o ~ SR ₁ are (S ₁ , S ₂ ,...S _{p-1 Sp} ), (S ₂ ,
To generate n bit patterns of p bits shifted by 1 bit, such as S ₃ ...S _p , S p ₊₁ ), (S ₃ , S ₄ , ...S _p+1 , S _p+2 ), ... Other circuits that can accomplish this purpose may be used.

Furthermore, in the embodiment shown in FIG. 1, (S ₁ ...S _p ), (S ₂
After generating a bit pattern such as (S _p+1 ), its sign is compared, and a bit logic match is detected every time an increase/decrease sign is generated, and a counter is used to count the number of times a bit logic match is detected. may be provided.

For example, in Figure 1, the shift register group
SR _o ~ SR ₁ is omitted, and PR ₁ is Si (however, 1 ip)
When S _i+1 is input to PR ₂ , S i _+o-2 is input to PR _o-1 , and S _i+o-1 is input to PR _o , S _i +1,...S _i+o-2 , S _i+o-1 is S _i
If the logic is the same as that of PR ₂ ,...PR _o-1 , PR _o, add 1 to the counters provided respectively, and input the n+p bit signal to shift register PR _o - PR ₁ . Comparison circuit for each counter's count value
You may also choose to compare using CO.

[Effect of idea]

As described above, according to this invention, since only the sign of the pulse interval difference is used to correlate pulse interval data, the circuit can be simplified and the processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is an explanatory diagram showing the shape of an input pulse train to be processed, and FIG. 3 is a block diagram showing a conventional circuit. I is the pulse interval measurement circuit, CTL is the control circuit,
OP is an arithmetic circuit, RG _k and RG _k-1 are pulse interval registers, PR _o -PR ₁ are n-bit shift registers,
SR _o to SR ₁ are a group of p-bit shift registers, PC is a code verification circuit, and CO is a comparison circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims for Utility Model Registration] Regarding the pulses of the pulse train that are input sequentially, from the pulse interval between the pulse input this time and the pulse input last time, it is possible to determine the difference between the pulse input last time and the pulse input before the previous time. means for generating a 1-bit increase/decrease sign by subtracting the pulse interval between the pulses, and when the result of the subtraction is positive or 0, it is expressed as a logic "0"; when the result of the subtraction is negative, it is expressed as a logic "1"; Continuous pulses of the above pulse train (n+p+
1) means for generating (n+p) bit increase/decrease codes corresponding to the inputs and arranging them in correspondence with the input order of pulses;
Means for extracting n types of bit patterns each consisting of consecutive p bits by shifting bits by bit; A pulse train correlation circuit with means for determining the most similar.