SU1437877A1 - Device for smoothing signals - Google Patents

Description

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The invention relates to computing and automation, and is primarily intended for use in digital information processing devices in digital measuring instruments and other devices for smoothing signals in noise and impulse noise.

The purpose of the invention is to increase the accuracy of smoothing signals in a sliding, processing mode by simultaneously suppressing impulse noise and a tum.

The drawing shows a block diagram of a device for smoothing signals.

The device contains a generator of I pulses 5 trigger 2, switch 3, the first adder 4, the first 5 and the second

6 registers, NOT 7 element, first 8 and

the second 9 elements AND, the generator Yu of random numbers, the block 11 for determining the order statistics, the second adder 12, the group I3 of switches from N switches, the group 14 of registers from AND registers, the element OR 15, the input 16 of setting the device bit.

Switches of group 3 switchboards. pass to the first outputs without changing the m most significant bits and zeroing the n – m least significant bits of the information code from their inputs, and n is the bit size of the elements of the sample being analyzed, and m is determined by information from the n-bit input 16 of the device. At the same time, the output of the first switch of group 13 receives m most significant bits of the input code with zeroing and nm the least significant bits of the input code without change, and the second output of the last switch of group 13 receives the code obtained by inverting the code consisting of m most significant zero. input code bits and nm low bits of the input code. The device input 16 is intended to select the ratio between the number of high order bits, the sampling elements used to suppress the impulse noise J, and the number of n-m least significant bits used to suppress noise. The second 6 registers, registers of register groups 14, switch groups of switch 13, block 11 for determining the order statistics and element 15 OR are n-bit switch 3 and the second adder 12 are n + 1 bit (K - defined

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It is derived from the relation), and the first 5 register and the first adder 4 are n -K-bit and -n.

In the device, the operation of dividing by a number is realized by dropping the K low bits of the dividend code.

The device works as follows.

At the input 16 of the device, an n-bit code is set, with the m most significant bits having 1. level, and the least significant bits nm - O level. As a result, in accordance with the control code at the input 16 of the device, ko; Mutators of the group of 13 switches skip to the first outputs without changing the L1 higher bits and zeroing the younger bits of the information code from their inputs. At the same time, the output of the higher bits of the first cohmutator of group 13 receives m old bits of the input code with zeroing and nm low-order bits of the input code without changing, and the output of the lower bits of the last switch of group 13 receives the code obtained by inverting the code consisting of m most significant bits of the input code with zeroing and nm the least significant bits of the input code without changing. According to the signal level 1 from the direct output of the trigger 2 in the block 1 1, the elements of the analyzed sample are ordered and input to its inputs from the corresponding outputs of the switch group 13, in order of their increase. Since 1 is an even number, to form pseudo-medians from the first and second codes of the block 1 1 from below: -1 K / 2-nd and N / 2 + I elements of an ordered sample, which are summed in n + 1-bit second adder 12 , By discarding one low bit of the code on the output of the adder 12, it is suspected that the sum obtained is divided by two. On the trailing edge of the pulse from the direct output of trigger 2, the pseudo-mediation code generated at the output of the adder 12 is written to the second register 6. The sample average is generated by shifting the averaging window by one element by subtracting the sample element from the code at the previous step and adding the resulting difference with the incoming item code. Inverted p-bit code

The output element is removed from the output of the last switch of switch group 13, and from the output of the first switch of switch group 13, the n-bit code of the incoming element is removed. The signal from the inverse output of the trigger 2 to the output of the n + 1-bit switch 3 receives either the inverted n-bit code of the outgoing element or the n-bit code of the received element. In this case, the n + 1th bit of the switch 3 is connected by a single-wire connection to the K senior bits of the second information at the end of the next clock cycle in the next state. In the registers of group 14 of registers, the code of the elements of the analyzed sample is recorded and the output of element 15 OR is smoothed in parallel with the code of the smoothed signal, Trigger 2 is in state O. B according to the logical 1 signal at the inverse output of trigger 2 at the output of adder 4 a code of slip code difference amount of window elements on the completed device operation cycle and code

The national input p + K-bit of the first-15 window element is retired to the next adder 4 and the signal of logical 1 is removed for the code of the retired element and the signal of logical o for the code of the incoming element. Subtraction

the overall tact of the device. On the leading edge of the odd pulse of the next clock cycle, 10 random numbers are generated at the generator output.

walks at the end of the next clock cycle in the next state. In the registers of group 14 of registers, the code of the elements of the analyzed sample is recorded and the output of element 15 OR is smoothed in parallel with the code of the smoothed signal, Trigger 2 is in state O. B according to the logical 1 signal at the inverse output of trigger 2 at the output of adder 4 a code of slip code difference amount of window elements on the completed device operation cycle and code

the overall tact of the device. On the leading edge of the odd pulse of the next clock cycle, 10 random numbers are generated at the generator output.

the code of the outgoing element from the code is an odd number due to the shifting of the sum of the sum of the forks and n (its window by one element. the world of the additional code on the trailing edge of the odd pulse based on the inverse code of the outgoing element and transfer input of the adder 4 of the logical 1 signal from the inverse output of the trigger 6. At the same time, the first information input n + K-ra is normal

the difference code is written from the output of adder 4 to register 5, as well as 25 the new number from the output of generator 10 is written to the first register of group 14 of registers with a shift in the contents of all registers. The number written in

adder 4 from the output of n + K-bit to the last register of group 14, the ter- rine of the first register 5 enters n + K-razo-zo. In registers group 14 registers

An odd sum code. On the falling edge of the clock pulse from the output of the generator 1, the difference code generated at the output of the adder 4 is written into register 5. After the output code of the resulting difference and the code of the incoming element is generated at the output of the adder 4, the trailing edge of the next clock pulse from the output of the generator 1 register 5 will write the sliding amount code at the new position of the sliding window. The sliding average at the output of the p + K-bit of the first register 5 is formed by dropping the K of the lower bits. In this case, the n most significant bits come together. With n-bits of the code at the output of the n-bit of the second second register 6 to the corresponding inputs of the element 15 OR. The OR operation in element 15 is performed on the input codes bitwise. As a result, the output of element 15 OR forms the code of the smoothed useful signal.

The device also operates in cycles consisting of half-pulses defined by pulses (odd and even). Suppose that the device has a new number due to the slip of the slides n (its windows by one element. On the trailing edge of the odd pulse

the difference code is written from the output of adder 4 to register 5, and 25 the new number is written from the output of generator 10 to the first register of group 14 of registers with a shift in the contents of all registers. The number written in

the codes of the elements of the analyzed sample are remembered at the new position of the sliding window. On the falling edge

an odd pulse also occurs

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1. As a result, at the output of the adder 4, a sliding code is formed, in block 11, in accordance with the control signal from the direct output of trigger 2, the sampling elements are arranged, and at the output of adder 12, the pseudo-median code is formed for a given position of the sliding window. On the falling edge

an even pulse resets the flip-flop 2 to the state O and writes the sliding sum code and sliding pseudo-media code for the specified window position to the first 5 and second 6 registers, respectively. From the output of the element OR 5, the code of the smoothed signal is removed. The operation cycle of the device is over. In the next cycle, the operation of the device is repeated.

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Claims (1)

Invention Formula A device for smoothing signals containing a pulse generator. The output of which is connected to the counting input of the trigger and to the input of receiving the code of the first register, whose information input is connected to the output of the adder's pair, the input of the first term of which is connected to the output of the first register, the input of the second term of the first adder is connected to the output of the switch The second register, characterized in that, in order to improve accuracy, due to the simultaneous suppression of impulse noise and noise, the device contains : the element is NOT, the two elements are And, the generator 15 groups are connected respectively with : random numbers, unit for determining the order statistics, the second adder / group of N switches (N sample size, even number), a group of N registers and the OR element, the output of the pulse generator is connected directly and through element 1Ш to the first inputs the first and second elements And, the second inputs of which are combined with the clock input of the first adder, with the control input of the switch and connected to the inversion output of the trigger, the direct output of which is connected to the synchronization input of the pore statistics determining unit and the input of the number of the second register, the output of the first element I is connected to the clock inputs of the group registers, the information outputs of the i-ro register are connected to the information inputs (i + l) -ro of the register (, N) and respectively to the information inputs of the i-ro switch the groups whose control inputs are combined and are the control input of the device, the first and second switch information inputs: connected to the low-order outputs of the first and N-ro switches of the group, the high-level outputs of the switches information inputs of the unit for determining the order statistics, outputs N / 2 and I / 2 + whose order statistics are connected respectively to the inputs of the first and second terms of the second adder, the output of which is connected to the information input of the second register, the output of which is connected to the first input of the OR element, the output of the first register is connected to the second input of the OR element, the output of which is the output of the device, the output of the second element AND is connected to the input of a random number generator, the output of which is connected to the information input of the first register of the register group.